stm32h7 0.16.0

///Register `EMR2` reader
pub type R = crate::R<EMR2rs>;
///Register `EMR2` writer
pub type W = crate::W<EMR2rs>;
///Field `MR32` reader - CPU event mask on event input i
pub type MR32_R = crate::BitReader;
///Field `MR32` writer - CPU event mask on event input i
pub type MR32_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR33` reader - CPU event mask on event input i
pub type MR33_R = crate::BitReader;
///Field `MR33` writer - CPU event mask on event input i
pub type MR33_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR34` reader - CPU event mask on event input i
pub type MR34_R = crate::BitReader;
///Field `MR34` writer - CPU event mask on event input i
pub type MR34_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR35` reader - CPU event mask on event input i
pub type MR35_R = crate::BitReader;
///Field `MR35` writer - CPU event mask on event input i
pub type MR35_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR36` reader - CPU event mask on event input i
pub type MR36_R = crate::BitReader;
///Field `MR36` writer - CPU event mask on event input i
pub type MR36_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR37` reader - CPU event mask on event input i
pub type MR37_R = crate::BitReader;
///Field `MR37` writer - CPU event mask on event input i
pub type MR37_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR38` reader - CPU event mask on event input i
pub type MR38_R = crate::BitReader;
///Field `MR38` writer - CPU event mask on event input i
pub type MR38_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR39` reader - CPU event mask on event input i
pub type MR39_R = crate::BitReader;
///Field `MR39` writer - CPU event mask on event input i
pub type MR39_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR40` reader - CPU event mask on event input i
pub type MR40_R = crate::BitReader;
///Field `MR40` writer - CPU event mask on event input i
pub type MR40_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR41` reader - CPU event mask on event input i
pub type MR41_R = crate::BitReader;
///Field `MR41` writer - CPU event mask on event input i
pub type MR41_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR42` reader - CPU event mask on event input i
pub type MR42_R = crate::BitReader;
///Field `MR42` writer - CPU event mask on event input i
pub type MR42_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR43` reader - CPU event mask on event input i
pub type MR43_R = crate::BitReader;
///Field `MR43` writer - CPU event mask on event input i
pub type MR43_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR44` reader - CPU event mask on event input i
pub type MR44_R = crate::BitReader;
///Field `MR44` writer - CPU event mask on event input i
pub type MR44_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR45` reader - CPU event mask on event input i
pub type MR45_R = crate::BitReader;
///Field `MR45` writer - CPU event mask on event input i
pub type MR45_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR46` reader - CPU event mask on event input i
pub type MR46_R = crate::BitReader;
///Field `MR46` writer - CPU event mask on event input i
pub type MR46_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR47` reader - CPU event mask on event input i
pub type MR47_R = crate::BitReader;
///Field `MR47` writer - CPU event mask on event input i
pub type MR47_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR48` reader - CPU event mask on event input i
pub type MR48_R = crate::BitReader;
///Field `MR48` writer - CPU event mask on event input i
pub type MR48_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR49` reader - CPU event mask on event input i
pub type MR49_R = crate::BitReader;
///Field `MR49` writer - CPU event mask on event input i
pub type MR49_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR50` reader - CPU event mask on event input i
pub type MR50_R = crate::BitReader;
///Field `MR50` writer - CPU event mask on event input i
pub type MR50_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR51` reader - CPU event mask on event input i
pub type MR51_R = crate::BitReader;
///Field `MR51` writer - CPU event mask on event input i
pub type MR51_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR52` reader - CPU event mask on event input i
pub type MR52_R = crate::BitReader;
///Field `MR52` writer - CPU event mask on event input i
pub type MR52_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR53` reader - CPU event mask on event input i
pub type MR53_R = crate::BitReader;
///Field `MR53` writer - CPU event mask on event input i
pub type MR53_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR54` reader - CPU event mask on event input i
pub type MR54_R = crate::BitReader;
///Field `MR54` writer - CPU event mask on event input i
pub type MR54_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR55` reader - CPU event mask on event input i
pub type MR55_R = crate::BitReader;
///Field `MR55` writer - CPU event mask on event input i
pub type MR55_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR56` reader - CPU event mask on event input i
pub type MR56_R = crate::BitReader;
///Field `MR56` writer - CPU event mask on event input i
pub type MR56_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR57` reader - CPU event mask on event input i
pub type MR57_R = crate::BitReader;
///Field `MR57` writer - CPU event mask on event input i
pub type MR57_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR58` reader - CPU event mask on event input i
pub type MR58_R = crate::BitReader;
///Field `MR58` writer - CPU event mask on event input i
pub type MR58_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `MR59` reader - CPU event mask on event input i
pub type MR59_R = crate::BitReader;
///Field `MR59` writer - CPU event mask on event input i
pub type MR59_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr32(&self) -> MR32_R {
        MR32_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr33(&self) -> MR33_R {
        MR33_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr34(&self) -> MR34_R {
        MR34_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr35(&self) -> MR35_R {
        MR35_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr36(&self) -> MR36_R {
        MR36_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr37(&self) -> MR37_R {
        MR37_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr38(&self) -> MR38_R {
        MR38_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 7 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr39(&self) -> MR39_R {
        MR39_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bit 8 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr40(&self) -> MR40_R {
        MR40_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr41(&self) -> MR41_R {
        MR41_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr42(&self) -> MR42_R {
        MR42_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 11 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr43(&self) -> MR43_R {
        MR43_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr44(&self) -> MR44_R {
        MR44_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr45(&self) -> MR45_R {
        MR45_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr46(&self) -> MR46_R {
        MR46_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr47(&self) -> MR47_R {
        MR47_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr48(&self) -> MR48_R {
        MR48_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr49(&self) -> MR49_R {
        MR49_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr50(&self) -> MR50_R {
        MR50_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 19 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr51(&self) -> MR51_R {
        MR51_R::new(((self.bits >> 19) & 1) != 0)
    }
    ///Bit 20 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr52(&self) -> MR52_R {
        MR52_R::new(((self.bits >> 20) & 1) != 0)
    }
    ///Bit 21 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr53(&self) -> MR53_R {
        MR53_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 22 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr54(&self) -> MR54_R {
        MR54_R::new(((self.bits >> 22) & 1) != 0)
    }
    ///Bit 23 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr55(&self) -> MR55_R {
        MR55_R::new(((self.bits >> 23) & 1) != 0)
    }
    ///Bit 24 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr56(&self) -> MR56_R {
        MR56_R::new(((self.bits >> 24) & 1) != 0)
    }
    ///Bit 25 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr57(&self) -> MR57_R {
        MR57_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 26 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr58(&self) -> MR58_R {
        MR58_R::new(((self.bits >> 26) & 1) != 0)
    }
    ///Bit 27 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr59(&self) -> MR59_R {
        MR59_R::new(((self.bits >> 27) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EMR2")
            .field("mr32", &self.mr32())
            .field("mr33", &self.mr33())
            .field("mr34", &self.mr34())
            .field("mr35", &self.mr35())
            .field("mr36", &self.mr36())
            .field("mr37", &self.mr37())
            .field("mr38", &self.mr38())
            .field("mr39", &self.mr39())
            .field("mr40", &self.mr40())
            .field("mr41", &self.mr41())
            .field("mr42", &self.mr42())
            .field("mr43", &self.mr43())
            .field("mr44", &self.mr44())
            .field("mr45", &self.mr45())
            .field("mr46", &self.mr46())
            .field("mr47", &self.mr47())
            .field("mr48", &self.mr48())
            .field("mr49", &self.mr49())
            .field("mr50", &self.mr50())
            .field("mr51", &self.mr51())
            .field("mr52", &self.mr52())
            .field("mr53", &self.mr53())
            .field("mr54", &self.mr54())
            .field("mr55", &self.mr55())
            .field("mr56", &self.mr56())
            .field("mr57", &self.mr57())
            .field("mr58", &self.mr58())
            .field("mr59", &self.mr59())
            .finish()
    }
}
impl W {
    ///Bit 0 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr32(&mut self) -> MR32_W<EMR2rs> {
        MR32_W::new(self, 0)
    }
    ///Bit 1 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr33(&mut self) -> MR33_W<EMR2rs> {
        MR33_W::new(self, 1)
    }
    ///Bit 2 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr34(&mut self) -> MR34_W<EMR2rs> {
        MR34_W::new(self, 2)
    }
    ///Bit 3 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr35(&mut self) -> MR35_W<EMR2rs> {
        MR35_W::new(self, 3)
    }
    ///Bit 4 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr36(&mut self) -> MR36_W<EMR2rs> {
        MR36_W::new(self, 4)
    }
    ///Bit 5 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr37(&mut self) -> MR37_W<EMR2rs> {
        MR37_W::new(self, 5)
    }
    ///Bit 6 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr38(&mut self) -> MR38_W<EMR2rs> {
        MR38_W::new(self, 6)
    }
    ///Bit 7 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr39(&mut self) -> MR39_W<EMR2rs> {
        MR39_W::new(self, 7)
    }
    ///Bit 8 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr40(&mut self) -> MR40_W<EMR2rs> {
        MR40_W::new(self, 8)
    }
    ///Bit 9 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr41(&mut self) -> MR41_W<EMR2rs> {
        MR41_W::new(self, 9)
    }
    ///Bit 10 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr42(&mut self) -> MR42_W<EMR2rs> {
        MR42_W::new(self, 10)
    }
    ///Bit 11 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr43(&mut self) -> MR43_W<EMR2rs> {
        MR43_W::new(self, 11)
    }
    ///Bit 12 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr44(&mut self) -> MR44_W<EMR2rs> {
        MR44_W::new(self, 12)
    }
    ///Bit 13 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr45(&mut self) -> MR45_W<EMR2rs> {
        MR45_W::new(self, 13)
    }
    ///Bit 14 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr46(&mut self) -> MR46_W<EMR2rs> {
        MR46_W::new(self, 14)
    }
    ///Bit 15 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr47(&mut self) -> MR47_W<EMR2rs> {
        MR47_W::new(self, 15)
    }
    ///Bit 16 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr48(&mut self) -> MR48_W<EMR2rs> {
        MR48_W::new(self, 16)
    }
    ///Bit 17 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr49(&mut self) -> MR49_W<EMR2rs> {
        MR49_W::new(self, 17)
    }
    ///Bit 18 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr50(&mut self) -> MR50_W<EMR2rs> {
        MR50_W::new(self, 18)
    }
    ///Bit 19 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr51(&mut self) -> MR51_W<EMR2rs> {
        MR51_W::new(self, 19)
    }
    ///Bit 20 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr52(&mut self) -> MR52_W<EMR2rs> {
        MR52_W::new(self, 20)
    }
    ///Bit 21 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr53(&mut self) -> MR53_W<EMR2rs> {
        MR53_W::new(self, 21)
    }
    ///Bit 22 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr54(&mut self) -> MR54_W<EMR2rs> {
        MR54_W::new(self, 22)
    }
    ///Bit 23 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr55(&mut self) -> MR55_W<EMR2rs> {
        MR55_W::new(self, 23)
    }
    ///Bit 24 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr56(&mut self) -> MR56_W<EMR2rs> {
        MR56_W::new(self, 24)
    }
    ///Bit 25 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr57(&mut self) -> MR57_W<EMR2rs> {
        MR57_W::new(self, 25)
    }
    ///Bit 26 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr58(&mut self) -> MR58_W<EMR2rs> {
        MR58_W::new(self, 26)
    }
    ///Bit 27 - CPU event mask on event input i
    #[inline(always)]
    pub fn mr59(&mut self) -> MR59_W<EMR2rs> {
        MR59_W::new(self, 27)
    }
}
/**EXTI event mask register

You can [`read`](crate::Reg::read) this register and get [`emr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct EMR2rs;
impl crate::RegisterSpec for EMR2rs {
    type Ux = u32;
}
///`read()` method returns [`emr2::R`](R) reader structure
impl crate::Readable for EMR2rs {}
///`write(|w| ..)` method takes [`emr2::W`](W) writer structure
impl crate::Writable for EMR2rs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets EMR2 to value 0
impl crate::Resettable for EMR2rs {}