stm32h7 0.16.0

Device support crates for STM32H7 devices
Documentation
///Register `INI1_WRITE_QOS` reader
pub type R = crate::R<INI1_WRITE_QOSrs>;
///Register `INI1_WRITE_QOS` writer
pub type W = crate::W<INI1_WRITE_QOSrs>;
///Field `AW_QOS` reader - Write channel QoS setting
pub type AW_QOS_R = crate::FieldReader;
///Field `AW_QOS` writer - Write channel QoS setting
pub type AW_QOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
impl R {
    ///Bits 0:3 - Write channel QoS setting
    #[inline(always)]
    pub fn aw_qos(&self) -> AW_QOS_R {
        AW_QOS_R::new((self.bits & 0x0f) as u8)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("INI1_WRITE_QOS").field("aw_qos", &self.aw_qos()).finish()
    }
}
impl W {
    ///Bits 0:3 - Write channel QoS setting
    #[inline(always)]
    pub fn aw_qos(&mut self) -> AW_QOS_W<INI1_WRITE_QOSrs> {
        AW_QOS_W::new(self, 0)
    }
}
/**AXI interconnect - INI x write QoS register

You can [`read`](crate::Reg::read) this register and get [`ini1_write_qos::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ini1_write_qos::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
pub struct INI1_WRITE_QOSrs;
impl crate::RegisterSpec for INI1_WRITE_QOSrs {
    type Ux = u32;
}
///`read()` method returns [`ini1_write_qos::R`](R) reader structure
impl crate::Readable for INI1_WRITE_QOSrs {}
///`write(|w| ..)` method takes [`ini1_write_qos::W`](W) writer structure
impl crate::Writable for INI1_WRITE_QOSrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets INI1_WRITE_QOS to value 0x04
impl crate::Resettable for INI1_WRITE_QOSrs {
    const RESET_VALUE: u32 = 0x04;
}