stm32g4 0.16.0

Device support crates for STM32G4 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263

///Register `APB2ENR` reader
pub type R = crate::R<APB2ENRrs>;
///Register `APB2ENR` writer
pub type W = crate::W<APB2ENRrs>;
/**SYSCFG + COMP + VREFBUF + OPAMP clock enable Set and cleared by software.

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SYSCFGEN {
    ///0: The selected clock is disabled
    Disabled = 0,
    ///1: The selected clock is enabled
    Enabled = 1,
}
impl From<SYSCFGEN> for bool {
    #[inline(always)]
    fn from(variant: SYSCFGEN) -> Self {
        variant as u8 != 0
    }
}
///Field `SYSCFGEN` reader - SYSCFG + COMP + VREFBUF + OPAMP clock enable Set and cleared by software.
pub type SYSCFGEN_R = crate::BitReader<SYSCFGEN>;
impl SYSCFGEN_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> SYSCFGEN {
        match self.bits {
            false => SYSCFGEN::Disabled,
            true => SYSCFGEN::Enabled,
        }
    }
    ///The selected clock is disabled
    #[inline(always)]
    pub fn is_disabled(&self) -> bool {
        *self == SYSCFGEN::Disabled
    }
    ///The selected clock is enabled
    #[inline(always)]
    pub fn is_enabled(&self) -> bool {
        *self == SYSCFGEN::Enabled
    }
}
///Field `SYSCFGEN` writer - SYSCFG + COMP + VREFBUF + OPAMP clock enable Set and cleared by software.
pub type SYSCFGEN_W<'a, REG> = crate::BitWriter<'a, REG, SYSCFGEN>;
impl<'a, REG> SYSCFGEN_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    ///The selected clock is disabled
    #[inline(always)]
    pub fn disabled(self) -> &'a mut crate::W<REG> {
        self.variant(SYSCFGEN::Disabled)
    }
    ///The selected clock is enabled
    #[inline(always)]
    pub fn enabled(self) -> &'a mut crate::W<REG> {
        self.variant(SYSCFGEN::Enabled)
    }
}
///Field `TIM1EN` reader - TIM1 timer clock enable Set and cleared by software.
pub use SYSCFGEN_R as TIM1EN_R;
///Field `SPI1EN` reader - SPI1 clock enable Set and cleared by software.
pub use SYSCFGEN_R as SPI1EN_R;
///Field `TIM8EN` reader - TIM8 timer clock enable Set and cleared by software.
pub use SYSCFGEN_R as TIM8EN_R;
///Field `USART1EN` reader - USART1clock enable Set and cleared by software.
pub use SYSCFGEN_R as USART1EN_R;
///Field `SPI4EN` reader - SPI4 clock enable Set and cleared by software.
pub use SYSCFGEN_R as SPI4EN_R;
///Field `TIM15EN` reader - TIM15 timer clock enable Set and cleared by software.
pub use SYSCFGEN_R as TIM15EN_R;
///Field `TIM16EN` reader - TIM16 timer clock enable Set and cleared by software.
pub use SYSCFGEN_R as TIM16EN_R;
///Field `TIM17EN` reader - TIM17 timer clock enable Set and cleared by software.
pub use SYSCFGEN_R as TIM17EN_R;
///Field `TIM20EN` reader - TIM20 timer clock enable Set and cleared by software.
pub use SYSCFGEN_R as TIM20EN_R;
///Field `SAI1EN` reader - SAI1 clock enable Set and cleared by software.
pub use SYSCFGEN_R as SAI1EN_R;
///Field `HRTIM1EN` reader - HRTIM1 clock enable Set and cleared by software.
pub use SYSCFGEN_R as HRTIM1EN_R;
///Field `TIM1EN` writer - TIM1 timer clock enable Set and cleared by software.
pub use SYSCFGEN_W as TIM1EN_W;
///Field `SPI1EN` writer - SPI1 clock enable Set and cleared by software.
pub use SYSCFGEN_W as SPI1EN_W;
///Field `TIM8EN` writer - TIM8 timer clock enable Set and cleared by software.
pub use SYSCFGEN_W as TIM8EN_W;
///Field `USART1EN` writer - USART1clock enable Set and cleared by software.
pub use SYSCFGEN_W as USART1EN_W;
///Field `SPI4EN` writer - SPI4 clock enable Set and cleared by software.
pub use SYSCFGEN_W as SPI4EN_W;
///Field `TIM15EN` writer - TIM15 timer clock enable Set and cleared by software.
pub use SYSCFGEN_W as TIM15EN_W;
///Field `TIM16EN` writer - TIM16 timer clock enable Set and cleared by software.
pub use SYSCFGEN_W as TIM16EN_W;
///Field `TIM17EN` writer - TIM17 timer clock enable Set and cleared by software.
pub use SYSCFGEN_W as TIM17EN_W;
///Field `TIM20EN` writer - TIM20 timer clock enable Set and cleared by software.
pub use SYSCFGEN_W as TIM20EN_W;
///Field `SAI1EN` writer - SAI1 clock enable Set and cleared by software.
pub use SYSCFGEN_W as SAI1EN_W;
///Field `HRTIM1EN` writer - HRTIM1 clock enable Set and cleared by software.
pub use SYSCFGEN_W as HRTIM1EN_W;
impl R {
    ///Bit 0 - SYSCFG + COMP + VREFBUF + OPAMP clock enable Set and cleared by software.
    #[inline(always)]
    pub fn syscfgen(&self) -> SYSCFGEN_R {
        SYSCFGEN_R::new((self.bits & 1) != 0)
    }
    ///Bit 11 - TIM1 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim1en(&self) -> TIM1EN_R {
        TIM1EN_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - SPI1 clock enable Set and cleared by software.
    #[inline(always)]
    pub fn spi1en(&self) -> SPI1EN_R {
        SPI1EN_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - TIM8 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim8en(&self) -> TIM8EN_R {
        TIM8EN_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - USART1clock enable Set and cleared by software.
    #[inline(always)]
    pub fn usart1en(&self) -> USART1EN_R {
        USART1EN_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - SPI4 clock enable Set and cleared by software.
    #[inline(always)]
    pub fn spi4en(&self) -> SPI4EN_R {
        SPI4EN_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - TIM15 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim15en(&self) -> TIM15EN_R {
        TIM15EN_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - TIM16 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim16en(&self) -> TIM16EN_R {
        TIM16EN_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - TIM17 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim17en(&self) -> TIM17EN_R {
        TIM17EN_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 20 - TIM20 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim20en(&self) -> TIM20EN_R {
        TIM20EN_R::new(((self.bits >> 20) & 1) != 0)
    }
    ///Bit 21 - SAI1 clock enable Set and cleared by software.
    #[inline(always)]
    pub fn sai1en(&self) -> SAI1EN_R {
        SAI1EN_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 26 - HRTIM1 clock enable Set and cleared by software.
    #[inline(always)]
    pub fn hrtim1en(&self) -> HRTIM1EN_R {
        HRTIM1EN_R::new(((self.bits >> 26) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("APB2ENR")
            .field("syscfgen", &self.syscfgen())
            .field("tim1en", &self.tim1en())
            .field("spi1en", &self.spi1en())
            .field("tim8en", &self.tim8en())
            .field("usart1en", &self.usart1en())
            .field("spi4en", &self.spi4en())
            .field("tim15en", &self.tim15en())
            .field("tim16en", &self.tim16en())
            .field("tim17en", &self.tim17en())
            .field("tim20en", &self.tim20en())
            .field("sai1en", &self.sai1en())
            .field("hrtim1en", &self.hrtim1en())
            .finish()
    }
}
impl W {
    ///Bit 0 - SYSCFG + COMP + VREFBUF + OPAMP clock enable Set and cleared by software.
    #[inline(always)]
    pub fn syscfgen(&mut self) -> SYSCFGEN_W<APB2ENRrs> {
        SYSCFGEN_W::new(self, 0)
    }
    ///Bit 11 - TIM1 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim1en(&mut self) -> TIM1EN_W<APB2ENRrs> {
        TIM1EN_W::new(self, 11)
    }
    ///Bit 12 - SPI1 clock enable Set and cleared by software.
    #[inline(always)]
    pub fn spi1en(&mut self) -> SPI1EN_W<APB2ENRrs> {
        SPI1EN_W::new(self, 12)
    }
    ///Bit 13 - TIM8 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim8en(&mut self) -> TIM8EN_W<APB2ENRrs> {
        TIM8EN_W::new(self, 13)
    }
    ///Bit 14 - USART1clock enable Set and cleared by software.
    #[inline(always)]
    pub fn usart1en(&mut self) -> USART1EN_W<APB2ENRrs> {
        USART1EN_W::new(self, 14)
    }
    ///Bit 15 - SPI4 clock enable Set and cleared by software.
    #[inline(always)]
    pub fn spi4en(&mut self) -> SPI4EN_W<APB2ENRrs> {
        SPI4EN_W::new(self, 15)
    }
    ///Bit 16 - TIM15 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim15en(&mut self) -> TIM15EN_W<APB2ENRrs> {
        TIM15EN_W::new(self, 16)
    }
    ///Bit 17 - TIM16 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim16en(&mut self) -> TIM16EN_W<APB2ENRrs> {
        TIM16EN_W::new(self, 17)
    }
    ///Bit 18 - TIM17 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim17en(&mut self) -> TIM17EN_W<APB2ENRrs> {
        TIM17EN_W::new(self, 18)
    }
    ///Bit 20 - TIM20 timer clock enable Set and cleared by software.
    #[inline(always)]
    pub fn tim20en(&mut self) -> TIM20EN_W<APB2ENRrs> {
        TIM20EN_W::new(self, 20)
    }
    ///Bit 21 - SAI1 clock enable Set and cleared by software.
    #[inline(always)]
    pub fn sai1en(&mut self) -> SAI1EN_W<APB2ENRrs> {
        SAI1EN_W::new(self, 21)
    }
    ///Bit 26 - HRTIM1 clock enable Set and cleared by software.
    #[inline(always)]
    pub fn hrtim1en(&mut self) -> HRTIM1EN_W<APB2ENRrs> {
        HRTIM1EN_W::new(self, 26)
    }
}
/**APB2 peripheral clock enable register

You can [`read`](crate::Reg::read) this register and get [`apb2enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G483.html#RCC:APB2ENR)*/
pub struct APB2ENRrs;
impl crate::RegisterSpec for APB2ENRrs {
    type Ux = u32;
}
///`read()` method returns [`apb2enr::R`](R) reader structure
impl crate::Readable for APB2ENRrs {}
///`write(|w| ..)` method takes [`apb2enr::W`](W) writer structure
impl crate::Writable for APB2ENRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets APB2ENR to value 0
impl crate::Resettable for APB2ENRrs {}