stm32g4-staging 0.22.0

Device support crates for STM32G4 devices
Documentation 
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///Register `TXBC` reader
pub type R = crate::R<TXBCrs>;
///Register `TXBC` writer
pub type W = crate::W<TXBCrs>;
///Field `TFQM` reader - Tx FIFO/queue mode This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 \[CCE\] and bit 0 \[INIT\] of CCCR register are set to 1.
pub type TFQM_R = crate::BitReader;
///Field `TFQM` writer - Tx FIFO/queue mode This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 \[CCE\] and bit 0 \[INIT\] of CCCR register are set to 1.
pub type TFQM_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 24 - Tx FIFO/queue mode This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 \[CCE\] and bit 0 \[INIT\] of CCCR register are set to 1.
    #[inline(always)]
    pub fn tfqm(&self) -> TFQM_R {
        TFQM_R::new(((self.bits >> 24) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TXBC").field("tfqm", &self.tfqm()).finish()
    }
}
impl W {
    ///Bit 24 - Tx FIFO/queue mode This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 \[CCE\] and bit 0 \[INIT\] of CCCR register are set to 1.
    #[inline(always)]
    pub fn tfqm(&mut self) -> TFQM_W<TXBCrs> {
        TFQM_W::new(self, 24)
    }
}
/**FDCAN Tx buffer configuration register

You can [`read`](crate::Reg::read) this register and get [`txbc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G441.html#FDCAN:TXBC)*/
pub struct TXBCrs;
impl crate::RegisterSpec for TXBCrs {
    type Ux = u32;
}
///`read()` method returns [`txbc::R`](R) reader structure
impl crate::Readable for TXBCrs {}
///`write(|w| ..)` method takes [`txbc::W`](W) writer structure
impl crate::Writable for TXBCrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets TXBC to value 0
impl crate::Resettable for TXBCrs {}