stm32g0 0.16.0

Device support crates for STM32G0 devices
Documentation 
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///Register `SIDR` reader
pub type R = crate::R<SIDRrs>;
///Field `ID` reader - Size Identification code
pub type ID_R = crate::FieldReader<u32>;
impl R {
    ///Bits 0:31 - Size Identification code
    #[inline(always)]
    pub fn id(&self) -> ID_R {
        ID_R::new(self.bits)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SIDR").field("id", &self.id()).finish()
    }
}
/**AES size ID register

You can [`read`](crate::Reg::read) this register and get [`sidr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#AES:SIDR)*/
pub struct SIDRrs;
impl crate::RegisterSpec for SIDRrs {
    type Ux = u32;
}
///`read()` method returns [`sidr::R`](R) reader structure
impl crate::Readable for SIDRrs {}
///`reset()` method sets SIDR to value 0x0017_0023
impl crate::Resettable for SIDRrs {
    const RESET_VALUE: u32 = 0x0017_0023;
}