#[doc = "Register `CR2` reader"]
pub struct R(crate::R<CR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR2` writer"]
pub struct W(crate::W<CR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "TI1 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TI1S_A {
#[doc = "0: The TIMx_CH1 pin is connected to TI1 input"]
Normal = 0,
#[doc = "1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
Xor = 1,
}
impl From<TI1S_A> for bool {
#[inline(always)]
fn from(variant: TI1S_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TI1S` reader - TI1 selection"]
pub type TI1S_R = crate::BitReader<TI1S_A>;
impl TI1S_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> TI1S_A {
match self.bits {
false => TI1S_A::Normal,
true => TI1S_A::Xor,
}
}
#[doc = "Checks if the value of the field is `Normal`"]
#[inline(always)]
pub fn is_normal(&self) -> bool {
*self == TI1S_A::Normal
}
#[doc = "Checks if the value of the field is `Xor`"]
#[inline(always)]
pub fn is_xor(&self) -> bool {
*self == TI1S_A::Xor
}
}
#[doc = "Field `TI1S` writer - TI1 selection"]
pub type TI1S_W<'a> = crate::BitWriter<'a, u32, CR2_SPEC, TI1S_A, 7>;
impl<'a> TI1S_W<'a> {
#[doc = "The TIMx_CH1 pin is connected to TI1 input"]
#[inline(always)]
pub fn normal(self) -> &'a mut W {
self.variant(TI1S_A::Normal)
}
#[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
#[inline(always)]
pub fn xor(self) -> &'a mut W {
self.variant(TI1S_A::Xor)
}
}
#[doc = "Master mode selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum MMS_A {
#[doc = "0: The UG bit from the TIMx_EGR register is used as trigger output"]
Reset = 0,
#[doc = "1: The counter enable signal, CNT_EN, is used as trigger output"]
Enable = 1,
#[doc = "2: The update event is selected as trigger output"]
Update = 2,
#[doc = "3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
ComparePulse = 3,
#[doc = "4: OC1REF signal is used as trigger output"]
CompareOc1 = 4,
#[doc = "5: OC2REF signal is used as trigger output"]
CompareOc2 = 5,
#[doc = "6: OC3REF signal is used as trigger output"]
CompareOc3 = 6,
#[doc = "7: OC4REF signal is used as trigger output"]
CompareOc4 = 7,
}
impl From<MMS_A> for u8 {
#[inline(always)]
fn from(variant: MMS_A) -> Self {
variant as _
}
}
#[doc = "Field `MMS` reader - Master mode selection"]
pub type MMS_R = crate::FieldReader<u8, MMS_A>;
impl MMS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> MMS_A {
match self.bits {
0 => MMS_A::Reset,
1 => MMS_A::Enable,
2 => MMS_A::Update,
3 => MMS_A::ComparePulse,
4 => MMS_A::CompareOc1,
5 => MMS_A::CompareOc2,
6 => MMS_A::CompareOc3,
7 => MMS_A::CompareOc4,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `Reset`"]
#[inline(always)]
pub fn is_reset(&self) -> bool {
*self == MMS_A::Reset
}
#[doc = "Checks if the value of the field is `Enable`"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == MMS_A::Enable
}
#[doc = "Checks if the value of the field is `Update`"]
#[inline(always)]
pub fn is_update(&self) -> bool {
*self == MMS_A::Update
}
#[doc = "Checks if the value of the field is `ComparePulse`"]
#[inline(always)]
pub fn is_compare_pulse(&self) -> bool {
*self == MMS_A::ComparePulse
}
#[doc = "Checks if the value of the field is `CompareOc1`"]
#[inline(always)]
pub fn is_compare_oc1(&self) -> bool {
*self == MMS_A::CompareOc1
}
#[doc = "Checks if the value of the field is `CompareOc2`"]
#[inline(always)]
pub fn is_compare_oc2(&self) -> bool {
*self == MMS_A::CompareOc2
}
#[doc = "Checks if the value of the field is `CompareOc3`"]
#[inline(always)]
pub fn is_compare_oc3(&self) -> bool {
*self == MMS_A::CompareOc3
}
#[doc = "Checks if the value of the field is `CompareOc4`"]
#[inline(always)]
pub fn is_compare_oc4(&self) -> bool {
*self == MMS_A::CompareOc4
}
}
#[doc = "Field `MMS` writer - Master mode selection"]
pub type MMS_W<'a> = crate::FieldWriterSafe<'a, u32, CR2_SPEC, u8, MMS_A, 3, 4>;
impl<'a> MMS_W<'a> {
#[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
#[inline(always)]
pub fn reset(self) -> &'a mut W {
self.variant(MMS_A::Reset)
}
#[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
#[inline(always)]
pub fn enable(self) -> &'a mut W {
self.variant(MMS_A::Enable)
}
#[doc = "The update event is selected as trigger output"]
#[inline(always)]
pub fn update(self) -> &'a mut W {
self.variant(MMS_A::Update)
}
#[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
#[inline(always)]
pub fn compare_pulse(self) -> &'a mut W {
self.variant(MMS_A::ComparePulse)
}
#[doc = "OC1REF signal is used as trigger output"]
#[inline(always)]
pub fn compare_oc1(self) -> &'a mut W {
self.variant(MMS_A::CompareOc1)
}
#[doc = "OC2REF signal is used as trigger output"]
#[inline(always)]
pub fn compare_oc2(self) -> &'a mut W {
self.variant(MMS_A::CompareOc2)
}
#[doc = "OC3REF signal is used as trigger output"]
#[inline(always)]
pub fn compare_oc3(self) -> &'a mut W {
self.variant(MMS_A::CompareOc3)
}
#[doc = "OC4REF signal is used as trigger output"]
#[inline(always)]
pub fn compare_oc4(self) -> &'a mut W {
self.variant(MMS_A::CompareOc4)
}
}
#[doc = "Capture/compare DMA selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCDS_A {
#[doc = "0: CCx DMA request sent when CCx event occurs"]
OnCompare = 0,
#[doc = "1: CCx DMA request sent when update event occurs"]
OnUpdate = 1,
}
impl From<CCDS_A> for bool {
#[inline(always)]
fn from(variant: CCDS_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCDS` reader - Capture/compare DMA selection"]
pub type CCDS_R = crate::BitReader<CCDS_A>;
impl CCDS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> CCDS_A {
match self.bits {
false => CCDS_A::OnCompare,
true => CCDS_A::OnUpdate,
}
}
#[doc = "Checks if the value of the field is `OnCompare`"]
#[inline(always)]
pub fn is_on_compare(&self) -> bool {
*self == CCDS_A::OnCompare
}
#[doc = "Checks if the value of the field is `OnUpdate`"]
#[inline(always)]
pub fn is_on_update(&self) -> bool {
*self == CCDS_A::OnUpdate
}
}
#[doc = "Field `CCDS` writer - Capture/compare DMA selection"]
pub type CCDS_W<'a> = crate::BitWriter<'a, u32, CR2_SPEC, CCDS_A, 3>;
impl<'a> CCDS_W<'a> {
#[doc = "CCx DMA request sent when CCx event occurs"]
#[inline(always)]
pub fn on_compare(self) -> &'a mut W {
self.variant(CCDS_A::OnCompare)
}
#[doc = "CCx DMA request sent when update event occurs"]
#[inline(always)]
pub fn on_update(self) -> &'a mut W {
self.variant(CCDS_A::OnUpdate)
}
}
impl R {
#[doc = "Bit 7 - TI1 selection"]
#[inline(always)]
pub fn ti1s(&self) -> TI1S_R {
TI1S_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 4:6 - Master mode selection"]
#[inline(always)]
pub fn mms(&self) -> MMS_R {
MMS_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 3 - Capture/compare DMA selection"]
#[inline(always)]
pub fn ccds(&self) -> CCDS_R {
CCDS_R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 7 - TI1 selection"]
#[inline(always)]
pub fn ti1s(&mut self) -> TI1S_W {
TI1S_W::new(self)
}
#[doc = "Bits 4:6 - Master mode selection"]
#[inline(always)]
pub fn mms(&mut self) -> MMS_W {
MMS_W::new(self)
}
#[doc = "Bit 3 - Capture/compare DMA selection"]
#[inline(always)]
pub fn ccds(&mut self) -> CCDS_W {
CCDS_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"]
pub struct CR2_SPEC;
impl crate::RegisterSpec for CR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr2::R](R) reader structure"]
impl crate::Readable for CR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"]
impl crate::Writable for CR2_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for CR2_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}