Struct stm32f4xx_hal::dma::StreamX

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pub struct StreamX<DMA, const S: u8> { /* private fields */ }

Expand description

Stream on the DMA controller.

Trait Implementations

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impl<I: Instance, const S: u8> Stream for StreamX<I, S> where
Self: Sealed + StreamISR,

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const NUMBER: usize = S as usize

Number of the register stream.

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fn set_peripheral_address(&mut self, value: u32)

Set the peripheral address (par) for the DMA stream.

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fn set_memory_address(&mut self, value: u32)

Set the memory address (m0ar) for the DMA stream.

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fn get_memory_address(&self) -> u32

Get the memory address (m0ar) for the DMA stream.

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fn set_memory_double_buffer_address(&mut self, value: u32)

Set the double buffer address (m1ar) for the DMA stream.

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fn get_memory_double_buffer_address(&self) -> u32

Get the double buffer address (m1ar) for the DMA stream.

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fn set_number_of_transfers(&mut self, value: u16)

Set the number of transfers (ndt) for the DMA stream.

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fn get_number_of_transfers() -> u16

Get the number of transfers (ndt) for the DMA stream.

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unsafe fn enable(&mut self)

Enable the DMA stream. Read more

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fn is_enabled() -> bool

Returns the state of the DMA stream.

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fn disable(&mut self)

Disable the DMA stream. Read more

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fn set_channel<const C: u8>(&mut self) where
ChannelX<C>: Channel,

Set the channel for the (chsel) the DMA stream.

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fn set_priority(&mut self, priority: Priority)

Set the priority (pl) the DMA stream.

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unsafe fn set_memory_size(&mut self, size: u8)

Set the memory size (msize) for the DMA stream. Read more

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unsafe fn set_peripheral_size(&mut self, size: u8)

Set the peripheral memory size (psize) for the DMA stream. Read more

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fn set_memory_increment(&mut self, increment: bool)

Enable/disable memory increment (minc) for the DMA stream.

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fn set_peripheral_increment(&mut self, increment: bool)

Enable/disable peripheral increment (pinc) for the DMA stream.

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fn set_direction<D: Direction>(&mut self, direction: D)

Set the direction (dir) of the DMA stream.

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fn set_interrupts_enable(
    &mut self,
    transfer_complete: bool,
    half_transfer: bool,
    transfer_error: bool,
    direct_mode_error: bool
)

Convenience method to configure the 4 common interrupts for the DMA stream.

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fn get_interrupts_enable() -> (bool, bool, bool, bool )

Convenience method to get the value of the 4 common interrupts for the DMA stream. The order of the returns are: transfer_complete, half_transfer, transfer_error and direct_mode_error. Read more

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fn set_transfer_complete_interrupt_enable(
&mut self,
transfer_complete_interrupt: bool
)

Enable/disable the transfer complete interrupt (tcie) of the DMA stream.

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fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool)

Enable/disable the half transfer interrupt (htie) of the DMA stream.

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fn set_transfer_error_interrupt_enable(
&mut self,
transfer_error_interrupt: bool
)

Enable/disable the transfer error interrupt (teie) of the DMA stream.

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fn set_direct_mode_error_interrupt_enable(
&mut self,
direct_mode_error_interrupt: bool
)

Enable/disable the direct mode error interrupt (dmeie) of the DMA stream.

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fn set_fifo_error_interrupt_enable(&mut self, fifo_error_interrupt: bool)

Enable/disable the fifo error interrupt (feie) of the DMA stream.

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fn set_double_buffer(&mut self, double_buffer: bool)

Enable/disable the double buffer (dbm) of the DMA stream.

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fn set_fifo_threshold(&mut self, fifo_threshold: FifoThreshold)

Set the fifo threshold (fcr.fth) of the DMA stream.

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fn set_fifo_enable(&mut self, fifo_enable: bool)

Enable/disable the fifo (dmdis) of the DMA stream.

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fn set_memory_burst(&mut self, memory_burst: BurstMode)

Set memory burst mode (mburst) of the DMA stream.

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fn set_peripheral_burst(&mut self, peripheral_burst: BurstMode)

Set peripheral burst mode (pburst) of the DMA stream.

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fn fifo_level() -> FifoLevel

Get the current fifo level (fs) of the DMA stream.

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fn current_buffer() -> CurrentBuffer

Get which buffer is currently in use by the DMA.

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impl<I: Instance> StreamISR for StreamX<I, 0> where
Self: Sealed,

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fn clear_interrupts(&mut self)

Clear all interrupts for the DMA stream.

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fn clear_transfer_complete_interrupt(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

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fn clear_half_transfer_interrupt(&mut self)

Clear half transfer interrupt (htif) for the DMA stream.

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fn clear_transfer_error_interrupt(&mut self)

Clear transfer error interrupt (teif) for the DMA stream.

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fn clear_direct_mode_error_interrupt(&mut self)

Clear direct mode error interrupt (dmeif) for the DMA stream.

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fn clear_fifo_error_interrupt(&mut self)

Clear fifo error interrupt (feif) for the DMA stream.

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fn get_transfer_complete_flag() -> bool

Get transfer complete flag.

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fn get_half_transfer_flag() -> bool

Get half transfer flag.

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fn get_transfer_error_flag() -> bool

Get transfer error flag

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fn get_fifo_error_flag() -> bool

Get fifo error flag

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fn get_direct_mode_error_flag() -> bool

Get direct mode error flag

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impl<I: Instance> StreamISR for StreamX<I, 1> where
Self: Sealed,

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fn clear_interrupts(&mut self)

Clear all interrupts for the DMA stream.

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fn clear_transfer_complete_interrupt(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

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fn clear_half_transfer_interrupt(&mut self)

Clear half transfer interrupt (htif) for the DMA stream.

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fn clear_transfer_error_interrupt(&mut self)

Clear transfer error interrupt (teif) for the DMA stream.

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fn clear_direct_mode_error_interrupt(&mut self)

Clear direct mode error interrupt (dmeif) for the DMA stream.

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fn clear_fifo_error_interrupt(&mut self)

Clear fifo error interrupt (feif) for the DMA stream.

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fn get_transfer_complete_flag() -> bool

Get transfer complete flag.

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fn get_half_transfer_flag() -> bool

Get half transfer flag.

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fn get_transfer_error_flag() -> bool

Get transfer error flag

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fn get_fifo_error_flag() -> bool

Get fifo error flag

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fn get_direct_mode_error_flag() -> bool

Get direct mode error flag

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impl<I: Instance> StreamISR for StreamX<I, 2> where
Self: Sealed,

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fn clear_interrupts(&mut self)

Clear all interrupts for the DMA stream.

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fn clear_transfer_complete_interrupt(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

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fn clear_half_transfer_interrupt(&mut self)

Clear half transfer interrupt (htif) for the DMA stream.

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fn clear_transfer_error_interrupt(&mut self)

Clear transfer error interrupt (teif) for the DMA stream.

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fn clear_direct_mode_error_interrupt(&mut self)

Clear direct mode error interrupt (dmeif) for the DMA stream.

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fn clear_fifo_error_interrupt(&mut self)

Clear fifo error interrupt (feif) for the DMA stream.

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fn get_transfer_complete_flag() -> bool

Get transfer complete flag.

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fn get_half_transfer_flag() -> bool

Get half transfer flag.

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fn get_transfer_error_flag() -> bool

Get transfer error flag

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fn get_fifo_error_flag() -> bool

Get fifo error flag

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fn get_direct_mode_error_flag() -> bool

Get direct mode error flag

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impl<I: Instance> StreamISR for StreamX<I, 3> where
Self: Sealed,

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fn clear_interrupts(&mut self)

Clear all interrupts for the DMA stream.

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fn clear_transfer_complete_interrupt(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

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fn clear_half_transfer_interrupt(&mut self)

Clear half transfer interrupt (htif) for the DMA stream.

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fn clear_transfer_error_interrupt(&mut self)

Clear transfer error interrupt (teif) for the DMA stream.

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fn clear_direct_mode_error_interrupt(&mut self)

Clear direct mode error interrupt (dmeif) for the DMA stream.

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fn clear_fifo_error_interrupt(&mut self)

Clear fifo error interrupt (feif) for the DMA stream.

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fn get_transfer_complete_flag() -> bool

Get transfer complete flag.

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fn get_half_transfer_flag() -> bool

Get half transfer flag.

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fn get_transfer_error_flag() -> bool

Get transfer error flag

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fn get_fifo_error_flag() -> bool

Get fifo error flag

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fn get_direct_mode_error_flag() -> bool

Get direct mode error flag

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impl<I: Instance> StreamISR for StreamX<I, 4> where
Self: Sealed,

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fn clear_interrupts(&mut self)

Clear all interrupts for the DMA stream.

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fn clear_transfer_complete_interrupt(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

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fn clear_half_transfer_interrupt(&mut self)

Clear half transfer interrupt (htif) for the DMA stream.

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fn clear_transfer_error_interrupt(&mut self)

Clear transfer error interrupt (teif) for the DMA stream.

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fn clear_direct_mode_error_interrupt(&mut self)

Clear direct mode error interrupt (dmeif) for the DMA stream.

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fn clear_fifo_error_interrupt(&mut self)

Clear fifo error interrupt (feif) for the DMA stream.

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fn get_transfer_complete_flag() -> bool

Get transfer complete flag.

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fn get_half_transfer_flag() -> bool

Get half transfer flag.

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fn get_transfer_error_flag() -> bool

Get transfer error flag

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fn get_fifo_error_flag() -> bool

Get fifo error flag

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fn get_direct_mode_error_flag() -> bool

Get direct mode error flag

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impl<I: Instance> StreamISR for StreamX<I, 5> where
Self: Sealed,

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fn clear_interrupts(&mut self)

Clear all interrupts for the DMA stream.

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fn clear_transfer_complete_interrupt(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

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fn clear_half_transfer_interrupt(&mut self)

Clear half transfer interrupt (htif) for the DMA stream.

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fn clear_transfer_error_interrupt(&mut self)

Clear transfer error interrupt (teif) for the DMA stream.

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fn clear_direct_mode_error_interrupt(&mut self)

Clear direct mode error interrupt (dmeif) for the DMA stream.

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fn clear_fifo_error_interrupt(&mut self)

Clear fifo error interrupt (feif) for the DMA stream.

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fn get_transfer_complete_flag() -> bool

Get transfer complete flag.

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fn get_half_transfer_flag() -> bool

Get half transfer flag.

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fn get_transfer_error_flag() -> bool

Get transfer error flag

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fn get_fifo_error_flag() -> bool

Get fifo error flag

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fn get_direct_mode_error_flag() -> bool

Get direct mode error flag

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impl<I: Instance> StreamISR for StreamX<I, 6> where
Self: Sealed,

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fn clear_interrupts(&mut self)

Clear all interrupts for the DMA stream.

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fn clear_transfer_complete_interrupt(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

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fn clear_half_transfer_interrupt(&mut self)

Clear half transfer interrupt (htif) for the DMA stream.

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fn clear_transfer_error_interrupt(&mut self)

Clear transfer error interrupt (teif) for the DMA stream.

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fn clear_direct_mode_error_interrupt(&mut self)

Clear direct mode error interrupt (dmeif) for the DMA stream.

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fn clear_fifo_error_interrupt(&mut self)

Clear fifo error interrupt (feif) for the DMA stream.

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fn get_transfer_complete_flag() -> bool

Get transfer complete flag.

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fn get_half_transfer_flag() -> bool

Get half transfer flag.

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fn get_transfer_error_flag() -> bool

Get transfer error flag

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fn get_fifo_error_flag() -> bool

Get fifo error flag

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fn get_direct_mode_error_flag() -> bool

Get direct mode error flag

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impl<I: Instance> StreamISR for StreamX<I, 7> where
Self: Sealed,

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fn clear_interrupts(&mut self)

Clear all interrupts for the DMA stream.

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fn clear_transfer_complete_interrupt(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

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fn clear_half_transfer_interrupt(&mut self)

Clear half transfer interrupt (htif) for the DMA stream.

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fn clear_transfer_error_interrupt(&mut self)

Clear transfer error interrupt (teif) for the DMA stream.

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fn clear_direct_mode_error_interrupt(&mut self)

Clear direct mode error interrupt (dmeif) for the DMA stream.

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fn clear_fifo_error_interrupt(&mut self)

Clear fifo error interrupt (feif) for the DMA stream.

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fn get_transfer_complete_flag() -> bool

Get transfer complete flag.

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fn get_half_transfer_flag() -> bool

Get half transfer flag.

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fn get_transfer_error_flag() -> bool

Get transfer error flag

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fn get_fifo_error_flag() -> bool

Get fifo error flag

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fn get_direct_mode_error_flag() -> bool

Get direct mode error flag

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impl DMASet<StreamX<DMA2, 0_u8>, 0_u8, MemoryToMemory<u16>> for MemoryToMemory<u16>

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impl DMASet<StreamX<DMA2, 0_u8>, 0_u8, MemoryToMemory<u32>> for MemoryToMemory<u32>

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impl DMASet<StreamX<DMA2, 0_u8>, 0_u8, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 0_u8>, 0_u8, PeripheralToMemory> for ADC1

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impl DMASet<StreamX<DMA2, 0_u8>, 0_u8, PeripheralToMemory> for Adc<ADC1>

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impl DMASet<StreamX<DMA2, 0_u8>, 2_u8, PeripheralToMemory> for ADC3

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impl DMASet<StreamX<DMA2, 0_u8>, 2_u8, PeripheralToMemory> for Adc<ADC3>

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impl DMASet<StreamX<DMA2, 0_u8>, 3_u8, PeripheralToMemory> for SPI1

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impl DMASet<StreamX<DMA2, 0_u8>, 3_u8, PeripheralToMemory> for Rx<SPI1>

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impl DMASet<StreamX<DMA2, 0_u8>, 4_u8, PeripheralToMemory> for SPI4

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impl DMASet<StreamX<DMA2, 0_u8>, 4_u8, PeripheralToMemory> for Rx<SPI4>

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impl DMASet<StreamX<DMA2, 0_u8>, 6_u8, MemoryToPeripheral> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 0_u8>, 6_u8, PeripheralToMemory> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 1_u8>, 0_u8, MemoryToMemory<u16>> for MemoryToMemory<u16>

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impl DMASet<StreamX<DMA2, 1_u8>, 0_u8, MemoryToMemory<u32>> for MemoryToMemory<u32>

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impl DMASet<StreamX<DMA2, 1_u8>, 0_u8, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 1_u8>, 1_u8, PeripheralToMemory> for DCMI

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impl DMASet<StreamX<DMA2, 1_u8>, 2_u8, PeripheralToMemory> for ADC3

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impl DMASet<StreamX<DMA2, 1_u8>, 2_u8, PeripheralToMemory> for Adc<ADC3>

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impl DMASet<StreamX<DMA2, 1_u8>, 4_u8, MemoryToPeripheral> for SPI4

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impl DMASet<StreamX<DMA2, 1_u8>, 4_u8, MemoryToPeripheral> for Tx<SPI4>

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impl DMASet<StreamX<DMA2, 1_u8>, 5_u8, PeripheralToMemory> for USART6

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impl DMASet<StreamX<DMA2, 1_u8>, 5_u8, PeripheralToMemory> for Rx<USART6>

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impl DMASet<StreamX<DMA2, 1_u8>, 6_u8, MemoryToPeripheral> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 1_u8>, 6_u8, PeripheralToMemory> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 1_u8>, 7_u8, MemoryToPeripheral> for DMAR<TIM8>

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impl DMASet<StreamX<DMA2, 1_u8>, 7_u8, PeripheralToMemory> for DMAR<TIM8>

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impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, MemoryToMemory<u16>> for MemoryToMemory<u16>

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impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, MemoryToMemory<u32>> for MemoryToMemory<u32>

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impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, MemoryToPeripheral> for CCR1<TIM8>

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impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, MemoryToPeripheral> for CCR2<TIM8>

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impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, MemoryToPeripheral> for CCR3<TIM8>

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impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, PeripheralToMemory> for CCR1<TIM8>

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impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, PeripheralToMemory> for CCR2<TIM8>

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impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, PeripheralToMemory> for CCR3<TIM8>

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impl DMASet<StreamX<DMA2, 2_u8>, 1_u8, PeripheralToMemory> for ADC2

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impl DMASet<StreamX<DMA2, 2_u8>, 1_u8, PeripheralToMemory> for Adc<ADC3>

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impl DMASet<StreamX<DMA2, 2_u8>, 3_u8, PeripheralToMemory> for SPI1

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impl DMASet<StreamX<DMA2, 2_u8>, 3_u8, PeripheralToMemory> for Rx<SPI1>

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impl DMASet<StreamX<DMA2, 2_u8>, 4_u8, PeripheralToMemory> for USART1

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impl DMASet<StreamX<DMA2, 2_u8>, 4_u8, PeripheralToMemory> for Rx<USART1>

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impl DMASet<StreamX<DMA2, 2_u8>, 5_u8, PeripheralToMemory> for USART6

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impl DMASet<StreamX<DMA2, 2_u8>, 5_u8, PeripheralToMemory> for Rx<USART6>

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impl DMASet<StreamX<DMA2, 2_u8>, 6_u8, MemoryToPeripheral> for CCR2<TIM1>

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impl DMASet<StreamX<DMA2, 2_u8>, 6_u8, PeripheralToMemory> for CCR2<TIM1>

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impl DMASet<StreamX<DMA2, 2_u8>, 7_u8, MemoryToPeripheral> for CCR1<TIM8>

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impl DMASet<StreamX<DMA2, 2_u8>, 7_u8, PeripheralToMemory> for CCR1<TIM8>

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impl DMASet<StreamX<DMA2, 3_u8>, 0_u8, MemoryToMemory<u16>> for MemoryToMemory<u16>

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impl DMASet<StreamX<DMA2, 3_u8>, 0_u8, MemoryToMemory<u32>> for MemoryToMemory<u32>

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impl DMASet<StreamX<DMA2, 3_u8>, 0_u8, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 3_u8>, 1_u8, PeripheralToMemory> for ADC2

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impl DMASet<StreamX<DMA2, 3_u8>, 1_u8, PeripheralToMemory> for Adc<ADC3>

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impl DMASet<StreamX<DMA2, 3_u8>, 2_u8, PeripheralToMemory> for SPI5

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impl DMASet<StreamX<DMA2, 3_u8>, 2_u8, PeripheralToMemory> for Rx<SPI5>

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impl DMASet<StreamX<DMA2, 3_u8>, 3_u8, MemoryToPeripheral> for SPI1

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impl DMASet<StreamX<DMA2, 3_u8>, 3_u8, MemoryToPeripheral> for Tx<SPI1>

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impl DMASet<StreamX<DMA2, 3_u8>, 4_u8, MemoryToPeripheral> for SDIO

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impl DMASet<StreamX<DMA2, 3_u8>, 4_u8, PeripheralToMemory> for SDIO

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impl DMASet<StreamX<DMA2, 3_u8>, 5_u8, PeripheralToMemory> for SPI4

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impl DMASet<StreamX<DMA2, 3_u8>, 5_u8, PeripheralToMemory> for Rx<SPI4>

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impl DMASet<StreamX<DMA2, 3_u8>, 6_u8, MemoryToPeripheral> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 3_u8>, 6_u8, PeripheralToMemory> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 3_u8>, 7_u8, MemoryToPeripheral> for CCR2<TIM8>

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impl DMASet<StreamX<DMA2, 3_u8>, 7_u8, PeripheralToMemory> for CCR2<TIM8>

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impl DMASet<StreamX<DMA2, 4_u8>, 0_u8, MemoryToMemory<u16>> for MemoryToMemory<u16>

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impl DMASet<StreamX<DMA2, 4_u8>, 0_u8, MemoryToMemory<u32>> for MemoryToMemory<u32>

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impl DMASet<StreamX<DMA2, 4_u8>, 0_u8, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 4_u8>, 0_u8, PeripheralToMemory> for ADC1

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impl DMASet<StreamX<DMA2, 4_u8>, 2_u8, MemoryToPeripheral> for SPI5

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impl DMASet<StreamX<DMA2, 4_u8>, 2_u8, MemoryToPeripheral> for Tx<SPI5>

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impl DMASet<StreamX<DMA2, 4_u8>, 5_u8, MemoryToPeripheral> for SPI4

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impl DMASet<StreamX<DMA2, 4_u8>, 5_u8, MemoryToPeripheral> for Tx<SPI4>

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impl DMASet<StreamX<DMA2, 4_u8>, 6_u8, MemoryToPeripheral> for CCR4<TIM1>

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impl DMASet<StreamX<DMA2, 4_u8>, 6_u8, MemoryToPeripheral> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 4_u8>, 6_u8, PeripheralToMemory> for CCR4<TIM1>

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impl DMASet<StreamX<DMA2, 4_u8>, 6_u8, PeripheralToMemory> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 4_u8>, 7_u8, MemoryToPeripheral> for CCR3<TIM8>

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impl DMASet<StreamX<DMA2, 4_u8>, 7_u8, PeripheralToMemory> for CCR3<TIM8>

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impl DMASet<StreamX<DMA2, 5_u8>, 0_u8, MemoryToMemory<u16>> for MemoryToMemory<u16>

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impl DMASet<StreamX<DMA2, 5_u8>, 0_u8, MemoryToMemory<u32>> for MemoryToMemory<u32>

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impl DMASet<StreamX<DMA2, 5_u8>, 0_u8, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 5_u8>, 1_u8, MemoryToPeripheral> for SPI6

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impl DMASet<StreamX<DMA2, 5_u8>, 1_u8, MemoryToPeripheral> for Tx<SPI6>

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impl DMASet<StreamX<DMA2, 5_u8>, 2_u8, PeripheralToMemory> for CRYP

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impl DMASet<StreamX<DMA2, 5_u8>, 3_u8, MemoryToPeripheral> for SPI1

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impl DMASet<StreamX<DMA2, 5_u8>, 3_u8, MemoryToPeripheral> for Tx<SPI1>

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impl DMASet<StreamX<DMA2, 5_u8>, 4_u8, PeripheralToMemory> for USART1

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impl DMASet<StreamX<DMA2, 5_u8>, 4_u8, PeripheralToMemory> for Rx<USART1>

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impl DMASet<StreamX<DMA2, 5_u8>, 6_u8, MemoryToPeripheral> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 5_u8>, 6_u8, PeripheralToMemory> for DMAR<TIM1>

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impl DMASet<StreamX<DMA2, 5_u8>, 7_u8, PeripheralToMemory> for SPI5

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impl DMASet<StreamX<DMA2, 5_u8>, 7_u8, PeripheralToMemory> for Rx<SPI5>

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impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, MemoryToMemory<u16>> for MemoryToMemory<u16>

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impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, MemoryToMemory<u32>> for MemoryToMemory<u32>

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impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, MemoryToPeripheral> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, MemoryToPeripheral> for CCR2<TIM1>

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impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, MemoryToPeripheral> for CCR3<TIM1>

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impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, PeripheralToMemory> for CCR1<TIM1>

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impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, PeripheralToMemory> for CCR2<TIM1>

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impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, PeripheralToMemory> for CCR3<TIM1>

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impl DMASet<StreamX<DMA2, 6_u8>, 1_u8, PeripheralToMemory> for SPI6

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impl DMASet<StreamX<DMA2, 6_u8>, 1_u8, PeripheralToMemory> for Rx<SPI6>

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impl DMASet<StreamX<DMA2, 6_u8>, 2_u8, MemoryToPeripheral> for CRYP

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impl DMASet<StreamX<DMA2, 6_u8>, 4_u8, MemoryToPeripheral> for SDIO

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impl DMASet<StreamX<DMA2, 6_u8>, 4_u8, PeripheralToMemory> for SDIO

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impl DMASet<StreamX<DMA2, 6_u8>, 5_u8, MemoryToPeripheral> for USART6

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impl DMASet<StreamX<DMA2, 6_u8>, 5_u8, MemoryToPeripheral> for Tx<USART6>

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impl DMASet<StreamX<DMA2, 6_u8>, 6_u8, MemoryToPeripheral> for CCR3<TIM1>

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impl DMASet<StreamX<DMA2, 6_u8>, 6_u8, PeripheralToMemory> for CCR3<TIM1>

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impl DMASet<StreamX<DMA2, 6_u8>, 7_u8, MemoryToPeripheral> for SPI5

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impl DMASet<StreamX<DMA2, 6_u8>, 7_u8, MemoryToPeripheral> for Tx<SPI5>

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impl DMASet<StreamX<DMA2, 7_u8>, 0_u8, MemoryToMemory<u16>> for MemoryToMemory<u16>

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impl DMASet<StreamX<DMA2, 7_u8>, 0_u8, MemoryToMemory<u32>> for MemoryToMemory<u32>

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impl DMASet<StreamX<DMA2, 7_u8>, 0_u8, MemoryToMemory<u8>> for MemoryToMemory<u8>

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impl DMASet<StreamX<DMA2, 7_u8>, 1_u8, PeripheralToMemory> for DCMI

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impl DMASet<StreamX<DMA2, 7_u8>, 2_u8, MemoryToPeripheral> for HASH

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impl DMASet<StreamX<DMA2, 7_u8>, 4_u8, MemoryToPeripheral> for USART1

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impl DMASet<StreamX<DMA2, 7_u8>, 4_u8, MemoryToPeripheral> for Tx<USART1>

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impl DMASet<StreamX<DMA2, 7_u8>, 5_u8, MemoryToPeripheral> for USART6

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impl DMASet<StreamX<DMA2, 7_u8>, 5_u8, MemoryToPeripheral> for Tx<USART6>

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impl DMASet<StreamX<DMA2, 7_u8>, 7_u8, MemoryToPeripheral> for CCR4<TIM8>

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impl DMASet<StreamX<DMA2, 7_u8>, 7_u8, MemoryToPeripheral> for DMAR<TIM8>

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impl DMASet<StreamX<DMA2, 7_u8>, 7_u8, PeripheralToMemory> for CCR4<TIM8>

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impl DMASet<StreamX<DMA2, 7_u8>, 7_u8, PeripheralToMemory> for DMAR<TIM8>

Auto Trait Implementations

impl<DMA, const S: u8> RefUnwindSafe for StreamX<DMA, S> where
DMA: RefUnwindSafe,

impl<DMA, const S: u8> Send for StreamX<DMA, S> where
DMA: Send,

impl<DMA, const S: u8> Sync for StreamX<DMA, S> where
DMA: Sync,

impl<DMA, const S: u8> Unpin for StreamX<DMA, S> where
DMA: Unpin,

impl<DMA, const S: u8> UnwindSafe for StreamX<DMA, S> where
DMA: UnwindSafe,

Blanket Implementations

source

impl<T> Any for T where
T: 'static + ?Sized,

source

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

source

impl<T> Borrow<T> for T where
T: ?Sized,

const: unstable · source

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

source

impl<T> BorrowMut<T> for T where
T: ?Sized,

const: unstable · source

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

source

impl<T> From<T> for T

const: unstable · source

fn from(t: T) -> T

Returns the argument unchanged.

source

impl<T, U> Into for T where
U: From<T>,

const: unstable · source

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

source

impl<T> Same<T> for T

type Output = T

Should always be Self

source

impl<T, U> TryFrom for T where
U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

const: unstable · source

fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

source

impl<T, U> TryInto for T where
U: TryFrom<T>,

type Error = >::Error

The type returned in the event of a conversion error.

const: unstable · source

fn try_into(self) -> Result<U, >::Error>

Performs the conversion.

Struct stm32f4xx_hal::dma::StreamX

Trait Implementations

impl<I: Instance, const S: u8> Stream for StreamX<I, S> where Self: Sealed + StreamISR,

const NUMBER: usize = S as usize

fn set_peripheral_address(&mut self, value: u32)

fn set_memory_address(&mut self, value: u32)

fn get_memory_address(&self) -> u32

fn set_memory_double_buffer_address(&mut self, value: u32)

fn get_memory_double_buffer_address(&self) -> u32

fn set_number_of_transfers(&mut self, value: u16)

fn get_number_of_transfers() -> u16

unsafe fn enable(&mut self)

fn is_enabled() -> bool

fn disable(&mut self)

fn set_channel<const C: u8>(&mut self) where ChannelX<C>: Channel,

fn set_priority(&mut self, priority: Priority)

unsafe fn set_memory_size(&mut self, size: u8)

unsafe fn set_peripheral_size(&mut self, size: u8)

fn set_memory_increment(&mut self, increment: bool)

fn set_peripheral_increment(&mut self, increment: bool)

fn set_direction<D: Direction>(&mut self, direction: D)

fn set_interrupts_enable( &mut self, transfer_complete: bool, half_transfer: bool, transfer_error: bool, direct_mode_error: bool)

fn get_interrupts_enable() -> (bool, bool, bool, bool)

fn set_transfer_complete_interrupt_enable( &mut self, transfer_complete_interrupt: bool)

fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool)

fn set_transfer_error_interrupt_enable( &mut self, transfer_error_interrupt: bool)

fn set_direct_mode_error_interrupt_enable( &mut self, direct_mode_error_interrupt: bool)

fn set_fifo_error_interrupt_enable(&mut self, fifo_error_interrupt: bool)

fn set_double_buffer(&mut self, double_buffer: bool)

fn set_fifo_threshold(&mut self, fifo_threshold: FifoThreshold)

fn set_fifo_enable(&mut self, fifo_enable: bool)

fn set_memory_burst(&mut self, memory_burst: BurstMode)

fn set_peripheral_burst(&mut self, peripheral_burst: BurstMode)

fn fifo_level() -> FifoLevel

fn current_buffer() -> CurrentBuffer

impl<I: Instance> StreamISR for StreamX<I, 0> where Self: Sealed,

fn clear_interrupts(&mut self)

fn clear_transfer_complete_interrupt(&mut self)

fn clear_half_transfer_interrupt(&mut self)

fn clear_transfer_error_interrupt(&mut self)

fn clear_direct_mode_error_interrupt(&mut self)

fn clear_fifo_error_interrupt(&mut self)

fn get_transfer_complete_flag() -> bool

fn get_half_transfer_flag() -> bool

fn get_transfer_error_flag() -> bool

fn get_fifo_error_flag() -> bool

fn get_direct_mode_error_flag() -> bool

impl<I: Instance> StreamISR for StreamX<I, 1> where Self: Sealed,

fn clear_interrupts(&mut self)

fn clear_transfer_complete_interrupt(&mut self)

fn clear_half_transfer_interrupt(&mut self)

fn clear_transfer_error_interrupt(&mut self)

fn clear_direct_mode_error_interrupt(&mut self)

fn clear_fifo_error_interrupt(&mut self)

fn get_transfer_complete_flag() -> bool

fn get_half_transfer_flag() -> bool

fn get_transfer_error_flag() -> bool

fn get_fifo_error_flag() -> bool

fn get_direct_mode_error_flag() -> bool

impl<I: Instance> StreamISR for StreamX<I, 2> where Self: Sealed,

fn clear_interrupts(&mut self)

fn clear_transfer_complete_interrupt(&mut self)

fn clear_half_transfer_interrupt(&mut self)

fn clear_transfer_error_interrupt(&mut self)

fn clear_direct_mode_error_interrupt(&mut self)

fn clear_fifo_error_interrupt(&mut self)

fn get_transfer_complete_flag() -> bool

fn get_half_transfer_flag() -> bool

fn get_transfer_error_flag() -> bool

fn get_fifo_error_flag() -> bool

fn get_direct_mode_error_flag() -> bool

impl<I: Instance> StreamISR for StreamX<I, 3> where Self: Sealed,

fn clear_interrupts(&mut self)

fn clear_transfer_complete_interrupt(&mut self)

fn clear_half_transfer_interrupt(&mut self)

fn clear_transfer_error_interrupt(&mut self)

fn clear_direct_mode_error_interrupt(&mut self)

fn clear_fifo_error_interrupt(&mut self)

fn get_transfer_complete_flag() -> bool

fn get_half_transfer_flag() -> bool

impl<I: Instance, const S: u8> Stream for StreamX<I, S> where
Self: Sealed + StreamISR,

fn set_channel<const C: u8>(&mut self) where
ChannelX<C>: Channel,

fn set_interrupts_enable(
&mut self,
transfer_complete: bool,
half_transfer: bool,
transfer_error: bool,
direct_mode_error: bool
)

fn get_interrupts_enable() -> (bool, bool, bool, bool )

fn set_transfer_complete_interrupt_enable(
&mut self,
transfer_complete_interrupt: bool
)

fn set_transfer_error_interrupt_enable(
&mut self,
transfer_error_interrupt: bool
)

fn set_direct_mode_error_interrupt_enable(
&mut self,
direct_mode_error_interrupt: bool
)

impl<I: Instance> StreamISR for StreamX<I, 0> where
Self: Sealed,

impl<I: Instance> StreamISR for StreamX<I, 1> where
Self: Sealed,

impl<I: Instance> StreamISR for StreamX<I, 2> where
Self: Sealed,

impl<I: Instance> StreamISR for StreamX<I, 3> where
Self: Sealed,

impl<I: Instance> StreamISR for StreamX<I, 4> where
Self: Sealed,

impl<I: Instance> StreamISR for StreamX<I, 5> where
Self: Sealed,

impl<I: Instance> StreamISR for StreamX<I, 6> where
Self: Sealed,

impl<I: Instance> StreamISR for StreamX<I, 7> where
Self: Sealed,