Module stm32f4xx_hal::dma
source · [−]Expand description
Direct Memory Access.
Transfer::init is only implemented for valid combinations of peripheral-stream-channel-direction, providing compile time checking.
This module implements Memory To Memory, Peripheral To Memory and Memory to Peripheral transfers, double buffering is supported only for Peripheral To Memory and Memory to Peripheral transfers.
Modules
Structs
A Channel that can be configured on a DMA stream.
DMA from one memory location to another memory location.
DMA from a memory location to a peripheral.
DMA from a peripheral to a memory location.
Stream on the DMA controller.
Alias for a tuple with all DMA streams.
DMA Transfer.
Enums
Which DMA buffer is in use.
Errors.
Possible DMA’s directions.
How full the DMA stream’s fifo is.
Type Definitions
Stream 0 on the DMA controller.
Stream 1 on the DMA controller.
Stream 2 on the DMA controller.
Stream 3 on the DMA controller.
Stream 4 on the DMA controller.
Stream 5 on the DMA controller.
Stream 6 on the DMA controller.
Stream 7 on the DMA controller.