Struct stm32f4xx_hal::dma::StreamX

pub struct StreamX<DMA, const S: u8> { /* private fields */ }

Stream on the DMA controller.

Trait Implementations

impl<I: Instance> ClearFlags for StreamX<I, 0>

type Flag = DmaFlag

Enum of manually clearable flags

fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>)

Clear interrupts flags with Self::Flagss

fn clear_all_flags(&mut self)

Clears all interrupts flags

impl<I: Instance> ClearFlags for StreamX<I, 1>

type Flag = DmaFlag

Enum of manually clearable flags

fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>)

Clear interrupts flags with Self::Flagss

fn clear_all_flags(&mut self)

Clears all interrupts flags

impl<I: Instance> ClearFlags for StreamX<I, 2>

type Flag = DmaFlag

Enum of manually clearable flags

fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>)

Clear interrupts flags with Self::Flagss

fn clear_all_flags(&mut self)

Clears all interrupts flags

impl<I: Instance> ClearFlags for StreamX<I, 3>

type Flag = DmaFlag

Enum of manually clearable flags

fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>)

Clear interrupts flags with Self::Flagss

fn clear_all_flags(&mut self)

Clears all interrupts flags

impl<I: Instance> ClearFlags for StreamX<I, 4>

type Flag = DmaFlag

Enum of manually clearable flags

fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>)

Clear interrupts flags with Self::Flagss

fn clear_all_flags(&mut self)

Clears all interrupts flags

impl<I: Instance> ClearFlags for StreamX<I, 5>

type Flag = DmaFlag

Enum of manually clearable flags

fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>)

Clear interrupts flags with Self::Flagss

fn clear_all_flags(&mut self)

Clears all interrupts flags

impl<I: Instance> ClearFlags for StreamX<I, 6>

type Flag = DmaFlag

Enum of manually clearable flags

fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>)

Clear interrupts flags with Self::Flagss

fn clear_all_flags(&mut self)

Clears all interrupts flags

impl<I: Instance> ClearFlags for StreamX<I, 7>

type Flag = DmaFlag

Enum of manually clearable flags

fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>)

Clear interrupts flags with Self::Flagss

fn clear_all_flags(&mut self)

Clears all interrupts flags

impl<I: Instance, const S: u8> Listen for StreamX<I, S>

where Self: Sealed + StreamISR,

type Event = DmaEvent

Enum of bit flags associated with events

fn listen(&mut self, interrupts: impl Into<BitFlags<DmaEvent>>)

Start listening for Events

fn listen_only(&mut self, interrupts: impl Into<BitFlags<DmaEvent>>)

Start listening for Events, stop all other

fn unlisten(&mut self, interrupts: impl Into<BitFlags<DmaEvent>>)

Stop listening for Events

fn listen_all(&mut self)

Start listening all Events

fn unlisten_all(&mut self)

Stop listening all Events

impl<I: Instance> ReadFlags for StreamX<I, 0>

type Flag = DmaFlag

Enum of bit flags

fn flags(&self) -> BitFlags<DmaFlag>

Get all interrupts flags a once.

impl<I: Instance> ReadFlags for StreamX<I, 1>

type Flag = DmaFlag

Enum of bit flags

fn flags(&self) -> BitFlags<DmaFlag>

Get all interrupts flags a once.

impl<I: Instance> ReadFlags for StreamX<I, 2>

type Flag = DmaFlag

Enum of bit flags

fn flags(&self) -> BitFlags<DmaFlag>

Get all interrupts flags a once.

impl<I: Instance> ReadFlags for StreamX<I, 3>

type Flag = DmaFlag

Enum of bit flags

fn flags(&self) -> BitFlags<DmaFlag>

Get all interrupts flags a once.

impl<I: Instance> ReadFlags for StreamX<I, 4>

type Flag = DmaFlag

Enum of bit flags

fn flags(&self) -> BitFlags<DmaFlag>

Get all interrupts flags a once.

impl<I: Instance> ReadFlags for StreamX<I, 5>

type Flag = DmaFlag

Enum of bit flags

fn flags(&self) -> BitFlags<DmaFlag>

Get all interrupts flags a once.

impl<I: Instance> ReadFlags for StreamX<I, 6>

type Flag = DmaFlag

Enum of bit flags

fn flags(&self) -> BitFlags<DmaFlag>

Get all interrupts flags a once.

impl<I: Instance> ReadFlags for StreamX<I, 7>

type Flag = DmaFlag

Enum of bit flags

fn flags(&self) -> BitFlags<DmaFlag>

Get all interrupts flags a once.

impl<I: Instance, const S: u8> Stream for StreamX<I, S>

where Self: Sealed + StreamISR,

const NUMBER: usize = _

Number of the register stream.

fn set_peripheral_address(&mut self, value: u32)

Set the peripheral address (par) of the DMA stream.

fn set_memory_address(&mut self, value: u32)

Set the memory address (m0ar) of the DMA stream.

fn memory_address(&self) -> u32

Get the memory address (m0ar) of the DMA stream.

fn set_alternate_memory_address(&mut self, value: u32)

Set the second memory address (m1ar) of the DMA stream. Only relevant with double buffer mode.

fn alternate_memory_address(&self) -> u32

Get the second memory address (m1ar) of the DMA stream. Only relevant with double buffer mode.

fn set_number_of_transfers(&mut self, value: u16)

Set the number of transfers (ndt) for the DMA stream.

fn number_of_transfers(&self) -> u16

Get the number of transfers (ndt) for the DMA stream.

unsafe fn enable(&mut self)

Enable the DMA stream.

fn is_enabled(&self) -> bool

Returns the state of the DMA stream.

unsafe fn disable(&mut self)

Disable the DMA stream.

fn set_channel(&mut self, channel: DmaChannel)

Set the channel for the (chsel) the DMA stream.

fn set_priority(&mut self, priority: Priority)

Set the priority (pl) the DMA stream.

fn set_peripheral_increment_offset(&mut self, value: PeripheralIncrementOffset)

Set the peripheral increment offset (pincos)

unsafe fn set_memory_size(&mut self, size: DmaDataSize)

Set the memory size (msize) for the DMA stream.

unsafe fn set_peripheral_size(&mut self, size: DmaDataSize)

Set the peripheral memory size (psize) for the DMA stream.

fn set_memory_increment(&mut self, increment: bool)

Enable/disable memory increment (minc) for the DMA stream.

fn set_peripheral_increment(&mut self, increment: bool)

Enable/disable peripheral increment (pinc) for the DMA stream.

fn set_circular_mode(&mut self, value: bool)

Enable/disable circular mode (circ) for the DMA stream.

fn set_direction(&mut self, direction: DmaDirection)

Set the direction (dir) of the DMA stream.

fn set_flow_controller(&mut self, value: DmaFlowController)

Set the flow controller (pfctrl).

fn events(&self) -> BitFlags<DmaEvent>

Convenience method to get the value of several interrupts of the DMA stream. The order of the returns are: transfer_complete, half_transfer, transfer_error and direct_mode_error

fn listen_fifo_error(&mut self)

Enable the fifo error interrupt (feie) of the DMA stream.

fn unlisten_fifo_error(&mut self)

Disable the fifo error interrupt (feie) of the DMA stream.

fn set_double_buffer(&mut self, double_buffer: bool)

Enable/disable the double buffer (dbm) of the DMA stream.

fn set_fifo_threshold(&mut self, fifo_threshold: FifoThreshold)

Set the fifo threshold (fcr.fth) of the DMA stream.

fn set_fifo_enable(&mut self, fifo_enable: bool)

Enable/disable the fifo (dmdis) of the DMA stream.

fn set_memory_burst(&mut self, memory_burst: BurstMode)

Set memory burst mode (mburst) of the DMA stream.

fn set_peripheral_burst(&mut self, peripheral_burst: BurstMode)

Set peripheral burst mode (pburst) of the DMA stream.

fn fifo_level(&self) -> FifoLevel

Get the current fifo level (fs) of the DMA stream.

fn current_buffer(&self) -> CurrentBuffer

Get which buffer is currently in use by the DMA.

fn listen_transfer_complete(&mut self)

Enable the transfer complete interrupt (tcie) of the DMA stream.

fn unlisten_transfer_complete(&mut self)

Disable the transfer complete interrupt (tcie) of the DMA stream.

fn listen_half_transfer(&mut self)

Enable the half transfer interrupt (htie) of the DMA stream.

fn unlisten_half_transfer(&mut self)

Disable the half transfer interrupt (htie) of the DMA stream.

fn listen_transfer_error(&mut self)

Enable the transfer error interrupt (teie) of the DMA stream.

fn unlisten_transfer_error(&mut self)

Disable the transfer error interrupt (teie) of the DMA stream.

fn listen_direct_mode_error(&mut self)

Enable the direct mode error interrupt (dmeie) of the DMA stream.

fn unlisten_direct_mode_error(&mut self)

Disable the direct mode error interrupt (dmeie) of the DMA stream.

impl<I: Instance> StreamISR for StreamX<I, 0>

fn clear_transfer_complete(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

fn clear_half_transfer(&mut self)

Clear half transfer interrupt flag (htif) for the DMA stream.

fn clear_transfer_error(&mut self)

Clear transfer error interrupt flag (teif) for the DMA stream.

fn clear_direct_mode_error(&mut self)

Clear direct mode error interrupt flag (dmeif) for the DMA stream.

fn clear_fifo_error(&mut self)

Clear fifo error interrupt flag (feif) for the DMA stream.

fn is_transfer_complete(&self) -> bool

Get transfer complete flag.

fn is_half_transfer(&self) -> bool

Get half transfer flag.

fn is_transfer_error(&self) -> bool

Get transfer error flag

fn is_direct_mode_error(&self) -> bool

Get direct mode error flag

fn is_fifo_error(&self) -> bool

Get fifo error flag

impl<I: Instance> StreamISR for StreamX<I, 1>

fn clear_transfer_complete(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

fn clear_half_transfer(&mut self)

Clear half transfer interrupt flag (htif) for the DMA stream.

fn clear_transfer_error(&mut self)

Clear transfer error interrupt flag (teif) for the DMA stream.

fn clear_direct_mode_error(&mut self)

Clear direct mode error interrupt flag (dmeif) for the DMA stream.

fn clear_fifo_error(&mut self)

Clear fifo error interrupt flag (feif) for the DMA stream.

fn is_transfer_complete(&self) -> bool

Get transfer complete flag.

fn is_half_transfer(&self) -> bool

Get half transfer flag.

fn is_transfer_error(&self) -> bool

Get transfer error flag

fn is_direct_mode_error(&self) -> bool

Get direct mode error flag

fn is_fifo_error(&self) -> bool

Get fifo error flag

impl<I: Instance> StreamISR for StreamX<I, 2>

fn clear_transfer_complete(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

fn clear_half_transfer(&mut self)

Clear half transfer interrupt flag (htif) for the DMA stream.

fn clear_transfer_error(&mut self)

Clear transfer error interrupt flag (teif) for the DMA stream.

fn clear_direct_mode_error(&mut self)

Clear direct mode error interrupt flag (dmeif) for the DMA stream.

fn clear_fifo_error(&mut self)

Clear fifo error interrupt flag (feif) for the DMA stream.

fn is_transfer_complete(&self) -> bool

Get transfer complete flag.

fn is_half_transfer(&self) -> bool

Get half transfer flag.

fn is_transfer_error(&self) -> bool

Get transfer error flag

fn is_direct_mode_error(&self) -> bool

Get direct mode error flag

fn is_fifo_error(&self) -> bool

Get fifo error flag

impl<I: Instance> StreamISR for StreamX<I, 3>

fn clear_transfer_complete(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

fn clear_half_transfer(&mut self)

Clear half transfer interrupt flag (htif) for the DMA stream.

fn clear_transfer_error(&mut self)

Clear transfer error interrupt flag (teif) for the DMA stream.

fn clear_direct_mode_error(&mut self)

Clear direct mode error interrupt flag (dmeif) for the DMA stream.

fn clear_fifo_error(&mut self)

Clear fifo error interrupt flag (feif) for the DMA stream.

fn is_transfer_complete(&self) -> bool

Get transfer complete flag.

fn is_half_transfer(&self) -> bool

Get half transfer flag.

fn is_transfer_error(&self) -> bool

Get transfer error flag

fn is_direct_mode_error(&self) -> bool

Get direct mode error flag

fn is_fifo_error(&self) -> bool

Get fifo error flag

impl<I: Instance> StreamISR for StreamX<I, 4>

fn clear_transfer_complete(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

fn clear_half_transfer(&mut self)

Clear half transfer interrupt flag (htif) for the DMA stream.

fn clear_transfer_error(&mut self)

Clear transfer error interrupt flag (teif) for the DMA stream.

fn clear_direct_mode_error(&mut self)

Clear direct mode error interrupt flag (dmeif) for the DMA stream.

fn clear_fifo_error(&mut self)

Clear fifo error interrupt flag (feif) for the DMA stream.

fn is_transfer_complete(&self) -> bool

Get transfer complete flag.

fn is_half_transfer(&self) -> bool

Get half transfer flag.

fn is_transfer_error(&self) -> bool

Get transfer error flag

fn is_direct_mode_error(&self) -> bool

Get direct mode error flag

fn is_fifo_error(&self) -> bool

Get fifo error flag

impl<I: Instance> StreamISR for StreamX<I, 5>

fn clear_transfer_complete(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

fn clear_half_transfer(&mut self)

Clear half transfer interrupt flag (htif) for the DMA stream.

fn clear_transfer_error(&mut self)

Clear transfer error interrupt flag (teif) for the DMA stream.

fn clear_direct_mode_error(&mut self)

Clear direct mode error interrupt flag (dmeif) for the DMA stream.

fn clear_fifo_error(&mut self)

Clear fifo error interrupt flag (feif) for the DMA stream.

fn is_transfer_complete(&self) -> bool

Get transfer complete flag.

fn is_half_transfer(&self) -> bool

Get half transfer flag.

fn is_transfer_error(&self) -> bool

Get transfer error flag

fn is_direct_mode_error(&self) -> bool

Get direct mode error flag

fn is_fifo_error(&self) -> bool

Get fifo error flag

impl<I: Instance> StreamISR for StreamX<I, 6>

fn clear_transfer_complete(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

fn clear_half_transfer(&mut self)

Clear half transfer interrupt flag (htif) for the DMA stream.

fn clear_transfer_error(&mut self)

Clear transfer error interrupt flag (teif) for the DMA stream.

fn clear_direct_mode_error(&mut self)

Clear direct mode error interrupt flag (dmeif) for the DMA stream.

fn clear_fifo_error(&mut self)

Clear fifo error interrupt flag (feif) for the DMA stream.

fn is_transfer_complete(&self) -> bool

Get transfer complete flag.

fn is_half_transfer(&self) -> bool

Get half transfer flag.

fn is_transfer_error(&self) -> bool

Get transfer error flag

fn is_direct_mode_error(&self) -> bool

Get direct mode error flag

fn is_fifo_error(&self) -> bool

Get fifo error flag

impl<I: Instance> StreamISR for StreamX<I, 7>

fn clear_transfer_complete(&mut self)

Clear transfer complete interrupt (tcif) for the DMA stream.

fn clear_half_transfer(&mut self)

Clear half transfer interrupt flag (htif) for the DMA stream.

fn clear_transfer_error(&mut self)

Clear transfer error interrupt flag (teif) for the DMA stream.

fn clear_direct_mode_error(&mut self)

Clear direct mode error interrupt flag (dmeif) for the DMA stream.

fn clear_fifo_error(&mut self)

Clear fifo error interrupt flag (feif) for the DMA stream.

fn is_transfer_complete(&self) -> bool

Get transfer complete flag.

fn is_half_transfer(&self) -> bool

Get half transfer flag.

fn is_transfer_error(&self) -> bool

Get transfer error flag

fn is_direct_mode_error(&self) -> bool

Get direct mode error flag

fn is_fifo_error(&self) -> bool

Get fifo error flag

impl DMASet<StreamX<DMA1, 0>, 0, PeripheralToMemory> for SPI3

impl DMASet<StreamX<DMA1, 0>, 1, PeripheralToMemory> for I2C1

impl DMASet<StreamX<DMA1, 0>, 2, MemoryToPeripheral> for CCR1<TIM4>

impl DMASet<StreamX<DMA1, 0>, 2, PeripheralToMemory> for CCR1<TIM4>

impl DMASet<StreamX<DMA1, 0>, 4, PeripheralToMemory> for UART5

impl DMASet<StreamX<DMA1, 0>, 5, MemoryToPeripheral> for UART8

impl DMASet<StreamX<DMA1, 0>, 6, MemoryToPeripheral> for CCR3<TIM5>

impl DMASet<StreamX<DMA1, 0>, 6, MemoryToPeripheral> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 0>, 6, PeripheralToMemory> for CCR3<TIM5>

impl DMASet<StreamX<DMA1, 0>, 6, PeripheralToMemory> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 1>, 3, MemoryToPeripheral> for CCR3<TIM2>

impl DMASet<StreamX<DMA1, 1>, 3, MemoryToPeripheral> for DMAR<TIM2>

impl DMASet<StreamX<DMA1, 1>, 3, PeripheralToMemory> for CCR3<TIM2>

impl DMASet<StreamX<DMA1, 1>, 3, PeripheralToMemory> for DMAR<TIM2>

impl DMASet<StreamX<DMA1, 1>, 4, PeripheralToMemory> for USART3

impl DMASet<StreamX<DMA1, 1>, 5, MemoryToPeripheral> for UART7

impl DMASet<StreamX<DMA1, 1>, 6, MemoryToPeripheral> for CCR4<TIM5>

impl DMASet<StreamX<DMA1, 1>, 6, MemoryToPeripheral> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 1>, 6, PeripheralToMemory> for CCR4<TIM5>

impl DMASet<StreamX<DMA1, 1>, 6, PeripheralToMemory> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 2>, 0, PeripheralToMemory> for SPI3

impl DMASet<StreamX<DMA1, 2>, 3, PeripheralToMemory> for I2C3

impl DMASet<StreamX<DMA1, 2>, 4, PeripheralToMemory> for UART4

impl DMASet<StreamX<DMA1, 2>, 5, MemoryToPeripheral> for CCR4<TIM3>

impl DMASet<StreamX<DMA1, 2>, 5, MemoryToPeripheral> for DMAR<TIM3>

impl DMASet<StreamX<DMA1, 2>, 5, PeripheralToMemory> for CCR4<TIM3>

impl DMASet<StreamX<DMA1, 2>, 5, PeripheralToMemory> for DMAR<TIM3>

impl DMASet<StreamX<DMA1, 2>, 6, MemoryToPeripheral> for CCR1<TIM5>

impl DMASet<StreamX<DMA1, 2>, 6, PeripheralToMemory> for CCR1<TIM5>

impl DMASet<StreamX<DMA1, 2>, 7, PeripheralToMemory> for I2C2

impl DMASet<StreamX<DMA1, 3>, 0, PeripheralToMemory> for SPI2

impl DMASet<StreamX<DMA1, 3>, 2, MemoryToPeripheral> for CCR2<TIM4>

impl DMASet<StreamX<DMA1, 3>, 2, PeripheralToMemory> for CCR2<TIM4>

impl DMASet<StreamX<DMA1, 3>, 4, MemoryToPeripheral> for USART3

impl DMASet<StreamX<DMA1, 3>, 5, PeripheralToMemory> for UART7

impl DMASet<StreamX<DMA1, 3>, 6, MemoryToPeripheral> for CCR4<TIM5>

impl DMASet<StreamX<DMA1, 3>, 6, MemoryToPeripheral> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 3>, 6, PeripheralToMemory> for CCR4<TIM5>

impl DMASet<StreamX<DMA1, 3>, 6, PeripheralToMemory> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 3>, 7, PeripheralToMemory> for I2C2

impl DMASet<StreamX<DMA1, 4>, 0, MemoryToPeripheral> for SPI2

impl DMASet<StreamX<DMA1, 4>, 3, MemoryToPeripheral> for I2C3

impl DMASet<StreamX<DMA1, 4>, 4, MemoryToPeripheral> for UART4

impl DMASet<StreamX<DMA1, 4>, 5, MemoryToPeripheral> for CCR1<TIM3>

impl DMASet<StreamX<DMA1, 4>, 5, MemoryToPeripheral> for DMAR<TIM3>

impl DMASet<StreamX<DMA1, 4>, 5, PeripheralToMemory> for CCR1<TIM3>

impl DMASet<StreamX<DMA1, 4>, 5, PeripheralToMemory> for DMAR<TIM3>

impl DMASet<StreamX<DMA1, 4>, 6, MemoryToPeripheral> for CCR2<TIM5>

impl DMASet<StreamX<DMA1, 4>, 6, PeripheralToMemory> for CCR2<TIM5>

impl DMASet<StreamX<DMA1, 4>, 7, MemoryToPeripheral> for USART3

impl DMASet<StreamX<DMA1, 5>, 0, MemoryToPeripheral> for SPI3

impl DMASet<StreamX<DMA1, 5>, 1, PeripheralToMemory> for I2C1

impl DMASet<StreamX<DMA1, 5>, 3, MemoryToPeripheral> for CCR1<TIM2>

impl DMASet<StreamX<DMA1, 5>, 3, PeripheralToMemory> for CCR1<TIM2>

impl DMASet<StreamX<DMA1, 5>, 4, PeripheralToMemory> for USART2

impl DMASet<StreamX<DMA1, 5>, 5, MemoryToPeripheral> for CCR2<TIM3>

impl DMASet<StreamX<DMA1, 5>, 5, PeripheralToMemory> for CCR2<TIM3>

impl DMASet<StreamX<DMA1, 6>, 1, MemoryToPeripheral> for I2C1

impl DMASet<StreamX<DMA1, 6>, 2, MemoryToPeripheral> for DMAR<TIM4>

impl DMASet<StreamX<DMA1, 6>, 2, PeripheralToMemory> for DMAR<TIM4>

impl DMASet<StreamX<DMA1, 6>, 3, MemoryToPeripheral> for CCR2<TIM2>

impl DMASet<StreamX<DMA1, 6>, 3, MemoryToPeripheral> for CCR4<TIM2>

impl DMASet<StreamX<DMA1, 6>, 3, PeripheralToMemory> for CCR2<TIM2>

impl DMASet<StreamX<DMA1, 6>, 3, PeripheralToMemory> for CCR4<TIM2>

impl DMASet<StreamX<DMA1, 6>, 4, MemoryToPeripheral> for USART2

impl DMASet<StreamX<DMA1, 6>, 5, PeripheralToMemory> for UART8

impl DMASet<StreamX<DMA1, 6>, 6, MemoryToPeripheral> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 6>, 6, PeripheralToMemory> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 7>, 0, MemoryToPeripheral> for SPI3

impl DMASet<StreamX<DMA1, 7>, 1, MemoryToPeripheral> for I2C1

impl DMASet<StreamX<DMA1, 7>, 2, MemoryToPeripheral> for CCR3<TIM4>

impl DMASet<StreamX<DMA1, 7>, 2, PeripheralToMemory> for CCR3<TIM4>

impl DMASet<StreamX<DMA1, 7>, 3, MemoryToPeripheral> for CCR4<TIM2>

impl DMASet<StreamX<DMA1, 7>, 3, MemoryToPeripheral> for DMAR<TIM2>

impl DMASet<StreamX<DMA1, 7>, 3, PeripheralToMemory> for CCR4<TIM2>

impl DMASet<StreamX<DMA1, 7>, 3, PeripheralToMemory> for DMAR<TIM2>

impl DMASet<StreamX<DMA1, 7>, 4, MemoryToPeripheral> for UART5

impl DMASet<StreamX<DMA1, 7>, 5, MemoryToPeripheral> for CCR3<TIM3>

impl DMASet<StreamX<DMA1, 7>, 5, PeripheralToMemory> for CCR3<TIM3>

impl DMASet<StreamX<DMA1, 7>, 7, MemoryToPeripheral> for I2C2

impl DMASet<StreamX<DMA2, 0>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 0>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 0>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 0>, 0, PeripheralToMemory> for ADC1

impl DMASet<StreamX<DMA2, 0>, 2, PeripheralToMemory> for ADC3

impl DMASet<StreamX<DMA2, 0>, 3, PeripheralToMemory> for SPI1

impl DMASet<StreamX<DMA2, 0>, 4, PeripheralToMemory> for SPI4

impl DMASet<StreamX<DMA2, 0>, 6, MemoryToPeripheral> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 0>, 6, PeripheralToMemory> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 1>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 1>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 1>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 1>, 0, MemoryToPeripheral> for SAICH<SAI, 0>

impl DMASet<StreamX<DMA2, 1>, 0, PeripheralToMemory> for SAICH<SAI, 0>

impl DMASet<StreamX<DMA2, 1>, 1, PeripheralToMemory> for DCMI

impl DMASet<StreamX<DMA2, 1>, 2, PeripheralToMemory> for ADC3

impl DMASet<StreamX<DMA2, 1>, 4, MemoryToPeripheral> for SPI4

impl DMASet<StreamX<DMA2, 1>, 5, PeripheralToMemory> for USART6

impl DMASet<StreamX<DMA2, 1>, 6, MemoryToPeripheral> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 1>, 6, PeripheralToMemory> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 1>, 7, MemoryToPeripheral> for DMAR<TIM8>

impl DMASet<StreamX<DMA2, 1>, 7, PeripheralToMemory> for DMAR<TIM8>

impl DMASet<StreamX<DMA2, 2>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 2>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 2>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 2>, 0, MemoryToPeripheral> for CCR1<TIM8>

impl DMASet<StreamX<DMA2, 2>, 0, MemoryToPeripheral> for CCR2<TIM8>

impl DMASet<StreamX<DMA2, 2>, 0, MemoryToPeripheral> for CCR3<TIM8>

impl DMASet<StreamX<DMA2, 2>, 0, PeripheralToMemory> for CCR1<TIM8>

impl DMASet<StreamX<DMA2, 2>, 0, PeripheralToMemory> for CCR2<TIM8>

impl DMASet<StreamX<DMA2, 2>, 0, PeripheralToMemory> for CCR3<TIM8>

impl DMASet<StreamX<DMA2, 2>, 1, PeripheralToMemory> for ADC2

impl DMASet<StreamX<DMA2, 2>, 3, PeripheralToMemory> for SPI1

impl DMASet<StreamX<DMA2, 2>, 4, PeripheralToMemory> for USART1

impl DMASet<StreamX<DMA2, 2>, 5, PeripheralToMemory> for USART6

impl DMASet<StreamX<DMA2, 2>, 6, MemoryToPeripheral> for CCR2<TIM1>

impl DMASet<StreamX<DMA2, 2>, 6, PeripheralToMemory> for CCR2<TIM1>

impl DMASet<StreamX<DMA2, 2>, 7, MemoryToPeripheral> for CCR1<TIM8>

impl DMASet<StreamX<DMA2, 2>, 7, PeripheralToMemory> for CCR1<TIM8>

impl DMASet<StreamX<DMA2, 3>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 3>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 3>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 3>, 0, MemoryToPeripheral> for SAICH<SAI, 0>

impl DMASet<StreamX<DMA2, 3>, 0, PeripheralToMemory> for SAICH<SAI, 0>

impl DMASet<StreamX<DMA2, 3>, 1, PeripheralToMemory> for ADC2

impl DMASet<StreamX<DMA2, 3>, 2, PeripheralToMemory> for SPI5

impl DMASet<StreamX<DMA2, 3>, 3, MemoryToPeripheral> for SPI1

impl DMASet<StreamX<DMA2, 3>, 4, MemoryToPeripheral> for SDIO

impl DMASet<StreamX<DMA2, 3>, 4, PeripheralToMemory> for SDIO

impl DMASet<StreamX<DMA2, 3>, 5, PeripheralToMemory> for SPI4

impl DMASet<StreamX<DMA2, 3>, 6, MemoryToPeripheral> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 3>, 6, PeripheralToMemory> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 3>, 7, MemoryToPeripheral> for CCR2<TIM8>

impl DMASet<StreamX<DMA2, 3>, 7, PeripheralToMemory> for CCR2<TIM8>

impl DMASet<StreamX<DMA2, 4>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 4>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 4>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 4>, 0, PeripheralToMemory> for ADC1

impl DMASet<StreamX<DMA2, 4>, 1, MemoryToPeripheral> for SAICH<SAI, 1>

impl DMASet<StreamX<DMA2, 4>, 1, PeripheralToMemory> for SAICH<SAI, 1>

impl DMASet<StreamX<DMA2, 4>, 2, MemoryToPeripheral> for SPI5

impl DMASet<StreamX<DMA2, 4>, 5, MemoryToPeripheral> for SPI4

impl DMASet<StreamX<DMA2, 4>, 6, MemoryToPeripheral> for CCR4<TIM1>

impl DMASet<StreamX<DMA2, 4>, 6, MemoryToPeripheral> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 4>, 6, PeripheralToMemory> for CCR4<TIM1>

impl DMASet<StreamX<DMA2, 4>, 6, PeripheralToMemory> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 4>, 7, MemoryToPeripheral> for CCR3<TIM8>

impl DMASet<StreamX<DMA2, 4>, 7, PeripheralToMemory> for CCR3<TIM8>

impl DMASet<StreamX<DMA2, 5>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 5>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 5>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 5>, 0, MemoryToPeripheral> for SAICH<SAI, 1>

impl DMASet<StreamX<DMA2, 5>, 0, PeripheralToMemory> for SAICH<SAI, 1>

impl DMASet<StreamX<DMA2, 5>, 1, MemoryToPeripheral> for SPI6

impl DMASet<StreamX<DMA2, 5>, 2, PeripheralToMemory> for CRYP

impl DMASet<StreamX<DMA2, 5>, 3, MemoryToPeripheral> for SPI1

impl DMASet<StreamX<DMA2, 5>, 4, PeripheralToMemory> for USART1

impl DMASet<StreamX<DMA2, 5>, 6, MemoryToPeripheral> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 5>, 6, PeripheralToMemory> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 5>, 7, PeripheralToMemory> for SPI5

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR2<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR3<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR2<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR3<TIM1>

impl DMASet<StreamX<DMA2, 6>, 1, PeripheralToMemory> for SPI6

impl DMASet<StreamX<DMA2, 6>, 2, MemoryToPeripheral> for CRYP

impl DMASet<StreamX<DMA2, 6>, 4, MemoryToPeripheral> for SDIO

impl DMASet<StreamX<DMA2, 6>, 4, PeripheralToMemory> for SDIO

impl DMASet<StreamX<DMA2, 6>, 5, MemoryToPeripheral> for USART6

impl DMASet<StreamX<DMA2, 6>, 6, MemoryToPeripheral> for CCR3<TIM1>

impl DMASet<StreamX<DMA2, 6>, 6, PeripheralToMemory> for CCR3<TIM1>

impl DMASet<StreamX<DMA2, 6>, 7, MemoryToPeripheral> for SPI5

impl DMASet<StreamX<DMA2, 7>, 0, MemoryToMemory<u16>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 7>, 0, MemoryToMemory<u32>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 7>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 7>, 1, PeripheralToMemory> for DCMI

impl DMASet<StreamX<DMA2, 7>, 2, MemoryToPeripheral> for HASH

impl DMASet<StreamX<DMA2, 7>, 4, MemoryToPeripheral> for USART1

impl DMASet<StreamX<DMA2, 7>, 5, MemoryToPeripheral> for USART6

impl DMASet<StreamX<DMA2, 7>, 7, MemoryToPeripheral> for CCR4<TIM8>

impl DMASet<StreamX<DMA2, 7>, 7, MemoryToPeripheral> for DMAR<TIM8>

impl DMASet<StreamX<DMA2, 7>, 7, PeripheralToMemory> for CCR4<TIM8>

impl DMASet<StreamX<DMA2, 7>, 7, PeripheralToMemory> for DMAR<TIM8>