#[doc = "Reader of register DSI_PSR"]
pub type R = crate::R<u32, super::DSI_PSR>;
#[doc = "Writer for register DSI_PSR"]
pub type W = crate::W<u32, super::DSI_PSR>;
#[doc = "Register DSI_PSR `reset()`'s with value 0x1528"]
impl crate::ResetValue for super::DSI_PSR {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0x1528
}
}
#[doc = "Reader of field `UAN1`"]
pub type UAN1_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `UAN1`"]
pub struct UAN1_W<'a> {
w: &'a mut W,
}
impl<'a> UAN1_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
self.w
}
}
#[doc = "Reader of field `PSS1`"]
pub type PSS1_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `PSS1`"]
pub struct PSS1_W<'a> {
w: &'a mut W,
}
impl<'a> PSS1_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
self.w
}
}
#[doc = "Reader of field `RUE0`"]
pub type RUE0_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `RUE0`"]
pub struct RUE0_W<'a> {
w: &'a mut W,
}
impl<'a> RUE0_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
self.w
}
}
#[doc = "Reader of field `UAN0`"]
pub type UAN0_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `UAN0`"]
pub struct UAN0_W<'a> {
w: &'a mut W,
}
impl<'a> UAN0_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
self.w
}
}
#[doc = "Reader of field `PSS0`"]
pub type PSS0_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `PSS0`"]
pub struct PSS0_W<'a> {
w: &'a mut W,
}
impl<'a> PSS0_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
self.w
}
}
#[doc = "Reader of field `UANC`"]
pub type UANC_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `UANC`"]
pub struct UANC_W<'a> {
w: &'a mut W,
}
impl<'a> UANC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
self.w
}
}
#[doc = "Reader of field `PSSC`"]
pub type PSSC_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `PSSC`"]
pub struct PSSC_W<'a> {
w: &'a mut W,
}
impl<'a> PSSC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
self.w
}
}
#[doc = "Reader of field `PD`"]
pub type PD_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `PD`"]
pub struct PD_W<'a> {
w: &'a mut W,
}
impl<'a> PD_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
self.w
}
}
impl R {
#[doc = "Bit 8 - ULPS Active Not lane 1"]
#[inline(always)]
pub fn uan1(&self) -> UAN1_R {
UAN1_R::new(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 7 - PHY Stop State lane 1"]
#[inline(always)]
pub fn pss1(&self) -> PSS1_R {
PSS1_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bit 6 - RX ULPS Escape lane 0"]
#[inline(always)]
pub fn rue0(&self) -> RUE0_R {
RUE0_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 5 - ULPS Active Not lane 1"]
#[inline(always)]
pub fn uan0(&self) -> UAN0_R {
UAN0_R::new(((self.bits >> 5) & 0x01) != 0)
}
#[doc = "Bit 4 - PHY Stop State lane 0"]
#[inline(always)]
pub fn pss0(&self) -> PSS0_R {
PSS0_R::new(((self.bits >> 4) & 0x01) != 0)
}
#[doc = "Bit 3 - ULPS Active Not Clock lane"]
#[inline(always)]
pub fn uanc(&self) -> UANC_R {
UANC_R::new(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bit 2 - PHY Stop State Clock lane"]
#[inline(always)]
pub fn pssc(&self) -> PSSC_R {
PSSC_R::new(((self.bits >> 2) & 0x01) != 0)
}
#[doc = "Bit 1 - PHY Direction"]
#[inline(always)]
pub fn pd(&self) -> PD_R {
PD_R::new(((self.bits >> 1) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 8 - ULPS Active Not lane 1"]
#[inline(always)]
pub fn uan1(&mut self) -> UAN1_W {
UAN1_W { w: self }
}
#[doc = "Bit 7 - PHY Stop State lane 1"]
#[inline(always)]
pub fn pss1(&mut self) -> PSS1_W {
PSS1_W { w: self }
}
#[doc = "Bit 6 - RX ULPS Escape lane 0"]
#[inline(always)]
pub fn rue0(&mut self) -> RUE0_W {
RUE0_W { w: self }
}
#[doc = "Bit 5 - ULPS Active Not lane 1"]
#[inline(always)]
pub fn uan0(&mut self) -> UAN0_W {
UAN0_W { w: self }
}
#[doc = "Bit 4 - PHY Stop State lane 0"]
#[inline(always)]
pub fn pss0(&mut self) -> PSS0_W {
PSS0_W { w: self }
}
#[doc = "Bit 3 - ULPS Active Not Clock lane"]
#[inline(always)]
pub fn uanc(&mut self) -> UANC_W {
UANC_W { w: self }
}
#[doc = "Bit 2 - PHY Stop State Clock lane"]
#[inline(always)]
pub fn pssc(&mut self) -> PSSC_W {
PSSC_W { w: self }
}
#[doc = "Bit 1 - PHY Direction"]
#[inline(always)]
pub fn pd(&mut self) -> PD_W {
PD_W { w: self }
}
}