#[doc = "Reader of register APB2ENR"]
pub type R = crate::R<u32, super::APB2ENR>;
#[doc = "Writer for register APB2ENR"]
pub type W = crate::W<u32, super::APB2ENR>;
#[doc = "Register APB2ENR `reset()`'s with value 0"]
impl crate::ResetValue for super::APB2ENR {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "SYSCFG clock enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SYSCFGEN_A {
#[doc = "0: The selected clock is disabled"]
DISABLED = 0,
#[doc = "1: The selected clock is enabled"]
ENABLED = 1,
}
impl From<SYSCFGEN_A> for bool {
#[inline(always)]
fn from(variant: SYSCFGEN_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `SYSCFGEN`"]
pub type SYSCFGEN_R = crate::R<bool, SYSCFGEN_A>;
impl SYSCFGEN_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> SYSCFGEN_A {
match self.bits {
false => SYSCFGEN_A::DISABLED,
true => SYSCFGEN_A::ENABLED,
}
}
#[doc = "Checks if the value of the field is `DISABLED`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SYSCFGEN_A::DISABLED
}
#[doc = "Checks if the value of the field is `ENABLED`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SYSCFGEN_A::ENABLED
}
}
#[doc = "Write proxy for field `SYSCFGEN`"]
pub struct SYSCFGEN_W<'a> {
w: &'a mut W,
}
impl<'a> SYSCFGEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SYSCFGEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
self.w
}
}
#[doc = "ADC 1 interface clock enable"]
pub type ADCEN_A = SYSCFGEN_A;
#[doc = "Reader of field `ADCEN`"]
pub type ADCEN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `ADCEN`"]
pub struct ADCEN_W<'a> {
w: &'a mut W,
}
impl<'a> ADCEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ADCEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
self.w
}
}
#[doc = "SPI 1 clock enable"]
pub type SPI1EN_A = SYSCFGEN_A;
#[doc = "Reader of field `SPI1EN`"]
pub type SPI1EN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `SPI1EN`"]
pub struct SPI1EN_W<'a> {
w: &'a mut W,
}
impl<'a> SPI1EN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SPI1EN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
self.w
}
}
#[doc = "USART1 clock enable"]
pub type USART1EN_A = SYSCFGEN_A;
#[doc = "Reader of field `USART1EN`"]
pub type USART1EN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `USART1EN`"]
pub struct USART1EN_W<'a> {
w: &'a mut W,
}
impl<'a> USART1EN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USART1EN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
self.w
}
}
#[doc = "TIM15 timer clock enable"]
pub type TIM15EN_A = SYSCFGEN_A;
#[doc = "Reader of field `TIM15EN`"]
pub type TIM15EN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `TIM15EN`"]
pub struct TIM15EN_W<'a> {
w: &'a mut W,
}
impl<'a> TIM15EN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM15EN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
self.w
}
}
#[doc = "TIM16 timer clock enable"]
pub type TIM16EN_A = SYSCFGEN_A;
#[doc = "Reader of field `TIM16EN`"]
pub type TIM16EN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `TIM16EN`"]
pub struct TIM16EN_W<'a> {
w: &'a mut W,
}
impl<'a> TIM16EN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM16EN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
self.w
}
}
#[doc = "TIM17 timer clock enable"]
pub type TIM17EN_A = SYSCFGEN_A;
#[doc = "Reader of field `TIM17EN`"]
pub type TIM17EN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `TIM17EN`"]
pub struct TIM17EN_W<'a> {
w: &'a mut W,
}
impl<'a> TIM17EN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM17EN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
self.w
}
}
#[doc = "TIM19 timer clock enable"]
pub type TIM19EN_A = SYSCFGEN_A;
#[doc = "Reader of field `TIM19EN`"]
pub type TIM19EN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `TIM19EN`"]
pub struct TIM19EN_W<'a> {
w: &'a mut W,
}
impl<'a> TIM19EN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM19EN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
self.w
}
}
#[doc = "MCU debug module clock enable"]
pub type DBGMCUEN_A = SYSCFGEN_A;
#[doc = "Reader of field `DBGMCUEN`"]
pub type DBGMCUEN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `DBGMCUEN`"]
pub struct DBGMCUEN_W<'a> {
w: &'a mut W,
}
impl<'a> DBGMCUEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DBGMCUEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
self.w
}
}
#[doc = "SDADC1 (Sigma Delta ADC 1) clock enable"]
pub type SDADC1EN_A = SYSCFGEN_A;
#[doc = "Reader of field `SDADC1EN`"]
pub type SDADC1EN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `SDADC1EN`"]
pub struct SDADC1EN_W<'a> {
w: &'a mut W,
}
impl<'a> SDADC1EN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SDADC1EN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
self.w
}
}
#[doc = "SDADC2 (Sigma Delta ADC 2) clock enable"]
pub type SDADC2EN_A = SYSCFGEN_A;
#[doc = "Reader of field `SDADC2EN`"]
pub type SDADC2EN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `SDADC2EN`"]
pub struct SDADC2EN_W<'a> {
w: &'a mut W,
}
impl<'a> SDADC2EN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SDADC2EN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
self.w
}
}
#[doc = "SDADC3 (Sigma Delta ADC 3) clock enable"]
pub type SDADC3EN_A = SYSCFGEN_A;
#[doc = "Reader of field `SDADC3EN`"]
pub type SDADC3EN_R = crate::R<bool, SYSCFGEN_A>;
#[doc = "Write proxy for field `SDADC3EN`"]
pub struct SDADC3EN_W<'a> {
w: &'a mut W,
}
impl<'a> SDADC3EN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SDADC3EN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The selected clock is disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::DISABLED)
}
#[doc = "The selected clock is enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(SYSCFGEN_A::ENABLED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
self.w
}
}
impl R {
#[doc = "Bit 0 - SYSCFG clock enable"]
#[inline(always)]
pub fn syscfgen(&self) -> SYSCFGEN_R {
SYSCFGEN_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 9 - ADC 1 interface clock enable"]
#[inline(always)]
pub fn adcen(&self) -> ADCEN_R {
ADCEN_R::new(((self.bits >> 9) & 0x01) != 0)
}
#[doc = "Bit 12 - SPI 1 clock enable"]
#[inline(always)]
pub fn spi1en(&self) -> SPI1EN_R {
SPI1EN_R::new(((self.bits >> 12) & 0x01) != 0)
}
#[doc = "Bit 14 - USART1 clock enable"]
#[inline(always)]
pub fn usart1en(&self) -> USART1EN_R {
USART1EN_R::new(((self.bits >> 14) & 0x01) != 0)
}
#[doc = "Bit 16 - TIM15 timer clock enable"]
#[inline(always)]
pub fn tim15en(&self) -> TIM15EN_R {
TIM15EN_R::new(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bit 17 - TIM16 timer clock enable"]
#[inline(always)]
pub fn tim16en(&self) -> TIM16EN_R {
TIM16EN_R::new(((self.bits >> 17) & 0x01) != 0)
}
#[doc = "Bit 18 - TIM17 timer clock enable"]
#[inline(always)]
pub fn tim17en(&self) -> TIM17EN_R {
TIM17EN_R::new(((self.bits >> 18) & 0x01) != 0)
}
#[doc = "Bit 19 - TIM19 timer clock enable"]
#[inline(always)]
pub fn tim19en(&self) -> TIM19EN_R {
TIM19EN_R::new(((self.bits >> 19) & 0x01) != 0)
}
#[doc = "Bit 22 - MCU debug module clock enable"]
#[inline(always)]
pub fn dbgmcuen(&self) -> DBGMCUEN_R {
DBGMCUEN_R::new(((self.bits >> 22) & 0x01) != 0)
}
#[doc = "Bit 24 - SDADC1 (Sigma Delta ADC 1) clock enable"]
#[inline(always)]
pub fn sdadc1en(&self) -> SDADC1EN_R {
SDADC1EN_R::new(((self.bits >> 24) & 0x01) != 0)
}
#[doc = "Bit 25 - SDADC2 (Sigma Delta ADC 2) clock enable"]
#[inline(always)]
pub fn sdadc2en(&self) -> SDADC2EN_R {
SDADC2EN_R::new(((self.bits >> 25) & 0x01) != 0)
}
#[doc = "Bit 26 - SDADC3 (Sigma Delta ADC 3) clock enable"]
#[inline(always)]
pub fn sdadc3en(&self) -> SDADC3EN_R {
SDADC3EN_R::new(((self.bits >> 26) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 0 - SYSCFG clock enable"]
#[inline(always)]
pub fn syscfgen(&mut self) -> SYSCFGEN_W {
SYSCFGEN_W { w: self }
}
#[doc = "Bit 9 - ADC 1 interface clock enable"]
#[inline(always)]
pub fn adcen(&mut self) -> ADCEN_W {
ADCEN_W { w: self }
}
#[doc = "Bit 12 - SPI 1 clock enable"]
#[inline(always)]
pub fn spi1en(&mut self) -> SPI1EN_W {
SPI1EN_W { w: self }
}
#[doc = "Bit 14 - USART1 clock enable"]
#[inline(always)]
pub fn usart1en(&mut self) -> USART1EN_W {
USART1EN_W { w: self }
}
#[doc = "Bit 16 - TIM15 timer clock enable"]
#[inline(always)]
pub fn tim15en(&mut self) -> TIM15EN_W {
TIM15EN_W { w: self }
}
#[doc = "Bit 17 - TIM16 timer clock enable"]
#[inline(always)]
pub fn tim16en(&mut self) -> TIM16EN_W {
TIM16EN_W { w: self }
}
#[doc = "Bit 18 - TIM17 timer clock enable"]
#[inline(always)]
pub fn tim17en(&mut self) -> TIM17EN_W {
TIM17EN_W { w: self }
}
#[doc = "Bit 19 - TIM19 timer clock enable"]
#[inline(always)]
pub fn tim19en(&mut self) -> TIM19EN_W {
TIM19EN_W { w: self }
}
#[doc = "Bit 22 - MCU debug module clock enable"]
#[inline(always)]
pub fn dbgmcuen(&mut self) -> DBGMCUEN_W {
DBGMCUEN_W { w: self }
}
#[doc = "Bit 24 - SDADC1 (Sigma Delta ADC 1) clock enable"]
#[inline(always)]
pub fn sdadc1en(&mut self) -> SDADC1EN_W {
SDADC1EN_W { w: self }
}
#[doc = "Bit 25 - SDADC2 (Sigma Delta ADC 2) clock enable"]
#[inline(always)]
pub fn sdadc2en(&mut self) -> SDADC2EN_W {
SDADC2EN_W { w: self }
}
#[doc = "Bit 26 - SDADC3 (Sigma Delta ADC 3) clock enable"]
#[inline(always)]
pub fn sdadc3en(&mut self) -> SDADC3EN_W {
SDADC3EN_W { w: self }
}
}