stm32f3-staging 0.17.0

///Register `IOHCR` reader
pub type R = crate::R<IOHCRrs>;
///Register `IOHCR` writer
pub type W = crate::W<IOHCRrs>;
///Field `G1_IO1` reader - G1_IO1 Schmitt trigger hysteresis mode
pub type G1_IO1_R = crate::BitReader;
///Field `G1_IO1` writer - G1_IO1 Schmitt trigger hysteresis mode
pub type G1_IO1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G1_IO2` reader - G1_IO2 Schmitt trigger hysteresis mode
pub type G1_IO2_R = crate::BitReader;
///Field `G1_IO2` writer - G1_IO2 Schmitt trigger hysteresis mode
pub type G1_IO2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G1_IO3` reader - G1_IO3 Schmitt trigger hysteresis mode
pub type G1_IO3_R = crate::BitReader;
///Field `G1_IO3` writer - G1_IO3 Schmitt trigger hysteresis mode
pub type G1_IO3_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G1_IO4` reader - G1_IO4 Schmitt trigger hysteresis mode
pub type G1_IO4_R = crate::BitReader;
///Field `G1_IO4` writer - G1_IO4 Schmitt trigger hysteresis mode
pub type G1_IO4_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G2_IO1` reader - G2_IO1 Schmitt trigger hysteresis mode
pub type G2_IO1_R = crate::BitReader;
///Field `G2_IO1` writer - G2_IO1 Schmitt trigger hysteresis mode
pub type G2_IO1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G2_IO2` reader - G2_IO2 Schmitt trigger hysteresis mode
pub type G2_IO2_R = crate::BitReader;
///Field `G2_IO2` writer - G2_IO2 Schmitt trigger hysteresis mode
pub type G2_IO2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G2_IO3` reader - G2_IO3 Schmitt trigger hysteresis mode
pub type G2_IO3_R = crate::BitReader;
///Field `G2_IO3` writer - G2_IO3 Schmitt trigger hysteresis mode
pub type G2_IO3_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G2_IO4` reader - G2_IO4 Schmitt trigger hysteresis mode
pub type G2_IO4_R = crate::BitReader;
///Field `G2_IO4` writer - G2_IO4 Schmitt trigger hysteresis mode
pub type G2_IO4_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G3_IO1` reader - G3_IO1 Schmitt trigger hysteresis mode
pub type G3_IO1_R = crate::BitReader;
///Field `G3_IO1` writer - G3_IO1 Schmitt trigger hysteresis mode
pub type G3_IO1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G3_IO2` reader - G3_IO2 Schmitt trigger hysteresis mode
pub type G3_IO2_R = crate::BitReader;
///Field `G3_IO2` writer - G3_IO2 Schmitt trigger hysteresis mode
pub type G3_IO2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G3_IO3` reader - G3_IO3 Schmitt trigger hysteresis mode
pub type G3_IO3_R = crate::BitReader;
///Field `G3_IO3` writer - G3_IO3 Schmitt trigger hysteresis mode
pub type G3_IO3_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G3_IO4` reader - G3_IO4 Schmitt trigger hysteresis mode
pub type G3_IO4_R = crate::BitReader;
///Field `G3_IO4` writer - G3_IO4 Schmitt trigger hysteresis mode
pub type G3_IO4_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G4_IO1` reader - G4_IO1 Schmitt trigger hysteresis mode
pub type G4_IO1_R = crate::BitReader;
///Field `G4_IO1` writer - G4_IO1 Schmitt trigger hysteresis mode
pub type G4_IO1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G4_IO2` reader - G4_IO2 Schmitt trigger hysteresis mode
pub type G4_IO2_R = crate::BitReader;
///Field `G4_IO2` writer - G4_IO2 Schmitt trigger hysteresis mode
pub type G4_IO2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G4_IO3` reader - G4_IO3 Schmitt trigger hysteresis mode
pub type G4_IO3_R = crate::BitReader;
///Field `G4_IO3` writer - G4_IO3 Schmitt trigger hysteresis mode
pub type G4_IO3_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G4_IO4` reader - G4_IO4 Schmitt trigger hysteresis mode
pub type G4_IO4_R = crate::BitReader;
///Field `G4_IO4` writer - G4_IO4 Schmitt trigger hysteresis mode
pub type G4_IO4_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G5_IO1` reader - G5_IO1 Schmitt trigger hysteresis mode
pub type G5_IO1_R = crate::BitReader;
///Field `G5_IO1` writer - G5_IO1 Schmitt trigger hysteresis mode
pub type G5_IO1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G5_IO2` reader - G5_IO2 Schmitt trigger hysteresis mode
pub type G5_IO2_R = crate::BitReader;
///Field `G5_IO2` writer - G5_IO2 Schmitt trigger hysteresis mode
pub type G5_IO2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G5_IO3` reader - G5_IO3 Schmitt trigger hysteresis mode
pub type G5_IO3_R = crate::BitReader;
///Field `G5_IO3` writer - G5_IO3 Schmitt trigger hysteresis mode
pub type G5_IO3_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G5_IO4` reader - G5_IO4 Schmitt trigger hysteresis mode
pub type G5_IO4_R = crate::BitReader;
///Field `G5_IO4` writer - G5_IO4 Schmitt trigger hysteresis mode
pub type G5_IO4_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G6_IO1` reader - G6_IO1 Schmitt trigger hysteresis mode
pub type G6_IO1_R = crate::BitReader;
///Field `G6_IO1` writer - G6_IO1 Schmitt trigger hysteresis mode
pub type G6_IO1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G6_IO2` reader - G6_IO2 Schmitt trigger hysteresis mode
pub type G6_IO2_R = crate::BitReader;
///Field `G6_IO2` writer - G6_IO2 Schmitt trigger hysteresis mode
pub type G6_IO2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G6_IO3` reader - G6_IO3 Schmitt trigger hysteresis mode
pub type G6_IO3_R = crate::BitReader;
///Field `G6_IO3` writer - G6_IO3 Schmitt trigger hysteresis mode
pub type G6_IO3_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G6_IO4` reader - G6_IO4 Schmitt trigger hysteresis mode
pub type G6_IO4_R = crate::BitReader;
///Field `G6_IO4` writer - G6_IO4 Schmitt trigger hysteresis mode
pub type G6_IO4_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G7_IO1` reader - G7_IO1 Schmitt trigger hysteresis mode
pub type G7_IO1_R = crate::BitReader;
///Field `G7_IO1` writer - G7_IO1 Schmitt trigger hysteresis mode
pub type G7_IO1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G7_IO2` reader - G7_IO2 Schmitt trigger hysteresis mode
pub type G7_IO2_R = crate::BitReader;
///Field `G7_IO2` writer - G7_IO2 Schmitt trigger hysteresis mode
pub type G7_IO2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G7_IO3` reader - G7_IO3 Schmitt trigger hysteresis mode
pub type G7_IO3_R = crate::BitReader;
///Field `G7_IO3` writer - G7_IO3 Schmitt trigger hysteresis mode
pub type G7_IO3_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G7_IO4` reader - G7_IO4 Schmitt trigger hysteresis mode
pub type G7_IO4_R = crate::BitReader;
///Field `G7_IO4` writer - G7_IO4 Schmitt trigger hysteresis mode
pub type G7_IO4_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G8_IO1` reader - G8_IO1 Schmitt trigger hysteresis mode
pub type G8_IO1_R = crate::BitReader;
///Field `G8_IO1` writer - G8_IO1 Schmitt trigger hysteresis mode
pub type G8_IO1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G8_IO2` reader - G8_IO2 Schmitt trigger hysteresis mode
pub type G8_IO2_R = crate::BitReader;
///Field `G8_IO2` writer - G8_IO2 Schmitt trigger hysteresis mode
pub type G8_IO2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G8_IO3` reader - G8_IO3 Schmitt trigger hysteresis mode
pub type G8_IO3_R = crate::BitReader;
///Field `G8_IO3` writer - G8_IO3 Schmitt trigger hysteresis mode
pub type G8_IO3_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `G8_IO4` reader - G8_IO4 Schmitt trigger hysteresis mode
pub type G8_IO4_R = crate::BitReader;
///Field `G8_IO4` writer - G8_IO4 Schmitt trigger hysteresis mode
pub type G8_IO4_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - G1_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g1_io1(&self) -> G1_IO1_R {
        G1_IO1_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - G1_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g1_io2(&self) -> G1_IO2_R {
        G1_IO2_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - G1_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g1_io3(&self) -> G1_IO3_R {
        G1_IO3_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - G1_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g1_io4(&self) -> G1_IO4_R {
        G1_IO4_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - G2_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g2_io1(&self) -> G2_IO1_R {
        G2_IO1_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - G2_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g2_io2(&self) -> G2_IO2_R {
        G2_IO2_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - G2_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g2_io3(&self) -> G2_IO3_R {
        G2_IO3_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 7 - G2_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g2_io4(&self) -> G2_IO4_R {
        G2_IO4_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bit 8 - G3_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g3_io1(&self) -> G3_IO1_R {
        G3_IO1_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - G3_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g3_io2(&self) -> G3_IO2_R {
        G3_IO2_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - G3_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g3_io3(&self) -> G3_IO3_R {
        G3_IO3_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 11 - G3_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g3_io4(&self) -> G3_IO4_R {
        G3_IO4_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - G4_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g4_io1(&self) -> G4_IO1_R {
        G4_IO1_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - G4_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g4_io2(&self) -> G4_IO2_R {
        G4_IO2_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - G4_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g4_io3(&self) -> G4_IO3_R {
        G4_IO3_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - G4_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g4_io4(&self) -> G4_IO4_R {
        G4_IO4_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - G5_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g5_io1(&self) -> G5_IO1_R {
        G5_IO1_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - G5_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g5_io2(&self) -> G5_IO2_R {
        G5_IO2_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - G5_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g5_io3(&self) -> G5_IO3_R {
        G5_IO3_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 19 - G5_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g5_io4(&self) -> G5_IO4_R {
        G5_IO4_R::new(((self.bits >> 19) & 1) != 0)
    }
    ///Bit 20 - G6_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g6_io1(&self) -> G6_IO1_R {
        G6_IO1_R::new(((self.bits >> 20) & 1) != 0)
    }
    ///Bit 21 - G6_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g6_io2(&self) -> G6_IO2_R {
        G6_IO2_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 22 - G6_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g6_io3(&self) -> G6_IO3_R {
        G6_IO3_R::new(((self.bits >> 22) & 1) != 0)
    }
    ///Bit 23 - G6_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g6_io4(&self) -> G6_IO4_R {
        G6_IO4_R::new(((self.bits >> 23) & 1) != 0)
    }
    ///Bit 24 - G7_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g7_io1(&self) -> G7_IO1_R {
        G7_IO1_R::new(((self.bits >> 24) & 1) != 0)
    }
    ///Bit 25 - G7_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g7_io2(&self) -> G7_IO2_R {
        G7_IO2_R::new(((self.bits >> 25) & 1) != 0)
    }
    ///Bit 26 - G7_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g7_io3(&self) -> G7_IO3_R {
        G7_IO3_R::new(((self.bits >> 26) & 1) != 0)
    }
    ///Bit 27 - G7_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g7_io4(&self) -> G7_IO4_R {
        G7_IO4_R::new(((self.bits >> 27) & 1) != 0)
    }
    ///Bit 28 - G8_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g8_io1(&self) -> G8_IO1_R {
        G8_IO1_R::new(((self.bits >> 28) & 1) != 0)
    }
    ///Bit 29 - G8_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g8_io2(&self) -> G8_IO2_R {
        G8_IO2_R::new(((self.bits >> 29) & 1) != 0)
    }
    ///Bit 30 - G8_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g8_io3(&self) -> G8_IO3_R {
        G8_IO3_R::new(((self.bits >> 30) & 1) != 0)
    }
    ///Bit 31 - G8_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g8_io4(&self) -> G8_IO4_R {
        G8_IO4_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IOHCR")
            .field("g1_io1", &self.g1_io1())
            .field("g1_io2", &self.g1_io2())
            .field("g1_io3", &self.g1_io3())
            .field("g1_io4", &self.g1_io4())
            .field("g2_io1", &self.g2_io1())
            .field("g2_io2", &self.g2_io2())
            .field("g2_io3", &self.g2_io3())
            .field("g2_io4", &self.g2_io4())
            .field("g3_io1", &self.g3_io1())
            .field("g3_io2", &self.g3_io2())
            .field("g3_io3", &self.g3_io3())
            .field("g3_io4", &self.g3_io4())
            .field("g4_io1", &self.g4_io1())
            .field("g4_io2", &self.g4_io2())
            .field("g4_io3", &self.g4_io3())
            .field("g4_io4", &self.g4_io4())
            .field("g5_io1", &self.g5_io1())
            .field("g5_io2", &self.g5_io2())
            .field("g5_io3", &self.g5_io3())
            .field("g5_io4", &self.g5_io4())
            .field("g6_io1", &self.g6_io1())
            .field("g6_io2", &self.g6_io2())
            .field("g6_io3", &self.g6_io3())
            .field("g6_io4", &self.g6_io4())
            .field("g7_io1", &self.g7_io1())
            .field("g7_io2", &self.g7_io2())
            .field("g7_io3", &self.g7_io3())
            .field("g7_io4", &self.g7_io4())
            .field("g8_io1", &self.g8_io1())
            .field("g8_io2", &self.g8_io2())
            .field("g8_io3", &self.g8_io3())
            .field("g8_io4", &self.g8_io4())
            .finish()
    }
}
impl W {
    ///Bit 0 - G1_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g1_io1(&mut self) -> G1_IO1_W<IOHCRrs> {
        G1_IO1_W::new(self, 0)
    }
    ///Bit 1 - G1_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g1_io2(&mut self) -> G1_IO2_W<IOHCRrs> {
        G1_IO2_W::new(self, 1)
    }
    ///Bit 2 - G1_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g1_io3(&mut self) -> G1_IO3_W<IOHCRrs> {
        G1_IO3_W::new(self, 2)
    }
    ///Bit 3 - G1_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g1_io4(&mut self) -> G1_IO4_W<IOHCRrs> {
        G1_IO4_W::new(self, 3)
    }
    ///Bit 4 - G2_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g2_io1(&mut self) -> G2_IO1_W<IOHCRrs> {
        G2_IO1_W::new(self, 4)
    }
    ///Bit 5 - G2_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g2_io2(&mut self) -> G2_IO2_W<IOHCRrs> {
        G2_IO2_W::new(self, 5)
    }
    ///Bit 6 - G2_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g2_io3(&mut self) -> G2_IO3_W<IOHCRrs> {
        G2_IO3_W::new(self, 6)
    }
    ///Bit 7 - G2_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g2_io4(&mut self) -> G2_IO4_W<IOHCRrs> {
        G2_IO4_W::new(self, 7)
    }
    ///Bit 8 - G3_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g3_io1(&mut self) -> G3_IO1_W<IOHCRrs> {
        G3_IO1_W::new(self, 8)
    }
    ///Bit 9 - G3_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g3_io2(&mut self) -> G3_IO2_W<IOHCRrs> {
        G3_IO2_W::new(self, 9)
    }
    ///Bit 10 - G3_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g3_io3(&mut self) -> G3_IO3_W<IOHCRrs> {
        G3_IO3_W::new(self, 10)
    }
    ///Bit 11 - G3_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g3_io4(&mut self) -> G3_IO4_W<IOHCRrs> {
        G3_IO4_W::new(self, 11)
    }
    ///Bit 12 - G4_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g4_io1(&mut self) -> G4_IO1_W<IOHCRrs> {
        G4_IO1_W::new(self, 12)
    }
    ///Bit 13 - G4_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g4_io2(&mut self) -> G4_IO2_W<IOHCRrs> {
        G4_IO2_W::new(self, 13)
    }
    ///Bit 14 - G4_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g4_io3(&mut self) -> G4_IO3_W<IOHCRrs> {
        G4_IO3_W::new(self, 14)
    }
    ///Bit 15 - G4_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g4_io4(&mut self) -> G4_IO4_W<IOHCRrs> {
        G4_IO4_W::new(self, 15)
    }
    ///Bit 16 - G5_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g5_io1(&mut self) -> G5_IO1_W<IOHCRrs> {
        G5_IO1_W::new(self, 16)
    }
    ///Bit 17 - G5_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g5_io2(&mut self) -> G5_IO2_W<IOHCRrs> {
        G5_IO2_W::new(self, 17)
    }
    ///Bit 18 - G5_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g5_io3(&mut self) -> G5_IO3_W<IOHCRrs> {
        G5_IO3_W::new(self, 18)
    }
    ///Bit 19 - G5_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g5_io4(&mut self) -> G5_IO4_W<IOHCRrs> {
        G5_IO4_W::new(self, 19)
    }
    ///Bit 20 - G6_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g6_io1(&mut self) -> G6_IO1_W<IOHCRrs> {
        G6_IO1_W::new(self, 20)
    }
    ///Bit 21 - G6_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g6_io2(&mut self) -> G6_IO2_W<IOHCRrs> {
        G6_IO2_W::new(self, 21)
    }
    ///Bit 22 - G6_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g6_io3(&mut self) -> G6_IO3_W<IOHCRrs> {
        G6_IO3_W::new(self, 22)
    }
    ///Bit 23 - G6_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g6_io4(&mut self) -> G6_IO4_W<IOHCRrs> {
        G6_IO4_W::new(self, 23)
    }
    ///Bit 24 - G7_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g7_io1(&mut self) -> G7_IO1_W<IOHCRrs> {
        G7_IO1_W::new(self, 24)
    }
    ///Bit 25 - G7_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g7_io2(&mut self) -> G7_IO2_W<IOHCRrs> {
        G7_IO2_W::new(self, 25)
    }
    ///Bit 26 - G7_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g7_io3(&mut self) -> G7_IO3_W<IOHCRrs> {
        G7_IO3_W::new(self, 26)
    }
    ///Bit 27 - G7_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g7_io4(&mut self) -> G7_IO4_W<IOHCRrs> {
        G7_IO4_W::new(self, 27)
    }
    ///Bit 28 - G8_IO1 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g8_io1(&mut self) -> G8_IO1_W<IOHCRrs> {
        G8_IO1_W::new(self, 28)
    }
    ///Bit 29 - G8_IO2 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g8_io2(&mut self) -> G8_IO2_W<IOHCRrs> {
        G8_IO2_W::new(self, 29)
    }
    ///Bit 30 - G8_IO3 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g8_io3(&mut self) -> G8_IO3_W<IOHCRrs> {
        G8_IO3_W::new(self, 30)
    }
    ///Bit 31 - G8_IO4 Schmitt trigger hysteresis mode
    #[inline(always)]
    pub fn g8_io4(&mut self) -> G8_IO4_W<IOHCRrs> {
        G8_IO4_W::new(self, 31)
    }
}
/**I/O hysteresis control register

You can [`read`](crate::Reg::read) this register and get [`iohcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iohcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TSC:IOHCR)*/
pub struct IOHCRrs;
impl crate::RegisterSpec for IOHCRrs {
    type Ux = u32;
}
///`read()` method returns [`iohcr::R`](R) reader structure
impl crate::Readable for IOHCRrs {}
///`write(|w| ..)` method takes [`iohcr::W`](W) writer structure
impl crate::Writable for IOHCRrs {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
///`reset()` method sets IOHCR to value 0xffff_ffff
impl crate::Resettable for IOHCRrs {
    const RESET_VALUE: u32 = 0xffff_ffff;
}