1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
#[repr(C)]
#[derive(Debug)]
///Register block
pub struct RegisterBlock {
sr: SR,
_reserved1: [u8; 0x02],
dr: DR,
_reserved2: [u8; 0x02],
brr: BRR,
_reserved3: [u8; 0x02],
cr1: CR1,
_reserved4: [u8; 0x02],
cr2: CR2,
_reserved5: [u8; 0x02],
cr3: CR3,
_reserved6: [u8; 0x02],
gtpr: GTPR,
}
impl RegisterBlock {
///0x00 - UART4 SR
#[inline(always)]
pub const fn sr(&self) -> &SR {
&self.sr
}
///0x04 - UART4 DR
#[inline(always)]
pub const fn dr(&self) -> &DR {
&self.dr
}
///0x08 - UART4 BRR
#[inline(always)]
pub const fn brr(&self) -> &BRR {
&self.brr
}
///0x0c - UART4 CR1
#[inline(always)]
pub const fn cr1(&self) -> &CR1 {
&self.cr1
}
///0x10 - UART4 CR2
#[inline(always)]
pub const fn cr2(&self) -> &CR2 {
&self.cr2
}
///0x14 - UART4 CR3
#[inline(always)]
pub const fn cr3(&self) -> &CR3 {
&self.cr3
}
///0x18 - Guard Time and Prescaler Register
#[inline(always)]
pub const fn gtpr(&self) -> >PR {
&self.gtpr
}
}
/**SR (rw) register accessor: UART4 SR
You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#UART4:SR)
For information about available fields see [`mod@sr`] module*/
pub type SR = crate::Reg<sr::SRrs>;
///UART4 SR
pub mod sr;
pub use crate::stm32f107::usart1::brr;
pub use crate::stm32f107::usart1::cr1;
pub use crate::stm32f107::usart1::dr;
pub use crate::stm32f107::usart1::BRR;
pub use crate::stm32f107::usart1::CR1;
pub use crate::stm32f107::usart1::DR;
/**CR2 (rw) register accessor: UART4 CR2
You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#UART4:CR2)
For information about available fields see [`mod@cr2`] module*/
pub type CR2 = crate::Reg<cr2::CR2rs>;
///UART4 CR2
pub mod cr2;
/**CR3 (rw) register accessor: UART4 CR3
You can [`read`](crate::Reg::read) this register and get [`cr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#UART4:CR3)
For information about available fields see [`mod@cr3`] module*/
pub type CR3 = crate::Reg<cr3::CR3rs>;
///UART4 CR3
pub mod cr3;
/**GTPR (rw) register accessor: Guard Time and Prescaler Register
You can [`read`](crate::Reg::read) this register and get [`gtpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#UART4:GTPR)
For information about available fields see [`mod@gtpr`] module*/
pub type GTPR = crate::Reg<gtpr::GTPRrs>;
///Guard Time and Prescaler Register
pub mod gtpr;