use core::fmt::Debug;
use hal;
const RESET_DELAY_MS: u8 = 10;
pub trait DisplayInterface {
type Error;
fn send_command(&mut self, command: u8) -> Result<(), Self::Error>;
fn send_data(&mut self, data: &[u8]) -> Result<(), Self::Error>;
fn reset<D: hal::blocking::delay::DelayMs<u8>>(&mut self, delay: &mut D);
fn busy_wait(&self);
}
#[allow(dead_code)] pub struct Interface<SPI, CS, BUSY, DC, RESET> {
spi: SPI,
cs: CS,
busy: BUSY,
dc: DC,
reset: RESET,
}
impl<SPI, CS, BUSY, DC, RESET> Interface<SPI, CS, BUSY, DC, RESET>
where
SPI: hal::blocking::spi::Write<u8>,
CS: hal::digital::v2::OutputPin,
BUSY: hal::digital::v2::InputPin,
DC: hal::digital::v2::OutputPin,
RESET: hal::digital::v2::OutputPin,
{
pub fn new(spi: SPI, cs: CS, busy: BUSY, dc: DC, reset: RESET) -> Self {
Self {
spi,
cs,
busy,
dc,
reset,
}
}
fn write(&mut self, data: &[u8]) -> Result<(), SPI::Error> {
if cfg!(target_os = "linux") {
for data_chunk in data.chunks(4096) {
self.spi.write(data_chunk)?;
}
} else {
self.spi.write(data)?;
}
Ok(())
}
}
impl<SPI, CS, BUSY, DC, RESET> DisplayInterface for Interface<SPI, CS, BUSY, DC, RESET>
where
SPI: hal::blocking::spi::Write<u8>,
CS: hal::digital::v2::OutputPin,
CS::Error: Debug,
BUSY: hal::digital::v2::InputPin,
DC: hal::digital::v2::OutputPin,
DC::Error: Debug,
RESET: hal::digital::v2::OutputPin,
RESET::Error: Debug,
{
type Error = SPI::Error;
fn reset<D: hal::blocking::delay::DelayMs<u8>>(&mut self, delay: &mut D) {
self.reset.set_low().unwrap();
delay.delay_ms(RESET_DELAY_MS);
self.reset.set_high().unwrap();
delay.delay_ms(RESET_DELAY_MS);
}
fn send_command(&mut self, command: u8) -> Result<(), Self::Error> {
self.dc.set_low().unwrap();
self.write(&[command])?;
self.dc.set_high().unwrap();
Ok(())
}
fn send_data(&mut self, data: &[u8]) -> Result<(), Self::Error> {
self.dc.set_high().unwrap();
self.write(data)
}
fn busy_wait(&self) {
while match self.busy.is_high() {
Ok(x) => x,
_ => false,
} {}
}
}