mod fmux;
mod ioblk;
pub use fmux::*;
pub use ioblk::*;
use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
pub const FMUX_BASE: usize = 0x0300_1000;
pub const IOBLK_G1_BASE: usize = 0x0300_1800;
pub const IOBLK_G7_BASE: usize = 0x0300_1900;
pub const IOBLK_G10_BASE: usize = 0x0300_1A00;
pub const IOBLK_G12_BASE: usize = 0x0300_1C00;
pub const IOBLK_GRTC_BASE: usize = 0x0502_7000;
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum PullConfig {
None,
PullUp,
PullDown,
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum DriveStrength {
Level0 = 0,
Level1 = 1,
Level2 = 2,
Level3 = 3,
Level4 = 4,
Level5 = 5,
Level6 = 6,
Level7 = 7,
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum SchmittTriggerLevel {
Level0 = 0,
Level1 = 1,
Level2 = 2,
Level3 = 3,
}
pub struct Pinmux {
pub fmux: &'static FmuxRegisters,
ioblk_g1: &'static IoblkG1Registers,
ioblk_g7: &'static IoblkG7Registers,
ioblk_g10: &'static IoblkG10Registers,
ioblk_g12: &'static IoblkG12Registers,
ioblk_grtc: &'static IoblkGrtcRegisters,
}
impl Pinmux {
pub fn new() -> Self {
unsafe {
Self {
fmux: &*(FMUX_BASE as *const FmuxRegisters),
ioblk_g1: &*(IOBLK_G1_BASE as *const IoblkG1Registers),
ioblk_g7: &*(IOBLK_G7_BASE as *const IoblkG7Registers),
ioblk_g10: &*(IOBLK_G10_BASE as *const IoblkG10Registers),
ioblk_g12: &*(IOBLK_G12_BASE as *const IoblkG12Registers),
ioblk_grtc: &*(IOBLK_GRTC_BASE as *const IoblkGrtcRegisters),
}
}
}
pub fn new_with_offset(offset: usize) -> Self {
unsafe {
Self {
fmux: &*((FMUX_BASE + offset) as *const FmuxRegisters),
ioblk_g1: &*((IOBLK_G1_BASE + offset) as *const IoblkG1Registers),
ioblk_g7: &*((IOBLK_G7_BASE + offset) as *const IoblkG7Registers),
ioblk_g10: &*((IOBLK_G10_BASE + offset) as *const IoblkG10Registers),
ioblk_g12: &*((IOBLK_G12_BASE + offset) as *const IoblkG12Registers),
ioblk_grtc: &*((IOBLK_GRTC_BASE + offset) as *const IoblkGrtcRegisters),
}
}
}
pub unsafe fn from_base_addresses(
fmux_base: usize,
ioblk_g1_base: usize,
ioblk_g7_base: usize,
ioblk_g10_base: usize,
ioblk_g12_base: usize,
ioblk_grtc_base: usize,
) -> Self {
unsafe {
Self {
fmux: &*(fmux_base as *const FmuxRegisters),
ioblk_g1: &*(ioblk_g1_base as *const IoblkG1Registers),
ioblk_g7: &*(ioblk_g7_base as *const IoblkG7Registers),
ioblk_g10: &*(ioblk_g10_base as *const IoblkG10Registers),
ioblk_g12: &*(ioblk_g12_base as *const IoblkG12Registers),
ioblk_grtc: &*(ioblk_grtc_base as *const IoblkGrtcRegisters),
}
}
}
pub fn fmux(&self) -> &FmuxRegisters {
self.fmux
}
pub fn ioblk_g1(&self) -> &IoblkG1Registers {
self.ioblk_g1
}
pub fn ioblk_g7(&self) -> &IoblkG7Registers {
self.ioblk_g7
}
pub fn ioblk_g10(&self) -> &IoblkG10Registers {
self.ioblk_g10
}
pub fn ioblk_g12(&self) -> &IoblkG12Registers {
self.ioblk_g12
}
pub fn ioblk_grtc(&self) -> &IoblkGrtcRegisters {
self.ioblk_grtc
}
}
impl Default for Pinmux {
fn default() -> Self {
Self::new()
}
}
impl Pinmux {
pub fn set_sd0_clk_func(&self, func: FMUX_SD0_CLK::FSEL::Value) {
self.fmux.sd0_clk.write(FMUX_SD0_CLK::FSEL.val(func as u32));
}
pub fn get_sd0_clk_func(&self) -> u32 {
self.fmux.sd0_clk.read(FMUX_SD0_CLK::FSEL)
}
pub fn set_sd0_cmd_func(&self, func: FMUX_SD0_CMD::FSEL::Value) {
self.fmux.sd0_cmd.write(FMUX_SD0_CMD::FSEL.val(func as u32));
}
pub fn get_sd0_cmd_func(&self) -> u32 {
self.fmux.sd0_cmd.read(FMUX_SD0_CMD::FSEL)
}
pub fn set_sd0_d0_func(&self, func: FMUX_SD0_D0::FSEL::Value) {
self.fmux.sd0_d0.write(FMUX_SD0_D0::FSEL.val(func as u32));
}
pub fn get_sd0_d0_func(&self) -> u32 {
self.fmux.sd0_d0.read(FMUX_SD0_D0::FSEL)
}
pub fn set_sd0_d1_func(&self, func: FMUX_SD0_D1::FSEL::Value) {
self.fmux.sd0_d1.write(FMUX_SD0_D1::FSEL.val(func as u32));
}
pub fn get_sd0_d1_func(&self) -> u32 {
self.fmux.sd0_d1.read(FMUX_SD0_D1::FSEL)
}
pub fn set_sd0_d2_func(&self, func: FMUX_SD0_D2::FSEL::Value) {
self.fmux.sd0_d2.write(FMUX_SD0_D2::FSEL.val(func as u32));
}
pub fn get_sd0_d2_func(&self) -> u32 {
self.fmux.sd0_d2.read(FMUX_SD0_D2::FSEL)
}
pub fn set_sd0_d3_func(&self, func: FMUX_SD0_D3::FSEL::Value) {
self.fmux.sd0_d3.write(FMUX_SD0_D3::FSEL.val(func as u32));
}
pub fn get_sd0_d3_func(&self) -> u32 {
self.fmux.sd0_d3.read(FMUX_SD0_D3::FSEL)
}
pub fn get_aux0_input(&self) -> u32 {
self.fmux.aux0.read(FMUX_AUX0::FSEL)
}
}
impl Pinmux {
pub fn set_uart0_tx_func(&self, func: FMUX_UART0_TX::FSEL::Value) {
self.fmux.uart0_tx.write(FMUX_UART0_TX::FSEL.val(func as u32));
}
pub fn get_uart0_tx_func(&self) -> u32 {
self.fmux.uart0_tx.read(FMUX_UART0_TX::FSEL)
}
pub fn set_uart0_rx_func(&self, func: FMUX_UART0_RX::FSEL::Value) {
self.fmux.uart0_rx.write(FMUX_UART0_RX::FSEL.val(func as u32));
}
pub fn get_uart0_rx_func(&self) -> u32 {
self.fmux.uart0_rx.read(FMUX_UART0_RX::FSEL)
}
pub fn set_uart0_tx_pull(&self, pull: PullConfig) {
match pull {
PullConfig::None => {
self.ioblk_g7.uart0_tx.modify(IOBLK_REG::PU::CLEAR + IOBLK_REG::PD::CLEAR);
}
PullConfig::PullUp => {
self.ioblk_g7.uart0_tx.modify(IOBLK_REG::PU::SET + IOBLK_REG::PD::CLEAR);
}
PullConfig::PullDown => {
self.ioblk_g7.uart0_tx.modify(IOBLK_REG::PU::CLEAR + IOBLK_REG::PD::SET);
}
}
}
pub fn set_uart0_rx_pull(&self, pull: PullConfig) {
match pull {
PullConfig::None => {
self.ioblk_g7.uart0_rx.modify(IOBLK_REG::PU::CLEAR + IOBLK_REG::PD::CLEAR);
}
PullConfig::PullUp => {
self.ioblk_g7.uart0_rx.modify(IOBLK_REG::PU::SET + IOBLK_REG::PD::CLEAR);
}
PullConfig::PullDown => {
self.ioblk_g7.uart0_rx.modify(IOBLK_REG::PU::CLEAR + IOBLK_REG::PD::SET);
}
}
}
}
impl Pinmux {
pub fn set_iic0_scl_func(&self, func: FMUX_IIC0_SCL::FSEL::Value) {
self.fmux.iic0_scl.write(FMUX_IIC0_SCL::FSEL.val(func as u32));
}
pub fn get_iic0_scl_func(&self) -> u32 {
self.fmux.iic0_scl.read(FMUX_IIC0_SCL::FSEL)
}
pub fn set_iic0_sda_func(&self, func: FMUX_IIC0_SDA::FSEL::Value) {
self.fmux.iic0_sda.write(FMUX_IIC0_SDA::FSEL.val(func as u32));
}
pub fn get_iic0_sda_func(&self) -> u32 {
self.fmux.iic0_sda.read(FMUX_IIC0_SDA::FSEL)
}
}
impl Pinmux {
pub fn set_pwr_gpio0_func(&self, func: FMUX_PWR_GPIO0::FSEL::Value) {
self.fmux.pwr_gpio0.write(FMUX_PWR_GPIO0::FSEL.val(func as u32));
}
pub fn get_pwr_gpio0_func(&self) -> u32 {
self.fmux.pwr_gpio0.read(FMUX_PWR_GPIO0::FSEL)
}
pub fn set_pwr_gpio1_func(&self, func: FMUX_PWR_GPIO1::FSEL::Value) {
self.fmux.pwr_gpio1.write(FMUX_PWR_GPIO1::FSEL.val(func as u32));
}
pub fn get_pwr_gpio1_func(&self) -> u32 {
self.fmux.pwr_gpio1.read(FMUX_PWR_GPIO1::FSEL)
}
pub fn set_pwr_gpio2_func(&self, func: FMUX_PWR_GPIO2::FSEL::Value) {
self.fmux.pwr_gpio2.write(FMUX_PWR_GPIO2::FSEL.val(func as u32));
}
pub fn get_pwr_gpio2_func(&self) -> u32 {
self.fmux.pwr_gpio2.read(FMUX_PWR_GPIO2::FSEL)
}
}
impl Pinmux {
pub fn set_iic3_scl_on_sd1_cmd(&self) {
self.fmux.sd1_cmd.write(FMUX_SD1_CMD::FSEL.val(FMUX_SD1_CMD::FSEL::IIC3_SCL.into()));
}
pub fn set_iic3_sda_on_sd1_clk(&self) {
self.fmux.sd1_clk.write(FMUX_SD1_CLK::FSEL.val(FMUX_SD1_CLK::FSEL::IIC3_SDA.into()));
}
pub fn setup_iic3_pins(&self) {
self.set_iic3_scl_on_sd1_cmd();
self.set_iic3_sda_on_sd1_clk();
}
pub fn set_sd1_d3_func(&self, func: FMUX_SD1_D3::FSEL::Value) {
self.fmux.sd1_d3.write(FMUX_SD1_D3::FSEL.val(func as u32));
}
pub fn get_sd1_d3_func(&self) -> u32 {
self.fmux.sd1_d3.read(FMUX_SD1_D3::FSEL)
}
pub fn set_sd1_d2_func(&self, func: FMUX_SD1_D2::FSEL::Value) {
self.fmux.sd1_d2.write(FMUX_SD1_D2::FSEL.val(func as u32));
}
pub fn get_sd1_d2_func(&self) -> u32 {
self.fmux.sd1_d2.read(FMUX_SD1_D2::FSEL)
}
pub fn set_sd1_d1_func(&self, func: FMUX_SD1_D1::FSEL::Value) {
self.fmux.sd1_d1.write(FMUX_SD1_D1::FSEL.val(func as u32));
}
pub fn get_sd1_d1_func(&self) -> u32 {
self.fmux.sd1_d1.read(FMUX_SD1_D1::FSEL)
}
pub fn set_sd1_d0_func(&self, func: FMUX_SD1_D0::FSEL::Value) {
self.fmux.sd1_d0.write(FMUX_SD1_D0::FSEL.val(func as u32));
}
pub fn get_sd1_d0_func(&self) -> u32 {
self.fmux.sd1_d0.read(FMUX_SD1_D0::FSEL)
}
pub fn set_sd1_cmd_func(&self, func: FMUX_SD1_CMD::FSEL::Value) {
self.fmux.sd1_cmd.write(FMUX_SD1_CMD::FSEL.val(func as u32));
}
pub fn get_sd1_cmd_func(&self) -> u32 {
self.fmux.sd1_cmd.read(FMUX_SD1_CMD::FSEL)
}
pub fn set_sd1_clk_func(&self, func: FMUX_SD1_CLK::FSEL::Value) {
self.fmux.sd1_clk.write(FMUX_SD1_CLK::FSEL.val(func as u32));
}
pub fn get_sd1_clk_func(&self) -> u32 {
self.fmux.sd1_clk.read(FMUX_SD1_CLK::FSEL)
}
}
impl Pinmux {
pub fn set_iic3(&self) {
self.fmux.sd1_cmd.write(FMUX_SD1_CMD::FSEL::IIC3_SCL);
self.fmux.sd1_clk.write(FMUX_SD1_CLK::FSEL::IIC3_SDA);
}
pub fn set_pwm_7(&self) {
self.fmux.jtag_cpu_tms.write(FMUX_JTAG_CPU_TMS::FSEL::PWM_7);
}
pub fn set_uart1(&self) {
self.fmux.jtag_cpu_tms.write(FMUX_JTAG_CPU_TMS::FSEL::UART1_TX);
self.fmux.jtag_cpu_tck.write(FMUX_JTAG_CPU_TCK::FSEL::UART1_RX);
}
pub fn set_camera(&self) {
self.fmux.pwr_gpio1.write(FMUX_PWR_GPIO1::FSEL::PWR_GPIO_1);
self.fmux.pad_mipirx0n.write(FMUX_PAD_MIPIRX0N::FSEL::CAM_MCLK1);
self.fmux.pwr_wakeup0.write(FMUX_PWR_WAKEUP0::FSEL::IIC4_SCL);
self.fmux.pwr_button1.write(FMUX_PWR_BUTTON1::FSEL::IIC4_SDA);
}
}