use tock_registers::{register_bitfields, register_structs, registers::ReadWrite};
register_bitfields! [
u32,
pub FMUX_SD0_CLK [
FSEL OFFSET(0) NUMBITS(3) [
SDIO0_CLK = 0,
IIC1_SDA = 1,
SPI0_SCK = 2,
XGPIOA_7 = 3,
PWM_15 = 5,
EPHY_LNK_LED = 6,
DBG_0 = 7
]
],
pub FMUX_SD0_CMD [
FSEL OFFSET(0) NUMBITS(3) [
SDIO0_CMD = 0,
IIC1_SCL = 1,
SPI0_SDO = 2,
XGPIOA_8 = 3,
PWM_14 = 5,
EPHY_SPD_LED = 6,
DBG_1 = 7
]
],
pub FMUX_SD0_D0 [
FSEL OFFSET(0) NUMBITS(3) [
SDIO0_D0 = 0,
CAM_MCLK1 = 1,
SPI0_SDI = 2,
XGPIOA_9 = 3,
UART3_TX = 4,
PWM_13 = 5,
WG0_D0 = 6,
DBG_2 = 7
]
],
pub FMUX_SD0_D1 [
FSEL OFFSET(0) NUMBITS(3) [
SDIO0_D1 = 0,
IIC1_SDA = 1,
AUX0 = 2,
XGPIOA_10 = 3,
UART1_TX = 4,
PWM_12 = 5,
WG0_D1 = 6,
DBG_3 = 7
]
],
pub FMUX_SD0_D2 [
FSEL OFFSET(0) NUMBITS(3) [
SDIO0_D2 = 0,
IIC1_SCL = 1,
AUX1 = 2,
XGPIOA_11 = 3,
UART1_RX = 4,
PWM_11 = 5,
WG1_D0 = 6,
DBG_4 = 7
]
],
pub FMUX_SD0_D3 [
FSEL OFFSET(0) NUMBITS(3) [
SDIO0_D3 = 0,
CAM_MCLK0 = 1,
SPI0_CS_X = 2,
XGPIOA_12 = 3,
UART3_RX = 4,
PWM_10 = 5,
WG1_D1 = 6,
DBG_5 = 7
]
],
pub FMUX_SD0_CD [
FSEL OFFSET(0) NUMBITS(3) [
SDIO0_CD = 0,
XGPIOA_13 = 3
]
],
pub FMUX_SD0_PWR_EN [
FSEL OFFSET(0) NUMBITS(3) [
SDIO0_PWR_EN = 0,
XGPIOA_14 = 3
]
],
pub FMUX_SPK_EN [
FSEL OFFSET(0) NUMBITS(3) [
XGPIOA_15 = 3
]
],
pub FMUX_UART0_TX [
FSEL OFFSET(0) NUMBITS(3) [
UART0_TX = 0,
CAM_MCLK1 = 1,
PWM_4 = 2,
XGPIOA_16 = 3,
UART1_TX = 4,
AUX1 = 5,
DBG_6 = 7
]
],
pub FMUX_UART0_RX [
FSEL OFFSET(0) NUMBITS(3) [
UART0_RX = 0,
CAM_MCLK0 = 1,
PWM_5 = 2,
XGPIOA_17 = 3,
UART1_RX = 4,
AUX0 = 5,
DBG_7 = 7
]
],
pub FMUX_EMMC_DAT2 [
FSEL OFFSET(0) NUMBITS(3) [
EMMC_DAT2 = 0,
SPINOR_HOLD_X = 1,
SPINAND_HOLD = 2,
XGPIOA_26 = 3
]
],
pub FMUX_EMMC_CLK [
FSEL OFFSET(0) NUMBITS(3) [
EMMC_CLK = 0,
SPINOR_SCK = 1,
SPINAND_CLK = 2,
XGPIOA_22 = 3
]
],
pub FMUX_EMMC_DAT0 [
FSEL OFFSET(0) NUMBITS(3) [
EMMC_DAT0 = 0,
SPINOR_MOSI = 1,
SPINAND_MOSI = 2,
XGPIOA_25 = 3
]
],
pub FMUX_EMMC_DAT3 [
FSEL OFFSET(0) NUMBITS(3) [
EMMC_DAT3 = 0,
SPINOR_WP_X = 1,
SPINAND_WP = 2,
XGPIOA_27 = 3
]
],
pub FMUX_EMMC_CMD [
FSEL OFFSET(0) NUMBITS(3) [
EMMC_CMD = 0,
SPINOR_MISO = 1,
SPINAND_MISO = 2,
XGPIOA_23 = 3
]
],
pub FMUX_EMMC_DAT1 [
FSEL OFFSET(0) NUMBITS(3) [
EMMC_DAT1 = 0,
SPINOR_CS_X = 1,
SPINAND_CS = 2,
XGPIOA_24 = 3
]
],
pub FMUX_JTAG_CPU_TMS [
FSEL OFFSET(0) NUMBITS(3) [
CR_4WTMS = 0,
CAM_MCLK0 = 1,
PWM_7 = 2,
XGPIOA_19 = 3,
UART1_RTS = 4,
AUX0 = 5,
UART1_TX = 6,
VO_D28 = 7
]
],
pub FMUX_JTAG_CPU_TCK [
FSEL OFFSET(0) NUMBITS(3) [
CR_4WTCK = 0,
CAM_MCLK1 = 1,
PWM_6 = 2,
XGPIOA_18 = 3,
UART1_CTS = 4,
AUX1 = 5,
UART1_RX = 6,
VO_D29 = 7
]
],
pub FMUX_IIC0_SCL [
FSEL OFFSET(0) NUMBITS(3) [
CR_4WTDI = 0,
UART1_TX = 1,
UART2_TX = 2,
XGPIOA_28 = 3,
WG0_D0 = 5,
DBG_10 = 7
]
],
pub FMUX_IIC0_SDA [
FSEL OFFSET(0) NUMBITS(3) [
CR_4WTDO = 0,
UART1_RX = 1,
UART2_RX = 2,
XGPIOA_29 = 3,
WG0_D1 = 5,
WG1_D0 = 6,
DBG_11 = 7
]
],
pub FMUX_AUX0 [
FSEL OFFSET(0) NUMBITS(3) [
AUX0 = 0,
XGPIOA_30 = 3,
IIS1_MCLK = 4,
VO_D31 = 5,
WG1_D1 = 6,
DBG_12 = 7
]
],
pub FMUX_PWR_VBAT_DET [
FSEL OFFSET(0) NUMBITS(3) [
PWR_VBAT_DET = 0
]
],
pub FMUX_PWR_RSTN [
FSEL OFFSET(0) NUMBITS(3) [
PWR_RSTN = 0
]
],
pub FMUX_PWR_SEQ1 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_SEQ1 = 0,
PWR_GPIO_3 = 3
]
],
pub FMUX_PWR_SEQ2 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_SEQ2 = 0,
PWR_GPIO_4 = 3
]
],
pub FMUX_PWR_WAKEUP0 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_WAKEUP0 = 0,
PWR_IR0 = 1,
PWR_UART0_TX = 2,
PWR_GPIO_6 = 3,
UART1_TX = 4,
IIC4_SCL = 5,
EPHY_LNK_LED = 6,
WG2_D0 = 7
]
],
pub FMUX_PWR_BUTTON1 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_BUTTON1 = 0,
PWR_GPIO_8 = 3,
UART1_RX = 4,
IIC4_SDA = 5,
EPHY_SPD_LED = 6,
WG2_D1 = 7
]
],
pub FMUX_XTAL_XIN [
FSEL OFFSET(0) NUMBITS(3) [
PWR_XTAL_CLKIN = 0
]
],
pub FMUX_PWR_GPIO0 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_GPIO_0 = 0,
UART2_TX = 1,
PWR_UART0_RX = 2,
PWM_8 = 4
]
],
pub FMUX_PWR_GPIO1 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_GPIO_1 = 0,
UART2_RX = 1,
PWM_9 = 4,
EPHY_LNK_LED = 6,
WG0_D0 = 7
]
],
pub FMUX_PWR_GPIO2 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_GPIO_2 = 0,
PWR_SECTICK = 2,
PWM_10 = 4,
EPHY_SPD_LED = 6,
WG0_D1 = 7
]
],
pub FMUX_ADC1 [
FSEL OFFSET(0) NUMBITS(3) [
ADC1 = 0
]
],
pub FMUX_USB_VBUS_DET [
FSEL OFFSET(0) NUMBITS(3) [
USB_VBUS_DET = 0,
XGPIOB_6 = 3,
CAM_MCLK0 = 4,
CAM_MCLK1 = 5
]
],
pub FMUX_MUX_SPI1_MISO [
FSEL OFFSET(0) NUMBITS(3) [
UART3_RTS = 1,
IIC1_SDA = 2,
XGPIOB_8 = 3,
PWM_9 = 4,
KEY_COL1 = 5,
SPI1_SDI = 6,
DBG_14 = 7
]
],
pub FMUX_MUX_SPI1_MOSI [
FSEL OFFSET(0) NUMBITS(3) [
UART3_RX = 1,
IIC1_SCL = 2,
XGPIOB_7 = 3,
PWM_8 = 4,
KEY_COL0 = 5,
SPI1_SDO = 6,
DBG_13 = 7
]
],
pub FMUX_MUX_SPI1_CS [
FSEL OFFSET(0) NUMBITS(3) [
UART3_CTS = 1,
CAM_MCLK0 = 2,
XGPIOB_10 = 3,
PWM_11 = 4,
KEY_ROW3 = 5,
SPI1_CS_X = 6,
DBG_16 = 7
]
],
pub FMUX_MUX_SPI1_SCK [
FSEL OFFSET(0) NUMBITS(3) [
UART3_TX = 1,
CAM_MCLK1 = 2,
XGPIOB_9 = 3,
PWM_10 = 4,
KEY_ROW2 = 5,
SPI1_SCK = 6,
DBG_15 = 7
]
],
pub FMUX_PAD_ETH_TXP [
FSEL OFFSET(0) NUMBITS(3) [
UART3_RX = 1,
IIC1_SCL = 2,
XGPIOB_25 = 3,
PWM_13 = 4,
CAM_MCLK0 = 5,
SPI1_SDO = 6,
IIS2_LRCK = 7
]
],
pub FMUX_PAD_ETH_RXP [
FSEL OFFSET(0) NUMBITS(3) [
UART3_TX = 1,
CAM_MCLK1 = 2,
XGPIOB_27 = 3,
PWM_15 = 4,
CAM_HS0 = 5,
SPI1_SCK = 6,
IIS2_DO = 7
]
],
pub FMUX_PAD_ETH_RXM [
FSEL OFFSET(0) NUMBITS(3) [
UART3_CTS = 1,
CAM_MCLK0 = 2,
XGPIOB_26 = 3,
PWM_14 = 4,
CAM_VS0 = 5,
SPI1_CS_X = 6,
IIS2_DI = 7
]
],
pub FMUX_PAD_MIPIRX4N [
FSEL OFFSET(0) NUMBITS(3) [
CR_SCL0 = 0,
VI0_CLK = 1,
VI1_D13 = 2,
XGPIOC_2 = 3,
IIC1_SDA = 4,
CAM_MCLK0 = 5,
KEY_ROW0 = 6,
MUX_SPI1_SCK = 7
]
],
pub FMUX_PAD_MIPIRX4P [
FSEL OFFSET(0) NUMBITS(3) [
CR_SDA0 = 0,
VI0_D0 = 1,
VI1_D14 = 2,
XGPIOC_3 = 3,
IIC1_SCL = 4,
CAM_MCLK1 = 5,
KEY_ROW1 = 6,
MUX_SPI1_CS = 7
]
],
pub FMUX_PAD_MIPIRX3N [
FSEL OFFSET(0) NUMBITS(3) [
CR_2WTMS = 0,
VI0_D1 = 1,
VI1_D15 = 2,
XGPIOC_4 = 3,
CAM_MCLK0 = 4,
MUX_SPI1_MISO = 7
]
],
pub FMUX_PAD_MIPIRX3P [
FSEL OFFSET(0) NUMBITS(3) [
CR_2WTCK = 0,
VI0_D2 = 1,
VI1_D16 = 2,
XGPIOC_5 = 3,
MUX_SPI1_MOSI = 7
]
],
pub FMUX_PAD_MIPIRX2N [
FSEL OFFSET(0) NUMBITS(3) [
VI0_D3 = 1,
VO_D10 = 2,
XGPIOC_6 = 3,
VI1_D17 = 4,
IIC4_SCL = 5,
DBG_6 = 7
]
],
pub FMUX_PAD_MIPIRX2P [
FSEL OFFSET(0) NUMBITS(3) [
VI0_D4 = 1,
VO_D9 = 2,
XGPIOC_7 = 3,
VI1_D18 = 4,
IIC4_SDA = 5,
DBG_7 = 7
]
],
pub FMUX_PAD_MIPIRX1N [
FSEL OFFSET(0) NUMBITS(3) [
VI0_D5 = 1,
VO_D8 = 2,
XGPIOC_8 = 3,
KEY_ROW3 = 6,
DBG_8 = 7
]
],
pub FMUX_PAD_MIPIRX1P [
FSEL OFFSET(0) NUMBITS(3) [
VI0_D6 = 1,
VO_D7 = 2,
XGPIOC_9 = 3,
IIC1_SDA = 4,
KEY_ROW2 = 6,
DBG_9 = 7
]
],
pub FMUX_PAD_MIPIRX0N [
FSEL OFFSET(0) NUMBITS(3) [
VI0_D7 = 1,
VO_D6 = 2,
XGPIOC_10 = 3,
IIC1_SCL = 4,
CAM_MCLK1 = 5,
DBG_10 = 7
]
],
pub FMUX_PAD_MIPIRX0P [
FSEL OFFSET(0) NUMBITS(3) [
VI0_D8 = 1,
VO_D5 = 2,
XGPIOC_11 = 3,
CAM_MCLK0 = 4,
DBG_11 = 7
]
],
pub FMUX_PAD_MIPI_TXM2 [
FSEL OFFSET(0) NUMBITS(3) [
CR_SDA0 = 0,
VI0_D13 = 1,
VO_D0 = 2,
XGPIOC_16 = 3,
IIC1_SDA = 4,
PWM_8 = 5,
SPI0_SCK = 6,
SD1_D2 = 7
]
],
pub FMUX_PAD_MIPI_TXP2 [
FSEL OFFSET(0) NUMBITS(3) [
CR_SCL0 = 0,
VI0_D14 = 1,
VO_CLK0 = 2,
XGPIOC_17 = 3,
IIC1_SCL = 4,
PWM_9 = 5,
SPI0_CS_X = 6,
SD1_D3 = 7
]
],
pub FMUX_PAD_MIPI_TXM1 [
FSEL OFFSET(0) NUMBITS(3) [
CR_2WTMS = 0,
VI0_D11 = 1,
VO_D2 = 2,
XGPIOC_14 = 3,
IIC2_SDA = 4,
PWM_10 = 5,
SPI0_SDO = 6,
DBG_14 = 7
]
],
pub FMUX_PAD_MIPI_TXP1 [
FSEL OFFSET(0) NUMBITS(3) [
CR_2WTCK = 0,
VI0_D12 = 1,
VO_D1 = 2,
XGPIOC_15 = 3,
IIC2_SCL = 4,
PWM_11 = 5,
SPI0_SDI = 6,
DBG_15 = 7
]
],
pub FMUX_PAD_MIPI_TXM0 [
FSEL OFFSET(0) NUMBITS(3) [
VI0_D9 = 1,
VO_D4 = 2,
XGPIOC_12 = 3,
CAM_MCLK1 = 4,
PWM_14 = 5,
CAM_VS0 = 6,
DBG_12 = 7
]
],
pub FMUX_PAD_MIPI_TXP0 [
FSEL OFFSET(0) NUMBITS(3) [
VI0_D10 = 1,
VO_D3 = 2,
XGPIOC_13 = 3,
CAM_MCLK0 = 4,
PWM_15 = 5,
CAM_HS0 = 6,
DBG_13 = 7
]
],
pub FMUX_PAD_AUD_AINL_MIC [
FSEL OFFSET(0) NUMBITS(3) [
XGPIOC_23 = 3,
IIS1_BCLK = 4,
IIS2_BCLK = 5
]
],
pub FMUX_PAD_AUD_AOUTR [
FSEL OFFSET(0) NUMBITS(3) [
XGPIOC_24 = 3,
IIS1_DI = 4,
IIS2_DO = 5,
IIS1_DO = 6
]
],
pub FMUX_GPIO_RTX [
FSEL OFFSET(0) NUMBITS(3) [
XGPIOB_23 = 3,
PWM_1 = 4,
CAM_MCLK0 = 5
]
],
pub FMUX_GPIO_ZQ [
FSEL OFFSET(0) NUMBITS(3) [
PWR_GPIO_24 = 3,
PWM_2 = 4
]
],
pub FMUX_PKG_TYPE [
FSEL OFFSET(0) NUMBITS(3) []
],
pub FMUX_SD1_D3 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_SD1_D3_VO32 = 0,
SPI2_CS_X = 1,
IIC1_SCL = 2,
PWR_GPIO_18 = 3,
CAM_MCLK0 = 4,
UART3_CTS = 5,
PWR_SPINOR1_CS_X = 6,
PWM_4 = 7
]
],
pub FMUX_SD1_D2 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_SD1_D2_VO33 = 0,
IIC1_SCL = 1,
UART2_TX = 2,
PWR_GPIO_19 = 3,
CAM_MCLK0 = 4,
UART3_TX = 5,
PWR_SPINOR1_HOLD_X = 6,
PWM_5 = 7
]
],
pub FMUX_SD1_D1 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_SD1_D1_VO34 = 0,
IIC1_SDA = 1,
UART2_RX = 2,
PWR_GPIO_20 = 3,
CAM_MCLK1 = 4,
UART3_RX = 5,
PWR_SPINOR1_WP_X = 6,
PWM_6 = 7
]
],
pub FMUX_SD1_D0 [
FSEL OFFSET(0) NUMBITS(3) [
PWR_SD1_D0_VO35 = 0,
SPI2_SDI = 1,
IIC1_SDA = 2,
PWR_GPIO_21 = 3,
CAM_MCLK1 = 4,
UART3_RTS = 5,
PWR_SPINOR1_MISO = 6,
PWM_7 = 7
]
],
pub FMUX_SD1_CMD [
FSEL OFFSET(0) NUMBITS(3) [
PWR_SD1_CMD_VO36 = 0,
SPI2_SDO = 1,
IIC3_SCL = 2,
PWR_GPIO_22 = 3,
CAM_VS0 = 4,
EPHY_LNK_LED = 5,
PWR_SPINOR1_MOSI = 6,
PWM_8 = 7
]
],
pub FMUX_SD1_CLK [
FSEL OFFSET(0) NUMBITS(3) [
PWR_SD1_CLK_VO37 = 0,
SPI2_SCK = 1,
IIC3_SDA = 2,
PWR_GPIO_23 = 3,
CAM_HS0 = 4,
EPHY_SPD_LED = 5,
PWR_SPINOR1_SCK = 6,
PWM_9 = 7
]
],
pub FMUX_PWM0_BUCK [
FSEL OFFSET(0) NUMBITS(3) [
XGPIOB_0 = 3
]
]
];
register_structs! {
pub FmuxRegisters {
(0x000 => _reserved0),
(0x01C => pub sd0_clk: ReadWrite<u32, FMUX_SD0_CLK::Register>),
(0x020 => pub sd0_cmd: ReadWrite<u32, FMUX_SD0_CMD::Register>),
(0x024 => pub sd0_d0: ReadWrite<u32, FMUX_SD0_D0::Register>),
(0x028 => pub sd0_d1: ReadWrite<u32, FMUX_SD0_D1::Register>),
(0x02C => pub sd0_d2: ReadWrite<u32, FMUX_SD0_D2::Register>),
(0x030 => pub sd0_d3: ReadWrite<u32, FMUX_SD0_D3::Register>),
(0x034 => pub sd0_cd: ReadWrite<u32, FMUX_SD0_CD::Register>),
(0x038 => pub sd0_pwr_en: ReadWrite<u32, FMUX_SD0_PWR_EN::Register>),
(0x03C => pub spk_en: ReadWrite<u32, FMUX_SPK_EN::Register>),
(0x040 => pub uart0_tx: ReadWrite<u32, FMUX_UART0_TX::Register>),
(0x044 => pub uart0_rx: ReadWrite<u32, FMUX_UART0_RX::Register>),
(0x048 => _reserved1),
(0x04C => pub emmc_dat2: ReadWrite<u32, FMUX_EMMC_DAT2::Register>),
(0x050 => pub emmc_clk: ReadWrite<u32, FMUX_EMMC_CLK::Register>),
(0x054 => pub emmc_dat0: ReadWrite<u32, FMUX_EMMC_DAT0::Register>),
(0x058 => pub emmc_dat3: ReadWrite<u32, FMUX_EMMC_DAT3::Register>),
(0x05C => pub emmc_cmd: ReadWrite<u32, FMUX_EMMC_CMD::Register>),
(0x060 => pub emmc_dat1: ReadWrite<u32, FMUX_EMMC_DAT1::Register>),
(0x064 => pub jtag_cpu_tms: ReadWrite<u32, FMUX_JTAG_CPU_TMS::Register>),
(0x068 => pub jtag_cpu_tck: ReadWrite<u32, FMUX_JTAG_CPU_TCK::Register>),
(0x06C => _reserved2),
(0x070 => pub iic0_scl: ReadWrite<u32, FMUX_IIC0_SCL::Register>),
(0x074 => pub iic0_sda: ReadWrite<u32, FMUX_IIC0_SDA::Register>),
(0x078 => pub aux0: ReadWrite<u32, FMUX_AUX0::Register>),
(0x07C => pub pwr_vbat_det: ReadWrite<u32, FMUX_PWR_VBAT_DET::Register>),
(0x080 => pub pwr_rstn: ReadWrite<u32, FMUX_PWR_RSTN::Register>),
(0x084 => pub pwr_seq1: ReadWrite<u32, FMUX_PWR_SEQ1::Register>),
(0x088 => pub pwr_seq2: ReadWrite<u32, FMUX_PWR_SEQ2::Register>),
(0x08C => _reserved3),
(0x090 => pub pwr_wakeup0: ReadWrite<u32, FMUX_PWR_WAKEUP0::Register>),
(0x094 => _reserved4),
(0x098 => pub pwr_button1: ReadWrite<u32, FMUX_PWR_BUTTON1::Register>),
(0x09C => _reserved5),
(0x0A0 => pub xtal_xin: ReadWrite<u32, FMUX_XTAL_XIN::Register>),
(0x0A4 => pub pwr_gpio0: ReadWrite<u32, FMUX_PWR_GPIO0::Register>),
(0x0A8 => pub pwr_gpio1: ReadWrite<u32, FMUX_PWR_GPIO1::Register>),
(0x0AC => pub pwr_gpio2: ReadWrite<u32, FMUX_PWR_GPIO2::Register>),
(0x0B0 => _reserved6),
(0x0D0 => pub sd1_d3: ReadWrite<u32, FMUX_SD1_D3::Register>),
(0x0D4 => pub sd1_d2: ReadWrite<u32, FMUX_SD1_D2::Register>),
(0x0D8 => pub sd1_d1: ReadWrite<u32, FMUX_SD1_D1::Register>),
(0x0DC => pub sd1_d0: ReadWrite<u32, FMUX_SD1_D0::Register>),
(0x0E0 => pub sd1_cmd: ReadWrite<u32, FMUX_SD1_CMD::Register>),
(0x0E4 => pub sd1_clk: ReadWrite<u32, FMUX_SD1_CLK::Register>),
(0x0E8 => _reserved6a),
(0x0EC => pub pwm0_buck: ReadWrite<u32, FMUX_PWM0_BUCK::Register>),
(0x0F0 => _reserved6b),
(0x0F8 => pub adc1: ReadWrite<u32, FMUX_ADC1::Register>),
(0x0FC => pub usb_vbus_det: ReadWrite<u32, FMUX_USB_VBUS_DET::Register>),
(0x100 => _reserved7),
(0x104 => pub pkg_type0: ReadWrite<u32, FMUX_PKG_TYPE::Register>),
(0x108 => _reserved8),
(0x10C => pub pkg_type1: ReadWrite<u32, FMUX_PKG_TYPE::Register>),
(0x110 => pub pkg_type2: ReadWrite<u32, FMUX_PKG_TYPE::Register>),
(0x114 => pub mux_spi1_miso: ReadWrite<u32, FMUX_MUX_SPI1_MISO::Register>),
(0x118 => pub mux_spi1_mosi: ReadWrite<u32, FMUX_MUX_SPI1_MOSI::Register>),
(0x11C => pub mux_spi1_cs: ReadWrite<u32, FMUX_MUX_SPI1_CS::Register>),
(0x120 => pub mux_spi1_sck: ReadWrite<u32, FMUX_MUX_SPI1_SCK::Register>),
(0x124 => _reserved9),
(0x128 => pub pad_eth_txp: ReadWrite<u32, FMUX_PAD_ETH_TXP::Register>),
(0x12C => pub pad_eth_rxp: ReadWrite<u32, FMUX_PAD_ETH_RXP::Register>),
(0x130 => pub pad_eth_rxm: ReadWrite<u32, FMUX_PAD_ETH_RXM::Register>),
(0x134 => _reserved10),
(0x16C => pub pad_mipirx4n: ReadWrite<u32, FMUX_PAD_MIPIRX4N::Register>),
(0x170 => pub pad_mipirx4p: ReadWrite<u32, FMUX_PAD_MIPIRX4P::Register>),
(0x174 => pub pad_mipirx3n: ReadWrite<u32, FMUX_PAD_MIPIRX3N::Register>),
(0x178 => pub pad_mipirx3p: ReadWrite<u32, FMUX_PAD_MIPIRX3P::Register>),
(0x17C => pub pad_mipirx2n: ReadWrite<u32, FMUX_PAD_MIPIRX2N::Register>),
(0x180 => pub pad_mipirx2p: ReadWrite<u32, FMUX_PAD_MIPIRX2P::Register>),
(0x184 => pub pad_mipirx1n: ReadWrite<u32, FMUX_PAD_MIPIRX1N::Register>),
(0x188 => pub pad_mipirx1p: ReadWrite<u32, FMUX_PAD_MIPIRX1P::Register>),
(0x18C => pub pad_mipirx0n: ReadWrite<u32, FMUX_PAD_MIPIRX0N::Register>),
(0x190 => pub pad_mipirx0p: ReadWrite<u32, FMUX_PAD_MIPIRX0P::Register>),
(0x194 => _reserved11),
(0x1A4 => pub pad_mipi_txm2: ReadWrite<u32, FMUX_PAD_MIPI_TXM2::Register>),
(0x1A8 => pub pad_mipi_txp2: ReadWrite<u32, FMUX_PAD_MIPI_TXP2::Register>),
(0x1AC => pub pad_mipi_txm1: ReadWrite<u32, FMUX_PAD_MIPI_TXM1::Register>),
(0x1B0 => pub pad_mipi_txp1: ReadWrite<u32, FMUX_PAD_MIPI_TXP1::Register>),
(0x1B4 => pub pad_mipi_txm0: ReadWrite<u32, FMUX_PAD_MIPI_TXM0::Register>),
(0x1B8 => pub pad_mipi_txp0: ReadWrite<u32, FMUX_PAD_MIPI_TXP0::Register>),
(0x1BC => pub pad_aud_ainl_mic: ReadWrite<u32, FMUX_PAD_AUD_AINL_MIC::Register>),
(0x1C0 => _reserved12),
(0x1C8 => pub pad_aud_aoutr: ReadWrite<u32, FMUX_PAD_AUD_AOUTR::Register>),
(0x1CC => pub gpio_rtx: ReadWrite<u32, FMUX_GPIO_RTX::Register>),
(0x1D0 => pub gpio_zq: ReadWrite<u32, FMUX_GPIO_ZQ::Register>),
(0x1D4 => @END),
}
}