#[doc = "Reader of register CHINTENCLR"]
pub type R = crate::R<u8, super::CHINTENCLR>;
#[doc = "Writer for register CHINTENCLR"]
pub type W = crate::W<u8, super::CHINTENCLR>;
#[doc = "Register CHINTENCLR `reset()`'s with value 0"]
impl crate::ResetValue for super::CHINTENCLR {
type Type = u8;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "Reader of field `OVR`"]
pub type OVR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `OVR`"]
pub struct OVR_W<'a> {
w: &'a mut W,
}
impl<'a> OVR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | ((value as u8) & 0x01);
self.w
}
}
#[doc = "Reader of field `EVD`"]
pub type EVD_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `EVD`"]
pub struct EVD_W<'a> {
w: &'a mut W,
}
impl<'a> EVD_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u8) & 0x01) << 1);
self.w
}
}
impl R {
#[doc = "Bit 0 - Channel Overrun Interrupt Disable"]
#[inline(always)]
pub fn ovr(&self) -> OVR_R {
OVR_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - Channel Event Detected Interrupt Disable"]
#[inline(always)]
pub fn evd(&self) -> EVD_R {
EVD_R::new(((self.bits >> 1) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 0 - Channel Overrun Interrupt Disable"]
#[inline(always)]
pub fn ovr(&mut self) -> OVR_W {
OVR_W { w: self }
}
#[doc = "Bit 1 - Channel Event Detected Interrupt Disable"]
#[inline(always)]
pub fn evd(&mut self) -> EVD_W {
EVD_W { w: self }
}
}