// asm = { label | inst }
label = @{ SOI ~ (ident | label_num) ~ ":" ~ EOI }
label_num = @{ ASCII_DIGIT+ }
inst = { inst_name ~ inst_args? }
inst_name = @{ inst_name_part ~ ("." ~ inst_name_part )* }
inst_name_part = @{ ASCII_ALPHA_LOWER+ ~ (ASCII_DIGIT | ASCII_ALPHA_LOWER)* }
inst_args = _{ inst_arg ~ ("," ~ inst_arg)* }
inst_arg = { inst_arg_mask | inst_arg_simple | inst_arg_addr | integer | inst_arg_variable }
inst_arg_variable = { "{" ~ (ident | int)? ~ "}" }
inst_arg_simple = @{ ASCII_ALPHA_LOWER+ ~ ASCII_DIGIT* }
inst_arg_addr = _{ "(" ~ inst_arg_simple ~ ")" }
ident = @{ (ASCII_ALPHA | "_")+ ~ (ASCII_ALPHANUMERIC | "_")* }
// from: [riscv-v-spec/v-spec.adoc]
// Even though current vector extensions only support one vector
// mask register `v0` and only the true form of predication, the assembly
// syntax writes it out in full to be compatible with future extensions
// that might add a mask register specifier and supporting both true and
// complement masking. The `.t` suffix on the masking operand also helps
// to visually encode the use of a mask.
inst_arg_mask = @{ "v0.t" }
integer = @{ ("-")? ~ (hexint | int) }
hexint = @{ ("0x" | "0X" ) ~ ASCII_HEX_DIGIT+ }
int = @{ "0" | (ASCII_NONZERO_DIGIT ~ ASCII_DIGIT*) }
WHITESPACE = _{ " " | "\t" | NEWLINE }
COMMENT = _{ ";" ~ (!NEWLINE ~ ANY)* }