rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158

//! # Hart Address Translation Tests
//!
//! Tests for address translation. Cache-walk-latency tests that exercised
//! the deleted `SystemState::simulate_memory_access` synchronous helper were
//! superseded by integration tests that drive the packet-based cache
//! hierarchy through a `Simulator`.

use crate::common::{AccessType, VirtAddr};
use crate::config::Config;
use crate::system::SystemState;
use crate::uarch::mmu::TranslateOutcome;

fn create_test_cpu() -> SystemState {
    let config = Config::default();
    let mut state = SystemState::build(&config, "");
    state.direct_mode = true;
    state
}

#[test]
fn test_translate_direct_mode_valid_address() {
    let mut sys = create_test_cpu();
    let mut state = sys.core_ctx(0);
    state.direct_mode = true;

    let vaddr = VirtAddr::new(0x8000_0000);
    let TranslateOutcome::Ready(result) = state.translate(vaddr, AccessType::Read, 4) else {
        panic!("NeedPte not expected in direct mode")
    };

    assert_eq!(result.trap, None);
    assert_eq!(result.paddr.val(), 0x8000_0000);
}

#[test]
fn test_translate_direct_mode_different_addresses() {
    let mut sys = create_test_cpu();
    let mut state = sys.core_ctx(0);
    state.direct_mode = true;

    let test_addrs = vec![0x8000_0000u64, 0x8000_1000u64, 0x8000_2000u64];

    for addr in test_addrs {
        let vaddr = VirtAddr::new(addr);
        let TranslateOutcome::Ready(result) = state.translate(vaddr, AccessType::Read, 4) else {
            panic!("NeedPte not expected in direct mode")
        };
        assert_eq!(result.paddr.val(), addr);
    }
}

#[test]
fn test_translate_direct_mode_fetch_access() {
    let mut sys = create_test_cpu();
    let mut state = sys.core_ctx(0);
    state.direct_mode = true;

    let vaddr = VirtAddr::new(0x8000_0000);
    let TranslateOutcome::Ready(result) = state.translate(vaddr, AccessType::Fetch, 4) else {
        panic!("NeedPte not expected in direct mode")
    };
    assert_eq!(result.trap, None);
}

#[test]
fn test_translate_direct_mode_write_access() {
    let mut sys = create_test_cpu();
    let mut state = sys.core_ctx(0);
    state.direct_mode = true;

    let vaddr = VirtAddr::new(0x8000_0000);
    let TranslateOutcome::Ready(result) = state.translate(vaddr, AccessType::Write, 4) else {
        panic!("NeedPte not expected in direct mode")
    };
    assert_eq!(result.trap, None);
}

#[test]
fn test_translate_preserves_translation_cost() {
    let mut sys = create_test_cpu();
    let mut state = sys.core_ctx(0);
    state.direct_mode = true;

    let vaddr = VirtAddr::new(0x8000_0000);
    let TranslateOutcome::Ready(result) = state.translate(vaddr, AccessType::Read, 4) else {
        panic!("NeedPte not expected in direct mode")
    };
    assert_eq!(result.cycles, 0);
}

#[test]
fn test_translate_multiple_calls() {
    let mut sys = create_test_cpu();
    let mut state = sys.core_ctx(0);
    state.direct_mode = true;

    for _ in 0..5 {
        let vaddr = VirtAddr::new(0x8000_0000);
        let TranslateOutcome::Ready(result) = state.translate(vaddr, AccessType::Read, 4) else {
            panic!("NeedPte not expected in direct mode")
        };
        assert_eq!(result.paddr.val(), 0x8000_0000);
    }
}

#[test]
fn test_translate_invalid_address_fetch() {
    let mut sys = create_test_cpu();
    let mut state = sys.core_ctx(0);
    state.direct_mode = true;

    let vaddr = VirtAddr::new(0xFFFF_FFFF_FFFF_FFFF);
    let TranslateOutcome::Ready(result) = state.translate(vaddr, AccessType::Fetch, 4) else {
        panic!("NeedPte not expected in direct mode")
    };
    assert!(result.trap.is_some());
}

#[test]
fn test_translate_invalid_address_read() {
    let mut sys = create_test_cpu();
    let mut state = sys.core_ctx(0);
    state.direct_mode = true;

    let vaddr = VirtAddr::new(0xFFFF_FFFF_FFFF_FFFF);
    let TranslateOutcome::Ready(result) = state.translate(vaddr, AccessType::Read, 4) else {
        panic!("NeedPte not expected in direct mode")
    };
    assert!(result.trap.is_some());
}

#[test]
fn test_translate_invalid_address_write() {
    let mut sys = create_test_cpu();
    let mut state = sys.core_ctx(0);
    state.direct_mode = true;

    let vaddr = VirtAddr::new(0xFFFF_FFFF_FFFF_FFFF);
    let TranslateOutcome::Ready(result) = state.translate(vaddr, AccessType::Write, 4) else {
        panic!("NeedPte not expected in direct mode")
    };
    assert!(result.trap.is_some());
}

#[test]
fn test_translate_with_direct_mode_false() {
    let mut sys = create_test_cpu();
    let mut state = sys.core_ctx(0);
    state.direct_mode = false;

    let vaddr = VirtAddr::new(0x8000_0000);
    // In M-mode with no paging (default SATP=Bare), translation completes
    // immediately and identity-maps. Walks only fire under Sv39+.
    let TranslateOutcome::Ready(result) = state.translate(vaddr, AccessType::Read, 4) else {
        panic!("M-mode + Bare should not require a walk")
    };
    assert!(result.trap.is_some() || result.paddr.val() == 0x8000_0000);
}