rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
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//! RISC-V Atomic Extension (A).
//!
//! Defines constants and logic for Atomic Memory Operations (AMO).
//! AMOs perform a read-modify-write operation in a single instruction.

pub mod funct3;

pub mod funct5;

pub mod opcodes;

/// The `aq` (acquire) ordering bit of an AMO, LR or SC instruction.
pub const AQ: u32 = 1 << 26;

/// The `rl` (release) ordering bit of an AMO, LR or SC instruction.
pub const RL: u32 = 1 << 25;