rvsim-core 2.0.0

A cycle-level RISC-V 64-bit system simulator.
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//! What vector configuration instructions establish.

use crate::exec::compute::vector::vsetvl::execute_vsetvl;
use crate::exec::inst::Inst;
use crate::isa::encoding::rvv::encoding as v_enc;
use crate::isa::op::VectorOp;
use crate::isa::rvv::{VectorConfig, Vlen};

/// The configuration the `vsetvl` `inst` establishes when `vl` is currently
/// `current_vl`.
#[must_use]
pub fn vector_config(
    inst: &Inst,
    rs1_value: u64,
    rs2_value: u64,
    vlen: Vlen,
    current_vl: u64,
) -> VectorConfig {
    let (avl, requested_vtype, rs1_is_zero) = match inst.ctrl.vec_op {
        VectorOp::Vsetvli => (rs1_value, v_enc::zimm_vsetvli(inst.bits), inst.rs1.is_zero()),
        VectorOp::Vsetivli => {
            (v_enc::uimm_vsetivli(inst.bits), v_enc::zimm_vsetivli(inst.bits), false)
        }
        _ => (rs1_value, rs2_value, inst.rs1.is_zero()),
    };
    let (vl, vtype) =
        execute_vsetvl(avl, requested_vtype, inst.rd.is_zero(), rs1_is_zero, vlen, current_vl);
    VectorConfig { vtype, vl, vstart: 0 }
}