RISC-V emulator core implementation
NOTE: This project is currently under intensely development. The source code might be changed dramatically.
How to use
Create an Emulator
object, place a binary data in DRAM and set the program counter to
DRAM_BASE
. The binary data must contain no headers for now. The example is here:
use DRAM_BASE;
use Emulator;
See the example usage in rvemu/lib/rvemu-cli/src/main.rs.
Features
Now, supports the following features (will be added in the future):
- RV64G ISA
- RV64C ISA
- Privileged ISA
- Control and status registers (CSRs)
- Virtual memory system (Sv39)
- Devices
- UART: universal asynchronous receiver-transmitter
- CLINT: core local interruptor
- PLIC: platform level interrupt controller
- Virtio