Crate rvemu 

RISC-V emulator core implementation.

How to use

Create an Emulator object, place a binary data in DRAM and set the program counter to DRAM_BASE. The binary data must contain no headers for now. The example is here:

use rvemu::bus::DRAM_BASE;
use rvemu::emulator::Emulator;

fn main() {
    // Create a dummy binary data.
    let data = vec![
        0x93, 0x0f, 0xa0, 0x02, // addi x31, x0, 42
    ];

    // Create an emulator object.
    let mut emu = Emulator::new();
    // Place the binary data in the beginning of DRAM.
    emu.initialize_dram(data);
    // Set the program counter to 0x8000_0000, which is the address DRAM starts.
    emu.initialize_pc(DRAM_BASE);
    // Start the emulator.
    emu.start();

    // `IllegalInstruction` is raised for now because of the termination condition of the emulator,
    // but the register is successfully updated.
    assert_eq!(42, emu.cpu.xregs.read(31));
}

See the example usage in rvemu/lib/rvemu-cli/src/main.rs.

Modules

bus

The bus module contains the system bus which can access the memroy or memory-mapped peripheral devices.

cpu

The cpu module contains the privileged mode, registers, and CPU.

csr

The csr module contains all the control and status registers.

devices

The devices module contains peripheral devices.

dram

The memory module contains the memory structure and implementation to read/write the memory.

emulator

The emulator module represents an entire computer.

exception

The exception module contains all the exception kinds and the function to handle exceptions.

interrupt

The interrupt module contains all the interrupt kinds and the function to handle interrupts.

rom

The rom module contains the read-only memory structure and implementation to read the memory. ROM includes a device tree blob (DTB) compiled from a device tree source (DTS).