Rivet RTOS — ARM Cortex-M ISA port.

Implements the Group A (rivet::port::arch) symbol contract for Cortex-M targets: PendSV context switch, MemManage fault handling, MPU programming, SysTick tick source. Contains no board/MMIO knowledge beyond what's genuinely part of the Cortex-M architecture (SCB, MPU, SysTick, and their fixed System Control Space addresses — identical on every Cortex-M3/4/7/33). A board's clock rate, console, and exit/reset path are supplied separately by a rivet-bsp-* crate.

Preemptive context switch

Tasks run in Thread mode using PSP (Process Stack Pointer); exceptions (SysTick, PendSV, everything else) always run in Handler mode using MSP (Main Stack Pointer) — automatic Cortex-M behavior. That split matters: a PendSV handler's own nested Rust calls (the scheduler, atomics, etc.) run on MSP, never touching a task's PSP-based stack — no RISC-V-style risk of the scheduler's own call chain competing for space with whatever a task had reserved for itself.

Following ARM's recommended pattern: SysTick only requests a reschedule (SCB.ICSR.PENDSVSET); the actual register save/restore and scheduling decision happen in PendSV, which — being the lowest-priority exception — never preempts a higher-priority ISR mid-flight.