Crate rivet_arch_cortex_m 

Rivet RTOS — ARM Cortex-M ISA port.

Implements the Group A (rivet::port::arch) symbol contract for Cortex-M targets: PendSV context switch, MemManage fault handling, MPU programming, SysTick tick source. Contains no board/MMIO knowledge beyond what’s genuinely part of the Cortex-M architecture (SCB, MPU, SysTick, and their fixed System Control Space addresses — identical on every Cortex-M3/4/7/33). A board’s clock rate, console, and exit/reset path are supplied separately by a rivet-bsp-* crate.

Preemptive context switch

Tasks run in Thread mode using PSP (Process Stack Pointer); exceptions (SysTick, PendSV, everything else) always run in Handler mode using MSP (Main Stack Pointer) — automatic Cortex-M behavior. That split matters: a PendSV handler’s own nested Rust calls (the scheduler, atomics, etc.) run on MSP, never touching a task’s PSP-based stack — no RISC-V-style risk of the scheduler’s own call chain competing for space with whatever a task had reserved for itself.

Following ARM’s recommended pattern: SysTick only requests a reschedule (SCB.ICSR.PENDSVSET); the actual register save/restore and scheduling decision happen in PendSV, which — being the lowest-priority exception — never preempts a higher-priority ISR mid-flight.

Modules

dwt

DWT CYCCNT-based cycle counter (plan.md Phase 10).

mpu

Memory Protection Unit: two-region stack isolation.

semihosting

ARM semihosting debug I/O. Architectural (the bkpt 0xAB sequence is recognized by any semihosting-aware debug host, not tied to any particular board’s memory map) — a utility a BSP may use for its console/exit implementation instead of a real UART.

Constants

MIN_TASK_STACK

Minimum task stack: the PendSV frame (32 bytes r4-r11 + 32 bytes hardware-stacked r0-r3/r12/lr/pc/xPSR) plus slack for the entry trampoline.

Functions

system_reset

Cortex-M system reset via SCB AIRCR SYSRESETREQ. A utility for BSPs’ __rivet_board_reset implementation — architecturally universal, not board-specific.