riscv 0.16.1

//! sstatus register

pub use super::misa::XLEN;
pub use super::mstatus::{FS, VS, XS};

#[cfg(target_arch = "riscv32")]
const MASK: usize = 0x800d_e762;
#[cfg(not(target_arch = "riscv32"))]
const MASK: usize = 0x8000_0003_000d_e762;

read_write_csr! {
    /// Supervisor Status Register
    Sstatus: 0x100,
    mask: MASK,
}

csr_field_enum! {
    /// Supervisor Previous Privilege Mode
    SPP {
        default: User,
        /// Previous privilege mode is User mode.
        User = 0,
        /// Previous privilege mode is Supervisor mode.
        Supervisor = 1,
    }
}

read_write_csr_field! {
    Sstatus,
    /// Supervisor Interrupt Enable
    sie: 1,
}

read_write_csr_field! {
    Sstatus,
    /// Supervisor Previous Interrupt Enable
    spie: 5,
}

read_write_csr_field! {
    Sstatus,
    /// U-mode non-instruction-fetch memory endianness
    ube: 6,
}

read_write_csr_field! {
    Sstatus,
    /// Supervisor Previous Privilege Mode
    spp,
    SPP: [8:8],
}

read_write_csr_field! {
    Sstatus,
    /// Vector extension state
    vs,
    VS: [9:10],
}

read_write_csr_field! {
    Sstatus,
    /// The status of the floating-point unit
    fs,
    FS: [13:14],
}

read_only_csr_field! {
    Sstatus,
    /// The status of additional user-mode extensions
    /// and associated state
    xs,
    XS: [15:16],
}

read_write_csr_field! {
    Sstatus,
    /// Permit Supervisor User Memory access
    sum: 18,
}

read_write_csr_field! {
    Sstatus,
    /// Make eXecutable Readable
    mxr: 19,
}

#[cfg(not(target_arch = "riscv32"))]
read_write_csr_field! {
    Sstatus,
    /// Effective xlen in U-mode (i.e., `UXLEN`).
    uxl,
    XLEN: [32:33],
}

#[cfg(target_arch = "riscv32")]
read_only_csr_field! {
    Sstatus,
    /// Whether either the FS field or XS field signals the presence of some dirty state.
    ///
    /// This is a read-only bit computed by hardware as `(FS == Dirty) || (XS == Dirty) || (VS == Dirty)`.
    sd: 31,
}

#[cfg(not(target_arch = "riscv32"))]
read_only_csr_field! {
    Sstatus,
    /// Whether either the FS field or XS field signals the presence of some dirty state.
    ///
    /// This is a read-only bit computed by hardware as `(FS == Dirty) || (XS == Dirty) || (VS == Dirty)`.
    sd: 63,
}

impl Sstatus {
    /// Effective xlen in U-mode (i.e., `UXLEN`).
    ///
    /// In RISCV-32, UXL does not exist, and `UXLEN` is always [`XLEN::XLEN32`].
    #[inline]
    #[cfg(target_arch = "riscv32")]
    pub fn uxl(&self) -> XLEN {
        XLEN::XLEN32
    }
}

set!(0x100);
clear!(0x100);

set_clear_csr!(
    /// User Interrupt Enable.
    ///
    /// This helper is kept for API compatibility with legacy code that still
    /// targets the deprecated N-extension encoding. On systems that do not
    /// implement these bits, writes may be ignored by hardware.
    , set_uie, clear_uie, 1 << 0);
set_clear_csr!(
    /// Supervisor Interrupt Enable
    , set_sie, clear_sie, 1 << 1);
set_csr!(
    /// User Previous Interrupt Enable.
    ///
    /// This helper is kept for API compatibility with legacy code that still
    /// targets the deprecated N-extension encoding. On systems that do not
    /// implement these bits, writes may be ignored by hardware.
    , set_upie, 1 << 4);
set_csr!(
    /// Supervisor Previous Interrupt Enable
    , set_spie, 1 << 5);
set_clear_csr!(
    /// U-mode non-instruction-fetch memory endianness
    , set_ube, clear_ube, 1 << 6);
set_clear_csr!(
    /// Permit Supervisor User Memory access
    , set_sum, clear_sum, 1 << 18);
set_clear_csr!(
    /// Make eXecutable Readable
    , set_mxr, clear_mxr, 1 << 19);

/// Supervisor Previous Privilege Mode
#[inline]
pub unsafe fn set_spp(spp: SPP) {
    match spp {
        SPP::Supervisor => _set(1 << 8),
        SPP::User => _clear(1 << 8),
    }
}

/// The status of the floating-point unit
#[inline]
pub unsafe fn set_fs(fs: FS) {
    let mut value = _read();
    value &= !(0x3 << 13); // clear previous value
    value |= (fs as usize) << 13;
    _write(value);
}

/// Vector extension state
#[inline]
pub unsafe fn set_vs(vs: VS) {
    let mut value = _read();
    value &= !(0x3 << 9); // clear previous value
    value |= (vs as usize) << 9;
    _write(value);
}

/// Effective xlen in U-mode (i.e., `UXLEN`)
///
/// # Note
///
/// In RISCV-32, `UXL` does not exist.
#[inline]
#[cfg(not(target_arch = "riscv32"))]
pub unsafe fn set_uxl(uxl: XLEN) {
    let mut value = _read();
    value &= !(0x3 << 32); // clear previous value
    value |= (uxl as usize) << 32;
    _write(value);
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_sstatus() {
        let mut sstatus = Sstatus::from_bits(0);

        test_csr_field!(sstatus, sie);
        test_csr_field!(sstatus, spie);
        test_csr_field!(sstatus, ube);

        [SPP::User, SPP::Supervisor].into_iter().for_each(|spp| {
            test_csr_field!(sstatus, spp: spp);
        });

        [VS::Off, VS::Initial, VS::Clean, VS::Dirty]
            .into_iter()
            .for_each(|vs| {
                test_csr_field!(sstatus, vs: vs);
            });

        [FS::Off, FS::Initial, FS::Clean, FS::Dirty]
            .into_iter()
            .for_each(|fs| {
                test_csr_field!(sstatus, fs: fs);
            });

        [
            XS::AllOff,
            XS::NoneDirtyOrClean,
            XS::NoneDirtySomeClean,
            XS::SomeDirty,
        ]
        .into_iter()
        .for_each(|xs| {
            let sstatus = Sstatus::from_bits(xs.into_usize() << 15);
            assert_eq!(sstatus.xs(), xs);
            assert_eq!(sstatus.try_xs(), Ok(xs));
        });

        test_csr_field!(sstatus, sum);
        test_csr_field!(sstatus, mxr);

        [XLEN::XLEN32, XLEN::XLEN64, XLEN::XLEN128]
            .into_iter()
            .for_each(|xlen| {
                test_csr_field!(sstatus, uxl: xlen);
            });

        // SD is read-only: hardware sets it whenever FS, VS, or XS == Dirty.
        assert!(!Sstatus::from_bits(0).sd());
        assert!(Sstatus::from_bits(usize::MAX).sd());
    }
}