riscv-aia 0.0.0

Low level access to the RISC-V Advanced Interrupt Architecture (AIA)
Documentation 
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//! Machine virtual interrupt enables high-half (mvieh) (RV32 only)

riscv::read_write_csr! {
    /// Upper 32 bits of mvien (RV32 only).
    Mvieh: 0x318,
    mask: 0xFFFF_FFFF,
}

impl Mvieh {
    #[inline]
    pub const fn raw(self) -> usize {
        self.bits
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn mvieh_raw_roundtrip() {
        let bits: usize = 0xCAFEBABEu32 as usize;
        let reg = Mvieh::from_bits(bits);
        assert_eq!(reg.raw(), bits);
    }
}