riscv-aia 0.0.0

Low level access to the RISC-V Advanced Interrupt Architecture (AIA)
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

//! Hypervisor virtual interrupt enables high-half (hvienh) (RV32 only)

riscv::read_write_csr! {
    /// Upper 32 bits of hvien.
    Hvienh: 0x618,
    mask: 0xFFFF_FFFF,
}

impl Hvienh {
    #[inline]
    pub const fn raw(self) -> usize {
        self.bits
    }
}

#[cfg(test)]
mod tests {
    use super::*;
    use crate::register::hviph::Hviph;

    #[test]
    fn hvienh_hviph_raw_roundtrip() {
        let bits: usize = 0xDEAD_BEEFusize & 0xFFFF_FFFF;
        let en = Hvienh::from_bits(bits);
        let p = Hviph::from_bits(bits);
        assert_eq!(en.raw(), bits);
        assert_eq!(p.raw(), bits);
    }
}