qingke 0.7.0

Low level access to WCH's QingKe RISC-V processors
Documentation 
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//! corecfgr, core configuration register
use core::arch::asm;

#[inline]
pub fn read() -> usize {
    let ans: usize;
    unsafe { asm!("csrr {}, 0xBC0", out(reg) ans) };
    ans
}

/// Write to corecfgr
#[inline]
pub unsafe fn write(bits: usize) {
    unsafe { asm!("csrs 0xBC0, {}", in(reg) bits) };
}

/// Write 0x1f to ??? (in EVT code)
#[inline]
pub unsafe fn set_default() {
    unsafe { write(0x1f) };
}