PyTV

Python Templated Verilog

Package

The package pytv is available on crates.io. Documentation is available on docs.rs.

To use the package, run

cargo add pytv

Features

Python Template

This is the basic feature of this package.

//! a = 1 + 2;            #  Python inline
assign wire_`a` = wire_b; // Verilog with variable/expression substitute
/*!
b = a ** 2;               #  Python block
*/

The magic comment string can be configured (! as default).

Instantiation

The crate feature inst is enabled by default. YAML contents between <INST> and </INST> are used to provide instantiation information.

Related Auto Generator Projects

• FLAMES: template-based C++ library for Vitis HLS [website] [GitHub] [paper at IEEE] [paper PDF]
• AHDW: a DSL, the predecessor of this project [paper at IEEE] [paper PDF]

Author

Teddy van Jerry (Wuqiong Zhao)