Crate pytv

Python Templated Verilog

Generation Process

.pytv ----> .v.py --+-> .v
                    |
                    +-> .inst

Examples

//! a = 1 + 2;            #  Python inline
assign wire_`a` = wire_b; // Verilog with variable/expression substitute
/*!
b = a ** 2;               #  Python block
*/

The magic comment string can be configured (! as default).

Related Auto Generator Projects

• FLAMES: template-based C++ library for Vitis HLS [website] [GitHub] [paper at IEEE] [paper PDF]
• AHDW: a DSL, the predecessor of this project [paper at IEEE] [paper PDF]

Structs

Config

Represents the configuration options for PyTV.

Convert

Represents a converter that converts PyTV script to Python script to generate Verilog.

FileOptions

Represents the options for input and output file for PyTV.