open-vaf 0.4.2

A compiler frontend for VerilogA aimed predominently at compact modelling
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54

`include "disciplines.va"


/*
 * ******************************************************************************************
 * Copyright (c) 2019 Pascal Kuthe. This file is part of the OpenVAF project.
 * It is subject to the license terms in the LICENSE file found in the top-level directory
 *  of this distribution and at  https://gitlab.com/DSPOM/OpenVAF/blob/master/LICENSE.
 *  No part of OpenVAF, including this file, may be copied, modified, propagated, or
 *  distributed except according to the terms contained in the LICENSE file.
 * *****************************************************************************************
 */


`define branches\
    branch (A,x) ax;\
    branch (A,y) ay;\
    branch (x,B) xb;\
    branch (y,B) yb;\
    branch (x,y) xy;

`define calculate(a,b)\
    b**a/2;\
    C = C**2;


module schaltung (A,B);
    inout electrical A,B;
    electrical x,y;
    `branches
    real C = 30;

    analog begin
        if (V(ax) > 100) begin
            if (V(ax) > 100) begin
                C=42*31+1;
            end
                        if (V(ax) > 100) begin
                            C=42*31+1;
                        end else             if (V(ax) > 100) begin
                                                 C=42*31+1;
                                             end else begin
                                             end
        end
        I(xy) <+ (C*V(ax)+I(xy))/30;
        I(ax) <+ `calculate(31,V(ax))
        I(ay) <+ V(ay)/20;
        if (V(ax) > 100) begin
            C=42*31+1;
        end
        I(ax) <+ V(ax)/40;
        I(ay) <+ C*V(ay)/50;
    end
endmodule