open-vaf 0.4.2

A compiler frontend for VerilogA aimed predominently at compact modelling
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`include "constants.va"
`include "disciplines.va"


module Diode(inout electrical A,inout electrical C);
  branch (A,C) d;
  parameter real I_s0 = 1E-11 from [1E-20:1];
  parameter real m = 1 from [0.1:10];
  parameter real zeta = 1;
  parameter real T_0 = 300 from [0:inf];
  real V_t,I_s;
  integer i;
  (*extract*) real I_d;
  (*extract*) real I_d_ddx;
  analog begin
        I_s = I_s0*($temperature/T_0)**zeta;
        V_t = `P_K*$temperature/`P_Q;
        I_d = I_s;
        i = 0;
        while (i < 1000) begin
            I_d = I_d * exp( V(d) /(m*V_t) );
            if (i > 500) begin
                I_d = I_d + 2;
            end
            i = i+1;
        end
        I_d_ddx = ddx(I_d,V(A));
   end
endmodule