use embedded_hal::digital::OutputPin;
use embedded_hal_async::spi::SpiBus;
pub use super::cmd::cmd_wisun::*;
use super::{BusyPin, Lr2021, Lr2021Error, RxBw};
#[derive(Debug, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct WisunPacketParams {
pub tx_crc: WisunFcsLen,
pub whitening: bool,
pub crc_hw: bool,
pub mode_switch_tx: bool,
pub fec_tx: WisunFec,
pub frame_len_tx: u16,
pub pbl_len_tx: u8,
pub pbl_detect: u8
}
impl WisunPacketParams {
pub fn new_data(tx_len: u16, tx_fec: WisunFec, tx_crc: WisunFcsLen) -> Self {
Self {
tx_crc,
whitening: true,
crc_hw: true,
mode_switch_tx: false,
fec_tx: tx_fec,
frame_len_tx: tx_len,
pbl_len_tx: 32,
pbl_detect: 255,
}
}
pub fn with_pbl_len(self, pbl_len_tx: u8) -> Self {
Self {
pbl_len_tx,
..self
}
}
pub fn new_mode_switch() -> Self {
Self {
tx_crc: WisunFcsLen::Fcs16b,
whitening: true,
crc_hw: true,
mode_switch_tx: true,
fec_tx: WisunFec::None,
frame_len_tx: 0,
pbl_len_tx: 32,
pbl_detect: 255,
}
}
}
impl<O,SPI, M> Lr2021<O,SPI, M> where
O: OutputPin, SPI: SpiBus<u8>, M: BusyPin
{
pub async fn set_wisun_modulation(&mut self, mode: WisunMode, rx_bw: RxBw) -> Result<(), Lr2021Error> {
let req = set_wisun_mode_cmd(mode, rx_bw);
self.cmd_wr(&req).await
}
pub async fn set_wisun_packet(&mut self, params: WisunPacketParams) -> Result<(), Lr2021Error> {
let req = set_wisun_packet_params_cmd(params.tx_crc, params.whitening, params.crc_hw, params.mode_switch_tx, params.fec_tx, params.frame_len_tx, params.pbl_len_tx, params.pbl_detect);
self.cmd_wr(&req).await
}
pub async fn get_wisun_packet_status(&mut self) -> Result<WisunPacketStatusRsp, Lr2021Error> {
let req = get_wisun_packet_status_req();
let mut rsp = WisunPacketStatusRsp::new();
self.cmd_rd(&req, rsp.as_mut()).await?;
Ok(rsp)
}
pub async fn get_wisun_rx_stats(&mut self) -> Result<WisunRxStatsRsp, Lr2021Error> {
let req = get_wisun_rx_stats_req();
let mut rsp = WisunRxStatsRsp::new();
self.cmd_rd(&req, rsp.as_mut()).await?;
Ok(rsp)
}
}