Struct lpc845_pac::dma0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub ctrl: Reg<CTRL_SPEC>,
    pub intstat: Reg<INTSTAT_SPEC>,
    pub srambase: Reg<SRAMBASE_SPEC>,
    pub enableset0: Reg<ENABLESET0_SPEC>,
    pub enableclr0: Reg<ENABLECLR0_SPEC>,
    pub active0: Reg<ACTIVE0_SPEC>,
    pub busy0: Reg<BUSY0_SPEC>,
    pub errint0: Reg<ERRINT0_SPEC>,
    pub intenset0: Reg<INTENSET0_SPEC>,
    pub intenclr0: Reg<INTENCLR0_SPEC>,
    pub inta0: Reg<INTA0_SPEC>,
    pub intb0: Reg<INTB0_SPEC>,
    pub setvalid0: Reg<SETVALID0_SPEC>,
    pub settrig0: Reg<SETTRIG0_SPEC>,
    pub abort0: Reg<ABORT0_SPEC>,
    pub channel0: CHANNEL,
    pub channel1: CHANNEL,
    pub channel2: CHANNEL,
    pub channel3: CHANNEL,
    pub channel4: CHANNEL,
    pub channel5: CHANNEL,
    pub channel6: CHANNEL,
    pub channel7: CHANNEL,
    pub channel8: CHANNEL,
    pub channel9: CHANNEL,
    pub channel10: CHANNEL,
    pub channel11: CHANNEL,
    pub channel12: CHANNEL,
    pub channel13: CHANNEL,
    pub channel14: CHANNEL,
    pub channel15: CHANNEL,
    pub channel16: CHANNEL,
    pub channel17: CHANNEL,
    pub channel18: CHANNEL,
    pub channel19: CHANNEL,
    pub channel20: CHANNEL,
    pub channel21: CHANNEL,
    pub channel22: CHANNEL,
    pub channel23: CHANNEL,
    pub channel24: CHANNEL,
    // some fields omitted
}

Register block

Fields

ctrl: Reg<CTRL_SPEC>

0x00 - DMA control.

intstat: Reg<INTSTAT_SPEC>

0x04 - Interrupt status.

srambase: Reg<SRAMBASE_SPEC>

0x08 - SRAM address of the channel configuration table.

enableset0: Reg<ENABLESET0_SPEC>

0x20 - Channel Enable read and Set for all DMA channels.

enableclr0: Reg<ENABLECLR0_SPEC>

0x28 - Channel Enable Clear for all DMA channels.

active0: Reg<ACTIVE0_SPEC>

0x30 - Channel Active status for all DMA channels.

busy0: Reg<BUSY0_SPEC>

0x38 - Channel Busy status for all DMA channels.

errint0: Reg<ERRINT0_SPEC>

0x40 - Error Interrupt status for all DMA channels.

intenset0: Reg<INTENSET0_SPEC>

0x48 - Interrupt Enable read and Set for all DMA channels.

intenclr0: Reg<INTENCLR0_SPEC>

0x50 - Interrupt Enable Clear for all DMA channels.

inta0: Reg<INTA0_SPEC>

0x58 - Interrupt A status for all DMA channels.

intb0: Reg<INTB0_SPEC>

0x60 - Interrupt B status for all DMA channels.

setvalid0: Reg<SETVALID0_SPEC>

0x68 - Set ValidPending control bits for all DMA channels.

settrig0: Reg<SETTRIG0_SPEC>

0x70 - Set Trigger control bits for all DMA channels.

abort0: Reg<ABORT0_SPEC>

0x78 - Channel Abort control for all DMA channels.

channel0: CHANNEL

0x400..0x40c - no description available

channel1: CHANNEL

0x410..0x41c - no description available

channel2: CHANNEL

0x420..0x42c - no description available

channel3: CHANNEL

0x430..0x43c - no description available

channel4: CHANNEL

0x440..0x44c - no description available

channel5: CHANNEL

0x450..0x45c - no description available

channel6: CHANNEL

0x460..0x46c - no description available

channel7: CHANNEL

0x470..0x47c - no description available

channel8: CHANNEL

0x480..0x48c - no description available

channel9: CHANNEL

0x490..0x49c - no description available

channel10: CHANNEL

0x4a0..0x4ac - no description available

channel11: CHANNEL

0x4b0..0x4bc - no description available

channel12: CHANNEL

0x4c0..0x4cc - no description available

channel13: CHANNEL

0x4d0..0x4dc - no description available

channel14: CHANNEL

0x4e0..0x4ec - no description available

channel15: CHANNEL

0x4f0..0x4fc - no description available

channel16: CHANNEL

0x500..0x50c - no description available

channel17: CHANNEL

0x510..0x51c - no description available

channel18: CHANNEL

0x520..0x52c - no description available

channel19: CHANNEL

0x530..0x53c - no description available

channel20: CHANNEL

0x540..0x54c - no description available

channel21: CHANNEL

0x550..0x55c - no description available

channel22: CHANNEL

0x560..0x56c - no description available

channel23: CHANNEL

0x570..0x57c - no description available

channel24: CHANNEL

0x580..0x58c - no description available