Struct lpc55_pac::i2s0::fifotrig::RXLVL_R

pub struct RXLVL_R(_);

Field RXLVL reader - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full).

Methods from Deref<Target = FieldReader<u8, u8>>

pub fn bits(&self) -> U

Reads raw bits from field.

pub fn bit(&self) -> bool

Value of the field as raw bits.

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0).

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1).

Trait Implementations

impl Deref for RXLVL_R

type Target = FieldReader<u8, u8>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.