Crate lpc55_pac

Expand description

Peripheral access API for LPC55S69_CM33_CORE0 microcontrollers (generated using svd2rust v0.20.0 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

pub use self::Interrupt as interrupt;
pub use flash_cfpa0 as flash_cfpa_scratch;
pub use flash_cfpa0 as flash_cfpa1;
pub use gint0 as gint1;
pub use pint as secpint;
pub use ctimer0 as ctimer1;
pub use ctimer0 as ctimer2;
pub use ctimer0 as ctimer3;
pub use ctimer0 as ctimer4;
pub use dma0 as dma1;
pub use flexcomm0 as flexcomm1;
pub use flexcomm0 as flexcomm2;
pub use flexcomm0 as flexcomm3;
pub use flexcomm0 as flexcomm4;
pub use flexcomm0 as flexcomm5;
pub use flexcomm0 as flexcomm6;
pub use flexcomm0 as flexcomm7;
pub use flexcomm0 as flexcomm8;
pub use i2c0 as i2c1;
pub use i2c0 as i2c2;
pub use i2c0 as i2c3;
pub use i2c0 as i2c4;
pub use i2c0 as i2c5;
pub use i2c0 as i2c6;
pub use i2c0 as i2c7;
pub use i2s0 as i2s1;
pub use i2s0 as i2s2;
pub use i2s0 as i2s3;
pub use i2s0 as i2s4;
pub use i2s0 as i2s5;
pub use i2s0 as i2s6;
pub use i2s0 as i2s7;
pub use spi0 as spi1;
pub use spi0 as spi2;
pub use spi0 as spi3;
pub use spi0 as spi4;
pub use spi0 as spi5;
pub use spi0 as spi6;
pub use spi0 as spi7;
pub use spi0 as spi8;
pub use usart0 as usart1;
pub use usart0 as usart2;
pub use usart0 as usart3;
pub use usart0 as usart4;
pub use usart0 as usart5;
pub use usart0 as usart6;
pub use usart0 as usart7;
pub use usb1 as usb0;

Modules§

adc0: ADC
ahb_secure_ctrl: AHB secure controller
anactrl: ANALOGCTRL
casper: CASPER
crc_engine: CRC engine
ctimer0: Standard counter/timers (CTIMER0 to 4)
dbgmailbox: MCU Debugger Mailbox
dma0: DMA controller
flash: FLASH
flash_cfpa0: FLASH_CFPA
flash_cmpa: FLASH_CMPA
flash_key_store: FLASH_KEY_STORE
flexcomm0: Flexcomm serial communication
generic: Common register and bit access and modify traits
gint0: Group GPIO input interrupt (GINT0/1)
gpio: General Purpose I/O (GPIO)
hashcrypt: Hash-Crypt peripheral
i2c0: I2C-bus interfaces
i2s0: I2S interface
inputmux: Input multiplexing (INPUT MUX)
iocon: I/O pin configuration (IOCON)
mailbox: Mailbox
mrt0: Multi-Rate Timer (MRT)
ostimer: Synchronous OS/Event timer with Wakeup Timer
pint: Pin interrupt and pattern match (PINT)
plu: LPC80X Programmable Logic Unit (PLU)
pmc: PMC
powerquad: Digital Signal Co-Processing companion to a Cortex-M v8M CPU core
prince: PRINCE
puf: PUFCTRL
rng: RNG
rpu: NXP ROM patch unit. Undocumented by NXP, this peripheral is experimentally modeled following research by Oxide Computer Company: https://oxide.computer/blog/lpc55/.
rtc: Real-Time Clock (RTC)
sau: Security Attribution Unit
scn_scb: no description available
sct0: SCTimer/PWM (SCT)
sdif: SDMMC
secgpio: General Purpose I/O (GPIO)
spi0: Serial Peripheral Interfaces (SPI)
syscon: SYSCON
sysctl: system controller
usart0: USARTs
usb1: USB1 High-speed Device Controller
usbfsh: USB0 Full-speed Host controller
usbhsh: USB1 High-speed Host Controller
usbphy: Universal System Bus Physical Layer
utick0: Micro-tick Timer (UTICK)
wwdt: Windowed Watchdog Timer (WWDT)

Structs§

ADC0: ADC
AHB_SECURE_CTRL: AHB secure controller
ANACTRL: ANALOGCTRL
CASPER: CASPER
CBP: Cache and branch predictor maintenance operations
CPUID: CPUID
CRC_ENGINE: CRC engine
CTIMER0: Standard counter/timers (CTIMER0 to 4)
CTIMER1: Standard counter/timers (CTIMER0 to 4)
CTIMER2: Standard counter/timers (CTIMER0 to 4)
CTIMER3: Standard counter/timers (CTIMER0 to 4)
CTIMER4: Standard counter/timers (CTIMER0 to 4)
CorePeripherals: Core peripherals
DBGMAILBOX: MCU Debugger Mailbox
DCB: Debug Control Block
DMA0: DMA controller
DMA1: DMA controller
DWT: Data Watchpoint and Trace unit
FLASH: FLASH
FLASH_CFPA0: FLASH_CFPA
FLASH_CFPA1: FLASH_CFPA
FLASH_CFPA_SCRATCH: FLASH_CFPA
FLASH_CMPA: FLASH_CMPA
FLASH_KEY_STORE: FLASH_KEY_STORE
FLEXCOMM0: Flexcomm serial communication
FLEXCOMM1: Flexcomm serial communication
FLEXCOMM2: Flexcomm serial communication
FLEXCOMM3: Flexcomm serial communication
FLEXCOMM4: Flexcomm serial communication
FLEXCOMM5: Flexcomm serial communication
FLEXCOMM6: Flexcomm serial communication
FLEXCOMM7: Flexcomm serial communication
FLEXCOMM8: Flexcomm serial communication
FPB: Flash Patch and Breakpoint unit
FPU: Floating Point Unit
GINT0: Group GPIO input interrupt (GINT0/1)
GINT1: Group GPIO input interrupt (GINT0/1)
GPIO: General Purpose I/O (GPIO)
HASHCRYPT: Hash-Crypt peripheral
I2C0: I2C-bus interfaces
I2C1: I2C-bus interfaces
I2C2: I2C-bus interfaces
I2C3: I2C-bus interfaces
I2C4: I2C-bus interfaces
I2C5: I2C-bus interfaces
I2C6: I2C-bus interfaces
I2C7: I2C-bus interfaces
I2S0: I2S interface
I2S1: I2S interface
I2S2: I2S interface
I2S3: I2S interface
I2S4: I2S interface
I2S5: I2S interface
I2S6: I2S interface
I2S7: I2S interface
INPUTMUX: Input multiplexing (INPUT MUX)
IOCON: I/O pin configuration (IOCON)
ITM: Instrumentation Trace Macrocell
MAILBOX: Mailbox
MPU: Memory Protection Unit
MRT0: Multi-Rate Timer (MRT)
NVIC: Nested Vector Interrupt Controller
OSTIMER: Synchronous OS/Event timer with Wakeup Timer
PINT: Pin interrupt and pattern match (PINT)
PLU: LPC80X Programmable Logic Unit (PLU)
PMC: PMC
POWERQUAD: Digital Signal Co-Processing companion to a Cortex-M v8M CPU core
PRINCE: PRINCE
PUF: PUFCTRL
Peripherals: All the peripherals
RNG: RNG
RPU: NXP ROM patch unit. Undocumented by NXP, this peripheral is experimentally modeled following research by Oxide Computer Company: https://oxide.computer/blog/lpc55/.
RTC: Real-Time Clock (RTC)
SAU: Security Attribution Unit
SCB: System Control Block
SCNSCB: no description available
SCT0: SCTimer/PWM (SCT)
SDIF: SDMMC
SECGPIO: General Purpose I/O (GPIO)
SECPINT: Pin interrupt and pattern match (PINT)
SPI0: Serial Peripheral Interfaces (SPI)
SPI1: Serial Peripheral Interfaces (SPI)
SPI2: Serial Peripheral Interfaces (SPI)
SPI3: Serial Peripheral Interfaces (SPI)
SPI4: Serial Peripheral Interfaces (SPI)
SPI5: Serial Peripheral Interfaces (SPI)
SPI6: Serial Peripheral Interfaces (SPI)
SPI7: Serial Peripheral Interfaces (SPI)
SPI8: Serial Peripheral Interfaces (SPI)
SYSCON: SYSCON
SYSCTL: system controller
SYST: SysTick: System Timer
TPIU: Trace Port Interface Unit
USART0: USARTs
USART1: USARTs
USART2: USARTs
USART3: USARTs
USART4: USARTs
USART5: USARTs
USART6: USARTs
USART7: USARTs
USB0: USB1 High-speed Device Controller
USB1: USB1 High-speed Device Controller
USBFSH: USB0 Full-speed Host controller
USBHSH: USB1 High-speed Host Controller
USBPHY: Universal System Bus Physical Layer
UTICK0: Micro-tick Timer (UTICK)
WWDT: Windowed Watchdog Timer (WWDT)

Enums§

Interrupt: Enumeration of all the interrupts.

Constants§

NVIC_PRIO_BITS: Number available in the NVIC for configuring priority

Attribute Macros§

interrupt