pub struct R(_);
Expand description
Register CFG
reader
Implementations
sourceimpl R
impl R
sourcepub fn periphreqen(&self) -> PERIPHREQEN_R
pub fn periphreqen(&self) -> PERIPHREQEN_R
Bit 0 - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
sourcepub fn hwtrigen(&self) -> HWTRIGEN_R
pub fn hwtrigen(&self) -> HWTRIGEN_R
Bit 1 - Hardware Triggering Enable for this channel.
sourcepub fn trigpol(&self) -> TRIGPOL_R
pub fn trigpol(&self) -> TRIGPOL_R
Bit 4 - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
sourcepub fn trigtype(&self) -> TRIGTYPE_R
pub fn trigtype(&self) -> TRIGTYPE_R
Bit 5 - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
sourcepub fn trigburst(&self) -> TRIGBURST_R
pub fn trigburst(&self) -> TRIGBURST_R
Bit 6 - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
sourcepub fn burstpower(&self) -> BURSTPOWER_R
pub fn burstpower(&self) -> BURSTPOWER_R
Bits 8:11 - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
sourcepub fn srcburstwrap(&self) -> SRCBURSTWRAP_R
pub fn srcburstwrap(&self) -> SRCBURSTWRAP_R
Bit 14 - Source Burst Wrap. When enabled, the source data address for the DMA is ‘wrapped’, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
sourcepub fn dstburstwrap(&self) -> DSTBURSTWRAP_R
pub fn dstburstwrap(&self) -> DSTBURSTWRAP_R
Bit 15 - Destination Burst Wrap. When enabled, the destination data address for the DMA is ‘wrapped’, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
sourcepub fn chpriority(&self) -> CHPRIORITY_R
pub fn chpriority(&self) -> CHPRIORITY_R
Bits 16:18 - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
Methods from Deref<Target = R<CFG_SPEC>>
Trait Implementations
Auto Trait Implementations
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more