[][src]Type Definition lpc54606_pac::syscon::spificlkdiv::R

type R = R<u32, SPIFICLKDIV>;

Reader of register SPIFICLKDIV

Methods

impl R[src]

pub fn div(&self) -> DIV_R[src]

Bits 0:7 - Clock divider value.

pub fn reset(&self) -> RESET_R[src]

Bit 29 - Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count.

pub fn halt(&self) -> HALT_R[src]

Bit 30 - Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output.

pub fn reqflag(&self) -> REQFLAG_R[src]

Bit 31 - Divider status flag.