#[doc = "Register `TCR` reader"]
pub struct R(crate::R<TCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TCR` writer"]
pub struct W(crate::W<TCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CEN` reader - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
pub type CEN_R = crate::BitReader<bool>;
#[doc = "Field `CEN` writer - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, TCR_SPEC, bool, O>;
#[doc = "Field `CRES` reader - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
pub type CRES_R = crate::BitReader<bool>;
#[doc = "Field `CRES` writer - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
pub type CRES_W<'a, const O: u8> = crate::BitWriter<'a, u32, TCR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
#[inline(always)]
pub fn cen(&self) -> CEN_R {
CEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
#[inline(always)]
pub fn cres(&self) -> CRES_R {
CRES_R::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
#[inline(always)]
pub fn cen(&mut self) -> CEN_W<0> {
CEN_W::new(self)
}
#[doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
#[inline(always)]
pub fn cres(&mut self) -> CRES_W<1> {
CRES_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tcr](index.html) module"]
pub struct TCR_SPEC;
impl crate::RegisterSpec for TCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [tcr::R](R) reader structure"]
impl crate::Readable for TCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [tcr::W](W) writer structure"]
impl crate::Writable for TCR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets TCR to value 0"]
impl crate::Resettable for TCR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}