#[doc = "Register `CTCR` reader"]
pub struct R(crate::R<CTCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTCR` writer"]
pub struct W(crate::W<CTCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CTM` reader - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"]
pub type CTM_R = crate::FieldReader<u8, CTM_A>;
#[doc = "Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum CTM_A {
#[doc = "0: Timer Mode: every rising PCLK edge"]
TIMER_MODE_EVERY_RI = 0,
#[doc = "1: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2."]
RISING = 1,
#[doc = "2: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2."]
FALLLING = 2,
#[doc = "3: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2."]
BOTHEDGES = 3,
}
impl From<CTM_A> for u8 {
#[inline(always)]
fn from(variant: CTM_A) -> Self {
variant as _
}
}
impl CTM_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> CTM_A {
match self.bits {
0 => CTM_A::TIMER_MODE_EVERY_RI,
1 => CTM_A::RISING,
2 => CTM_A::FALLLING,
3 => CTM_A::BOTHEDGES,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `TIMER_MODE_EVERY_RI`"]
#[inline(always)]
pub fn is_timer_mode_every_ri(&self) -> bool {
*self == CTM_A::TIMER_MODE_EVERY_RI
}
#[doc = "Checks if the value of the field is `RISING`"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == CTM_A::RISING
}
#[doc = "Checks if the value of the field is `FALLLING`"]
#[inline(always)]
pub fn is_fallling(&self) -> bool {
*self == CTM_A::FALLLING
}
#[doc = "Checks if the value of the field is `BOTHEDGES`"]
#[inline(always)]
pub fn is_bothedges(&self) -> bool {
*self == CTM_A::BOTHEDGES
}
}
#[doc = "Field `CTM` writer - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"]
pub type CTM_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CTCR_SPEC, u8, CTM_A, 2, O>;
impl<'a, const O: u8> CTM_W<'a, O> {
#[doc = "Timer Mode: every rising PCLK edge"]
#[inline(always)]
pub fn timer_mode_every_ri(self) -> &'a mut W {
self.variant(CTM_A::TIMER_MODE_EVERY_RI)
}
#[doc = "Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2."]
#[inline(always)]
pub fn rising(self) -> &'a mut W {
self.variant(CTM_A::RISING)
}
#[doc = "Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2."]
#[inline(always)]
pub fn fallling(self) -> &'a mut W {
self.variant(CTM_A::FALLLING)
}
#[doc = "Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2."]
#[inline(always)]
pub fn bothedges(self) -> &'a mut W {
self.variant(CTM_A::BOTHEDGES)
}
}
#[doc = "Field `CIS` reader - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"]
pub type CIS_R = crate::FieldReader<u8, CIS_A>;
#[doc = "Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum CIS_A {
#[doc = "0: CT32Bn_CAP0"]
CT32BN_CAP0 = 0,
}
impl From<CIS_A> for u8 {
#[inline(always)]
fn from(variant: CIS_A) -> Self {
variant as _
}
}
impl CIS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> Option<CIS_A> {
match self.bits {
0 => Some(CIS_A::CT32BN_CAP0),
_ => None,
}
}
#[doc = "Checks if the value of the field is `CT32BN_CAP0`"]
#[inline(always)]
pub fn is_ct32bn_cap0(&self) -> bool {
*self == CIS_A::CT32BN_CAP0
}
}
#[doc = "Field `CIS` writer - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"]
pub type CIS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTCR_SPEC, u8, CIS_A, 2, O>;
impl<'a, const O: u8> CIS_W<'a, O> {
#[doc = "CT32Bn_CAP0"]
#[inline(always)]
pub fn ct32bn_cap0(self) -> &'a mut W {
self.variant(CIS_A::CT32BN_CAP0)
}
}
impl R {
#[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"]
#[inline(always)]
pub fn ctm(&self) -> CTM_R {
CTM_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"]
#[inline(always)]
pub fn cis(&self) -> CIS_R {
CIS_R::new(((self.bits >> 2) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"]
#[inline(always)]
pub fn ctm(&mut self) -> CTM_W<0> {
CTM_W::new(self)
}
#[doc = "Bits 2:3 - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"]
#[inline(always)]
pub fn cis(&mut self) -> CIS_W<2> {
CIS_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctcr](index.html) module"]
pub struct CTCR_SPEC;
impl crate::RegisterSpec for CTCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctcr::R](R) reader structure"]
impl crate::Readable for CTCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctcr::W](W) writer structure"]
impl crate::Writable for CTCR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CTCR to value 0"]
impl crate::Resettable for CTCR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}