Lockstitch
Lockstitch is an incremental, stateful cryptographic primitive for symmetric-key cryptographic operations (e.g. hashing, encryption, message authentication codes, and authenticated encryption) in complex protocols. Inspired by TupleHash, STROBE, Noise Protocol's stateful objects, and Xoodyak's Cyclist mode, Lockstitch combines BLAKE3 and AEGIS128L to provide GiB/sec performance on modern processors at a 128-bit security level.
⚠️ WARNING: You should not use this. ⚠️
Neither the design nor the implementation of this library have been independently evaluated.
Design
A Lockstitch protocol is a stateful object which has five different operations:
Mix: Mixes a piece of data into the protocol's state, making all future outputs dependent on it.Derive: Outputs bytes of pseudo-random data dependent on the protocol's prior state.Encrypt/Decrypt: Encrypts and decrypts data using the protocol's state as the key.Seal/Open: Similar toEncrypt/Decryptbut uses a MAC to ensure authenticity.Ratchet: Irreversibly modifies the protocol's state, preventing rollback.
Using these operations, one can construct a wide variety of symmetric-key constructions.
Use
Lockstitch is used to compose cryptographic protocols.
For example, we can create message digests:
assert_eq!;
assert_ne!;
We can create message authentication codes:
assert_eq!;
assert_ne!;
assert_ne!;
We can even create authenticated encryption:
let plaintext = b"a message".to_vec;
let ciphertext = aead_encrypt;
assert_eq!;
assert_eq!;
assert_eq!;
assert_eq!;
let mut bad_ciphertext = ciphertext.to_vec;
bad_ciphertext ^= 1; // flip one bit
assert_eq!;
Cargo Features
std: Enables features based on the Rust standard library. Enabled by default.hedge: Enables hedged random value generation withrand_core. Enabled by default.
Performance
Both BLAKE3 and AEGIS128L benefit significantly from the use of specific CPU instructions.
x86_64
On x86_64 CPUs, Lockstitch achieves its best performance with the aes and ssse3 CPU features
enabled and the std crate feature enabled. This allows the blake3 create to detect CPU features
at runtime, ensures AEGIS128L benefits from the AES-NI instructions, and prevents interference
between AES-NI and AVX2 in the AEGIS128L implementation.
To compile a x86_64 binary with support for these features, create a .cargo/config.toml file
with the following:
[]
= ["-C", "target-feature=+aes,+ssse3"]
Or use the following RUSTFLAGS environment variable:
aarch64
Lockstitch includes a NEON-optimized AEGIS128L implementation and the blake3 crate includes NEON
optimizations, so no Rust-specific settings are required.
Additional Information
For more information on the design of Lockstitch, see design.md.
For more information on performance, see perf.md.
License
Copyright © 2022 Coda Hale, Frank Denis
AEGIS128L implementation copied from rust-aegis with some modifications.
Distributed under the MIT License.