llvm-native-core 0.1.2

//! X86 Calling Conventions — complete implementation of all major X86 ABIs.
//!
//! Covers:
//! - System V AMD64 ABI (Linux, macOS, FreeBSD, Solaris)
//! - Microsoft x64 ABI (Windows)
//! - 32-bit cdecl, stdcall, fastcall, thiscall, vectorcall
//! - GCC/ICC extensions: regcall, preserve_all, preserve_most
//! - GHC (Glasgow Haskell Compiler) calling convention
//! - AnyReg (any register for return value)
//!
//! Classification follows the AMD64 ABI §3.2.3 algorithm for aggregate
//! types (structs, unions, arrays) with eightbyte-by-eightbyte analysis
//! and post-merger cleanup per the published specification.
//!
//! Clean-room reconstruction from:
//! - System V Application Binary Interface: AMD64 Architecture Processor
//!   Supplement (with LP64 and ILP32 programming models)
//! - Microsoft x64 Software Conventions
//! - Intel® 64 and IA-32 Architectures Software Developer's Manual
//! - cdecl/stdcall/fastcall/thiscall/vectorcall conventions
//!
//! Zero LLVM source code consultation.

use crate::types::{Type, TypeKind};
use crate::x86::x86_register_info::*;
use std::collections::HashMap;

// ============================================================================
// X86ArgClass — AMD64 ABI eightbyte classification categories
// ============================================================================

/// Classification category for each eightbyte of an argument type,
/// per System V AMD64 ABI §3.2.3.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum X86ArgClass {
    /// No class at all (zero-sized or empty).
    NoClass,
    /// Integer types: _Bool, char, short, int, long, long long, pointers,
    /// and enums. Fit in a general-purpose register.
    Integer,
    /// SSE types: float, double, _Decimal32, _Decimal64, __m64,
    /// and vectors of these. Fit in an XMM register.
    SSE,
    /// SSEUp: upper 8 bytes of a type that uses two eightbytes
    /// where the first is SSE. Goes in the next XMM register.
    SSEUp,
    /// X87: 80-bit extended precision (long double). Uses the x87 stack.
    X87,
    /// X87Up: upper 8 bytes of a complex type whose first eightbyte is X87.
    X87Up,
    /// ComplexX87: complex long double — split across x87 and memory.
    ComplexX87,
    /// Memory: passed on the stack (too large, or contains holes).
    Memory,
}

impl X86ArgClass {
    /// Returns true if this class indicates a register-passed eightbyte.
    pub fn is_register_class(&self) -> bool {
        matches!(
            self,
            X86ArgClass::Integer | X86ArgClass::SSE | X86ArgClass::SSEUp | X86ArgClass::X87
        )
    }

    /// Returns true if the class needs an XMM register.
    pub fn needs_xmm(&self) -> bool {
        matches!(self, X86ArgClass::SSE | X86ArgClass::SSEUp)
    }
}

// ============================================================================
// X86CallingConvention — the set of all supported X86 calling conventions
// ============================================================================

/// All X86 calling conventions supported by this backend.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum X86CallingConvention {
    /// C calling convention (cdecl) — default for C on 32-bit.
    /// All arguments on stack, caller cleans up.
    C,

    /// Fastcall — first 2 integer args in ECX, EDX; rest on stack (32-bit).
    /// On 64-bit Windows, fastcall is the default (first 4 in RCX,RDX,R8,R9).
    Fast,

    /// Stdcall — Windows 32-bit convention; callee cleans stack.
    StdCall,

    /// Thiscall — C++ member functions on 32-bit Windows; `this` in ECX.
    ThisCall,

    /// Vectorcall — up to 6 SIMD args in XMM0-XMM5; integers in registers.
    /// Used for SIMD-heavy functions.
    VectorCall,

    /// System V AMD64 ABI — standard on Linux, macOS, FreeBSD, Solaris.
    /// First 6 integer args in RDI,RSI,RDX,RCX,R8,R9; first 8 SSE in XMM0-XMM7.
    #[allow(non_camel_case_types)]
    X86_64_SysV,

    /// Microsoft x64 ABI — Windows 64-bit.
    /// First 4 in RCX,RDX,R8,R9 (or XMM0-XMM3 for floats); 32-byte shadow space.
    Win64,

    /// Regcall — ICC/GCC extension passing many args in registers.
    #[allow(non_camel_case_types)]
    X86_RegCall,

    /// PreserveAll — callee saves and restores all registers.
    PreserveAll,

    /// PreserveMost — callee saves most registers (used for runtime calls).
    PreserveMost,

    /// GHC — Glasgow Haskell Compiler calling convention.
    GHC,

    /// AnyReg — any register may be used for the return value.
    AnyReg,
}

impl Default for X86CallingConvention {
    fn default() -> Self {
        X86CallingConvention::X86_64_SysV
    }
}

impl X86CallingConvention {
    /// Create a calling convention from a `CallConv` (from frame lowering).
    pub fn new(cc: crate::x86::x86_frame_lowering::CallConv) -> Self {
        use crate::x86::x86_frame_lowering::CallConv;
        match cc {
            CallConv::SystemV => X86CallingConvention::X86_64_SysV,
            CallConv::Win64 => X86CallingConvention::Win64,
            CallConv::CDecl32 => X86CallingConvention::C,
            CallConv::StdCall32 => X86CallingConvention::StdCall,
            CallConv::FastCall32 => X86CallingConvention::Fast,
        }
    }

    /// Human-readable name of the calling convention.
    pub fn name(&self) -> &'static str {
        match self {
            X86CallingConvention::C => "cdecl",
            X86CallingConvention::Fast => "fastcall",
            X86CallingConvention::StdCall => "stdcall",
            X86CallingConvention::ThisCall => "thiscall",
            X86CallingConvention::VectorCall => "vectorcall",
            X86CallingConvention::X86_64_SysV => "System V AMD64",
            X86CallingConvention::Win64 => "Microsoft x64",
            X86CallingConvention::X86_RegCall => "regcall",
            X86CallingConvention::PreserveAll => "preserve_all",
            X86CallingConvention::PreserveMost => "preserve_most",
            X86CallingConvention::GHC => "GHC",
            X86CallingConvention::AnyReg => "anyreg",
        }
    }

    /// Whether this convention is a 64-bit convention.
    pub fn is_64bit(&self) -> bool {
        matches!(
            self,
            X86CallingConvention::X86_64_SysV
                | X86CallingConvention::Win64
                | X86CallingConvention::X86_RegCall
        )
    }

    /// Whether the callee cleans the stack (true) or caller (false).
    pub fn callee_cleans_stack(&self) -> bool {
        matches!(
            self,
            X86CallingConvention::StdCall
                | X86CallingConvention::ThisCall
                | X86CallingConvention::Fast
        )
    }

    /// Whether this convention uses register parameters at all.
    pub fn uses_register_params(&self) -> bool {
        match self {
            X86CallingConvention::C => false,
            X86CallingConvention::Fast => true,
            X86CallingConvention::StdCall => false,
            X86CallingConvention::ThisCall => true,
            X86CallingConvention::VectorCall => true,
            X86CallingConvention::X86_64_SysV => true,
            X86CallingConvention::Win64 => true,
            X86CallingConvention::X86_RegCall => true,
            X86CallingConvention::PreserveAll => false,
            X86CallingConvention::PreserveMost => false,
            X86CallingConvention::GHC => true,
            X86CallingConvention::AnyReg => true,
        }
    }

    /// Number of integer parameter registers available.
    pub fn get_num_int_param_regs(&self) -> usize {
        match self {
            X86CallingConvention::C | X86CallingConvention::StdCall => 0,
            X86CallingConvention::Fast => 2,
            X86CallingConvention::ThisCall => 1,
            X86CallingConvention::VectorCall => 2,
            X86CallingConvention::X86_64_SysV => 6,
            X86CallingConvention::Win64 => 4,
            X86CallingConvention::X86_RegCall => 5, // EAX,ECX,EDX,EDI,ESI
            X86CallingConvention::PreserveAll | X86CallingConvention::PreserveMost => 0,
            X86CallingConvention::GHC => 0,
            X86CallingConvention::AnyReg => 1,
        }
    }

    /// Number of SSE (XMM) parameter registers available.
    pub fn get_num_sse_param_regs(&self) -> usize {
        match self {
            X86CallingConvention::VectorCall => 6,
            X86CallingConvention::X86_64_SysV => 8,
            X86CallingConvention::Win64 => 4,
            _ => 0,
        }
    }

    /// Integer parameter registers (by register ID).
    pub fn get_int_param_regs(&self) -> Vec<u16> {
        match self {
            X86CallingConvention::Fast => vec![ECX, EDX],
            X86CallingConvention::ThisCall => vec![ECX],
            X86CallingConvention::X86_64_SysV => vec![RDI, RSI, RDX, RCX, R8, R9],
            X86CallingConvention::Win64 => vec![RCX, RDX, R8, R9],
            X86CallingConvention::X86_RegCall => vec![EAX, ECX, EDX, EDI, ESI],
            _ => vec![],
        }
    }

    /// SSE (XMM) parameter registers (by register ID).
    pub fn get_sse_param_regs(&self) -> Vec<u16> {
        match self {
            X86CallingConvention::VectorCall => vec![XMM0, XMM1, XMM2, XMM3, XMM4, XMM5],
            X86CallingConvention::X86_64_SysV => {
                vec![XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]
            }
            X86CallingConvention::Win64 => vec![XMM0, XMM1, XMM2, XMM3],
            _ => vec![],
        }
    }

    /// Stack alignment at the function call boundary.
    pub fn get_stack_alignment(&self) -> u32 {
        match self {
            X86CallingConvention::X86_64_SysV
            | X86CallingConvention::Win64
            | X86CallingConvention::X86_RegCall
            | X86CallingConvention::PreserveAll
            | X86CallingConvention::PreserveMost
            | X86CallingConvention::GHC
            | X86CallingConvention::AnyReg => 16,
            // 32-bit ABIs often use 16-byte alignment with SSE, but default to 4
            _ => 4,
        }
    }

    /// Shadow store size (for Win64, this is always 32 bytes).
    pub fn get_shadow_store_size(&self) -> i64 {
        match self {
            X86CallingConvention::Win64 => 32,
            _ => 0,
        }
    }

    /// Whether a struct-return type needs a hidden sret pointer (first arg).
    /// Per AMD64 ABI: aggregates > 16 bytes, or with MEMORY class, use sret.
    /// Win64: aggregates > 8 bytes use hidden pointer.
    pub fn needs_hidden_sret(&self, ty: &Type, type_map: &HashMap<TypeId, Type>) -> bool {
        if !ty.is_struct() {
            return false;
        }
        let size = type_size(ty, type_map);
        match self {
            X86CallingConvention::X86_64_SysV => {
                let classes = classify_aggregate_type(ty, type_map);
                // If MEMORY class appears, or size > 16 bytes (two eightbytes)
                size > 16 || classes.iter().any(|c| *c == X86ArgClass::Memory)
            }
            X86CallingConvention::Win64 => size > 8,
            _ => false,
        }
    }

    /// Determine which registers hold the return value for a given type.
    /// Returns a vector of register IDs.
    pub fn get_return_regs(&self, ty: &Type, type_map: &HashMap<TypeId, Type>) -> Vec<u16> {
        match self {
            X86CallingConvention::X86_64_SysV => {
                let classes = classify_arg_type(ty, 0, type_map);
                sysv_return_regs_from_classes(&classes)
            }
            X86CallingConvention::Win64 => {
                let size = type_size(ty, type_map);
                win64_return_regs(ty, size)
            }
            X86CallingConvention::C
            | X86CallingConvention::StdCall
            | X86CallingConvention::Fast
            | X86CallingConvention::ThisCall
            | X86CallingConvention::VectorCall => {
                // 32-bit: return in EAX (or EDX:EAX for i64), ST0 for x87 float
                cdecl_return_regs(ty, type_map)
            }
            _ => vec![RAX],
        }
    }

    /// Full argument assignment: classify each arg, assign registers/stack slots.
    /// Returns the per-argument info and the overall call frame layout.
    pub fn assign_args(
        &self,
        args: &[Type],
        type_map: &HashMap<TypeId, Type>,
    ) -> (Vec<X86ArgInfo>, X86CallFrame) {
        match self {
            X86CallingConvention::X86_64_SysV => assign_sysv_args(args, type_map),
            X86CallingConvention::Win64 => assign_win64_args(args, type_map),
            X86CallingConvention::C => assign_cdecl_args(args, type_map),
            X86CallingConvention::StdCall => assign_stdcall_args(args, type_map),
            X86CallingConvention::Fast => assign_fastcall_args(args, type_map),
            X86CallingConvention::ThisCall => assign_thiscall_args(args, type_map),
            X86CallingConvention::VectorCall => assign_vectorcall_args(args, type_map),
            _ => assign_stack_only_args(args, type_map),
        }
    }

    /// Classify a single argument type into a vector of X86ArgClass (one per
    /// eightbyte). Works only for the System V AMD64 classification.
    pub fn classify_arg(
        &self,
        ty: &Type,
        offset: i64,
        type_map: &HashMap<TypeId, Type>,
    ) -> Vec<X86ArgClass> {
        classify_arg_type(ty, offset, type_map)
    }
}

// Re-export TypeId for convenience since it's used in type_map parameters.
use crate::types::TypeId;

// ============================================================================
// X86ArgInfo — per-argument assignment information
// ============================================================================

/// Describes how a single function argument is passed.
#[derive(Debug, Clone)]
pub struct X86ArgInfo {
    /// True if this argument is passed in a register.
    pub in_reg: bool,

    /// Register IDs assigned to this argument (may be empty if all-stack).
    pub regs: Vec<u16>,

    /// Offset from RSP (or base pointer) where this argument lives on
    /// the stack. Negative for caller's frame, positive for callee's.
    pub stack_offset: i64,

    /// Size of the argument in bytes.
    pub size: u32,

    /// Alignment requirement of the argument.
    pub alignment: u32,

    /// True if passed by value on the stack (struct byval).
    pub is_byval: bool,

    /// True if this argument is the hidden struct-return pointer (sret).
    pub is_sret: bool,

    /// Padding bytes needed before this argument for alignment.
    pub padding: u32,
}

impl Default for X86ArgInfo {
    fn default() -> Self {
        X86ArgInfo {
            in_reg: false,
            regs: Vec::new(),
            stack_offset: 0,
            size: 0,
            alignment: 1,
            is_byval: false,
            is_sret: false,
            padding: 0,
        }
    }
}

// ============================================================================
// X86CallFrame — overall stack frame layout for a call
// ============================================================================

/// Describes the stack frame layout for a function call.
#[derive(Debug, Clone)]
pub struct X86CallFrame {
    /// Total stack space needed for arguments (not including shadow store
    /// or alignment padding beyond what's implicit).
    pub stack_size: i64,

    /// Stack offset for each argument (index in the same order as args).
    pub arg_offsets: Vec<i64>,

    /// Offset of the struct-return save area, if sret is used.
    pub return_save_area: Option<i64>,

    /// Shadow store size (Win64: 32 bytes for RCX,RDX,R8,R9 spill).
    pub shadow_store_size: i64,

    /// Extra padding added to achieve the required stack alignment.
    pub alignment_padding: i64,
}

impl Default for X86CallFrame {
    fn default() -> Self {
        X86CallFrame {
            stack_size: 0,
            arg_offsets: Vec::new(),
            return_save_area: None,
            shadow_store_size: 0,
            alignment_padding: 0,
        }
    }
}

// ============================================================================
// Type size and alignment helpers
// ============================================================================

/// Compute the size in bytes of an LLVM type.
/// For compound types, uses `type_map` to resolve TypeIds.
pub fn type_size(ty: &Type, type_map: &HashMap<TypeId, Type>) -> u64 {
    match &ty.kind {
        TypeKind::Void => 0,
        TypeKind::Half => 2,
        TypeKind::BFloat => 2,
        TypeKind::Float => 4,
        TypeKind::Double => 8,
        TypeKind::FP128 => 16,
        TypeKind::X86FP80 => 16, // Stored as 16 bytes (10 bytes used + 6 padding)
        TypeKind::PPCFP128 => 16,
        TypeKind::Label => 0,
        TypeKind::Metadata => 0,
        TypeKind::X86AMX => 0, // Variable-sized tile
        TypeKind::X86MMX => 8,
        TypeKind::Token => 0,
        TypeKind::Integer { bits } => ((*bits + 7) / 8) as u64,
        TypeKind::Pointer { .. } => 8, // Assume 64-bit pointers
        TypeKind::Array {
            len,
            element_type_id,
        } => {
            let elem_size = type_size_from_id(*element_type_id, type_map);
            (*len) * elem_size
        }
        TypeKind::Struct {
            is_packed,
            element_type_ids,
            ..
        } => {
            if element_type_ids.is_empty() {
                return 0;
            }
            let mut total = 0u64;
            let mut max_align = 1u64;
            for tid in element_type_ids {
                let elem = type_size_from_id(*tid, type_map);
                let align = type_alignment_from_id(*tid, type_map);
                if align > max_align {
                    max_align = align;
                }
                if !(*is_packed) {
                    // Align current offset to element alignment
                    total = align_to(total, align);
                }
                total += elem;
            }
            if !(*is_packed) && max_align > 0 {
                total = align_to(total, max_align);
            }
            total
        }
        TypeKind::FixedVector {
            len,
            element_type_id,
        } => {
            let elem_size = type_size_from_id(*element_type_id, type_map);
            (*len as u64) * elem_size
        }
        TypeKind::ScalableVector {
            min_elems,
            element_type_id,
        } => {
            let elem_size = type_size_from_id(*element_type_id, type_map);
            (*min_elems as u64) * elem_size
        }
        TypeKind::Function { .. } => 8, // Function pointer
    }
}

/// Compute the alignment of an LLVM type.
pub fn type_alignment(ty: &Type, type_map: &HashMap<TypeId, Type>) -> u64 {
    match &ty.kind {
        TypeKind::Void | TypeKind::Label | TypeKind::Metadata | TypeKind::Token => 1,
        TypeKind::Half | TypeKind::BFloat => 2,
        TypeKind::Float => 4,
        TypeKind::Double => 8,
        TypeKind::FP128 | TypeKind::PPCFP128 => 16,
        TypeKind::X86FP80 => 16,
        TypeKind::X86AMX => 64,
        TypeKind::X86MMX => 8,
        TypeKind::Integer { bits } => {
            let bytes = (*bits + 7) / 8;
            if bytes >= 16 {
                16
            } else if bytes >= 8 {
                8
            } else if bytes >= 4 {
                4
            } else if bytes >= 2 {
                2
            } else {
                1
            }
        }
        TypeKind::Pointer { .. } => 8,
        TypeKind::Array {
            element_type_id, ..
        } => type_alignment_from_id(*element_type_id, type_map),
        TypeKind::Struct {
            is_packed,
            element_type_ids,
            ..
        } => {
            if *is_packed {
                1
            } else {
                let mut max_align = 1u64;
                for tid in element_type_ids {
                    let a = type_alignment_from_id(*tid, type_map);
                    if a > max_align {
                        max_align = a;
                    }
                }
                max_align
            }
        }
        TypeKind::FixedVector {
            len,
            element_type_id,
        } => {
            let total = (*len as u64) * type_size_from_id(*element_type_id, type_map);
            vector_alignment(total)
        }
        TypeKind::ScalableVector {
            min_elems,
            element_type_id,
        } => {
            let total = (*min_elems as u64) * type_size_from_id(*element_type_id, type_map);
            vector_alignment(total)
        }
        TypeKind::Function { .. } => 8,
    }
}

/// Vector alignment rules: vectors align to their total size up to 64 bytes.
fn vector_alignment(total_bytes: u64) -> u64 {
    if total_bytes >= 64 {
        64
    } else if total_bytes >= 32 {
        32
    } else if total_bytes >= 16 {
        16
    } else if total_bytes >= 8 {
        8
    } else if total_bytes >= 4 {
        4
    } else if total_bytes >= 2 {
        2
    } else {
        1
    }
}

/// Resolve a TypeId to a Type via the type map. Panics if not found.
fn resolve_type(tid: TypeId, type_map: &HashMap<TypeId, Type>) -> Type {
    type_map
        .get(&tid)
        .cloned()
        .unwrap_or_else(|| panic!("TypeId {} not found in type map", tid.as_u64()))
}

/// Compute the size from a TypeId, using the map.
fn type_size_from_id(tid: TypeId, type_map: &HashMap<TypeId, Type>) -> u64 {
    let ty = resolve_type(tid, type_map);
    type_size(&ty, type_map)
}

/// Compute the alignment from a TypeId, using the map.
fn type_alignment_from_id(tid: TypeId, type_map: &HashMap<TypeId, Type>) -> u64 {
    let ty = resolve_type(tid, type_map);
    type_alignment(&ty, type_map)
}

/// Align `value` up to `alignment`.
fn align_to(value: u64, alignment: u64) -> u64 {
    if alignment == 0 {
        return value;
    }
    ((value + alignment - 1) / alignment) * alignment
}

/// Check if a type is a floating-point type that maps to SSE class.
#[allow(dead_code)]
fn is_sse_type(ty: &Type) -> bool {
    matches!(
        ty.kind,
        TypeKind::Float | TypeKind::Double | TypeKind::Half | TypeKind::BFloat
    )
}

/// Check if a type is an x87 type (80-bit extended precision).
#[allow(dead_code)]
fn is_x87_type(ty: &Type) -> bool {
    matches!(ty.kind, TypeKind::X86FP80)
}

/// Check if a type is an integer-like type (integers and pointers).
#[allow(dead_code)]
fn is_integer_like(ty: &Type) -> bool {
    matches!(ty.kind, TypeKind::Integer { .. } | TypeKind::Pointer { .. })
}

// ============================================================================
// System V AMD64 ABI Classification Algorithm (§3.2.3)
// ============================================================================

/// Classify a type by eightbytes for the System V AMD64 ABI.
///
/// The algorithm walks the type in 8-byte chunks ("eightbytes"), determining
/// the class of each chunk based on the fields that span it. After initial
/// classification, a post-merger cleanup pass enforces the ABI rules.
pub fn classify_arg_type(
    ty: &Type,
    offset: i64,
    type_map: &HashMap<TypeId, Type>,
) -> Vec<X86ArgClass> {
    let size = type_size(ty, type_map);

    match &ty.kind {
        // Primitives → classify directly
        TypeKind::Integer { bits } => {
            let bytes = (*bits + 7) / 8;
            let num_eightbytes = ((bytes as i64 + 7) / 8).max(1);
            let classes = vec![X86ArgClass::Integer; num_eightbytes as usize];
            classes
        }
        TypeKind::Pointer { .. } => {
            vec![X86ArgClass::Integer]
        }
        TypeKind::Half | TypeKind::BFloat | TypeKind::Float | TypeKind::Double => {
            vec![X86ArgClass::SSE]
        }
        TypeKind::FP128 | TypeKind::PPCFP128 => {
            // 128-bit floats: SSE + SSEUp
            vec![X86ArgClass::SSE, X86ArgClass::SSEUp]
        }
        TypeKind::X86FP80 => {
            // 80-bit extended precision → X87 class
            if offset % 16 == 0 {
                vec![X86ArgClass::X87]
            } else {
                vec![X86ArgClass::Memory]
            }
        }
        TypeKind::X86MMX => {
            vec![X86ArgClass::SSE]
        }
        TypeKind::Void
        | TypeKind::Label
        | TypeKind::Metadata
        | TypeKind::Token
        | TypeKind::X86AMX => {
            vec![]
        }
        // Compound types → use the full aggregate classification
        TypeKind::Array { .. }
        | TypeKind::Struct { .. }
        | TypeKind::FixedVector { .. }
        | TypeKind::ScalableVector { .. }
        | TypeKind::Function { .. } => {
            let mut classes = Vec::new();
            classify_aggregate_impl(ty, 0, offset, type_map, &mut classes);
            post_merger_cleanup(&mut classes, size);
            classes
        }
    }
}

/// Classify an aggregate type (struct, array, vector) using the full
/// eightbyte-by-eightbyte algorithm from AMD64 ABI §3.2.3.
pub fn classify_aggregate_type(ty: &Type, type_map: &HashMap<TypeId, Type>) -> Vec<X86ArgClass> {
    let size = type_size(ty, type_map);
    let mut classes = Vec::new();
    classify_aggregate_impl(ty, 0, 0, type_map, &mut classes);
    post_merger_cleanup(&mut classes, size);
    classes
}

/// Recursive implementation of the eightbyte classification algorithm.
///
/// Each field of the aggregate is classified into the eightbyte(s) it occupies.
/// The `start_offset` is relative to the aggregate start; `base_offset` is
/// the absolute offset from the beginning of the argument list.
fn classify_aggregate_impl(
    ty: &Type,
    start_offset: i64,
    base_offset: i64,
    type_map: &HashMap<TypeId, Type>,
    classes: &mut Vec<X86ArgClass>,
) {
    // Determine how many eightbytes we need
    let size = type_size(ty, type_map) as i64;
    let num_eightbytes = ((size + 7) / 8).max(1) as usize;

    // Ensure classes vector is large enough
    while classes.len() < num_eightbytes {
        classes.push(X86ArgClass::NoClass);
    }

    match &ty.kind {
        TypeKind::Struct {
            is_packed,
            element_type_ids,
            ..
        } => {
            let mut field_offset = 0i64;
            for tid in element_type_ids {
                let field_ty = resolve_type(*tid, type_map);
                let field_size = type_size(&field_ty, type_map) as i64;
                let field_align = type_alignment(&field_ty, type_map) as i64;

                if !(*is_packed) && field_align > 1 {
                    field_offset = align_to_i64(field_offset, field_align);
                }

                let abs_offset = base_offset + start_offset + field_offset;
                // Recursively classify this field
                classify_field_in_eightbytes(
                    &field_ty,
                    field_offset,
                    abs_offset,
                    type_map,
                    classes,
                );

                field_offset += field_size;
            }
        }
        TypeKind::Array {
            len,
            element_type_id,
        } => {
            let elem_ty = resolve_type(*element_type_id, type_map);
            let elem_size = type_size(&elem_ty, type_map) as i64;
            for i in 0..(*len as i64) {
                let field_offset = i * elem_size;
                let abs_offset = base_offset + start_offset + field_offset;
                classify_field_in_eightbytes(&elem_ty, field_offset, abs_offset, type_map, classes);
            }
        }
        TypeKind::FixedVector {
            len,
            element_type_id,
        } => {
            let elem_ty = resolve_type(*element_type_id, type_map);
            let elem_size = type_size(&elem_ty, type_map) as i64;
            // Vectors: each element classified independently within the eightbytes
            for i in 0..(*len as i64) {
                let field_offset = i * elem_size;
                let abs_offset = base_offset + start_offset + field_offset;
                let elem_classes = classify_arg_type(&elem_ty, abs_offset, type_map);
                merge_classes_into(classes, &elem_classes, start_offset + field_offset);
            }
        }
        TypeKind::ScalableVector { .. } => {
            // Scalable vectors always go to memory
            for c in classes.iter_mut() {
                *c = X86ArgClass::Memory;
            }
        }
        _ => {
            // Single non-aggregate type: classify it
            let sub_classes = classify_arg_type(ty, base_offset + start_offset, type_map);
            for (i, cls) in sub_classes.iter().enumerate() {
                let idx = i + (start_offset as usize / 8);
                if idx < classes.len() {
                    classes[idx] = merge_classes(classes[idx], *cls);
                }
            }
        }
    }
}

/// Classify a field that falls within certain eightbytes.
fn classify_field_in_eightbytes(
    field_ty: &Type,
    field_offset: i64, // Offset within the parent aggregate
    abs_offset: i64,   // Absolute offset from arg list start
    type_map: &HashMap<TypeId, Type>,
    classes: &mut Vec<X86ArgClass>,
) {
    let _field_size = type_size(field_ty, type_map) as i64;
    let field_classes = classify_arg_type(field_ty, abs_offset, type_map);
    merge_classes_into(classes, &field_classes, field_offset);
}

/// Merge a list of classes into the `classes` buffer at the given offset.
fn merge_classes_into(
    classes: &mut Vec<X86ArgClass>,
    field_classes: &[X86ArgClass],
    field_offset: i64,
) {
    let start_eightbyte = (field_offset / 8) as usize;
    for (i, cls) in field_classes.iter().enumerate() {
        let idx = start_eightbyte + i;
        if idx < classes.len() {
            classes[idx] = merge_classes(classes[idx], *cls);
        }
    }
}

/// Merge two classes per the AMD64 ABI rules.
/// The more "severe" class takes precedence.
fn merge_classes(a: X86ArgClass, b: X86ArgClass) -> X86ArgClass {
    use X86ArgClass::*;
    match (a, b) {
        // If either is Memory, the result is Memory
        (Memory, _) | (_, Memory) => Memory,
        // If either is NoClass, use the other
        (NoClass, other) | (other, NoClass) => other,
        // Integer + Integer = Integer
        (Integer, Integer) => Integer,
        // SSE + SSE = SSE; SSE + SSEUp = SSE; SSEUp + SSEUp = SSE
        (SSE, SSE) | (SSE, SSEUp) | (SSEUp, SSE) | (SSEUp, SSEUp) => SSE,
        // Integer + SSE = SSE (SSE wins when mixed)
        (Integer, SSE) | (SSE, Integer) => SSE,
        // SSEUp + Integer = SSE
        (SSEUp, Integer) | (Integer, SSEUp) => SSE,
        // X87 combinations
        (X87, X87) => X87,
        (X87, X87Up) | (X87Up, X87) => X87,
        (X87, Integer) | (Integer, X87) => Memory,
        (X87, SSE) | (SSE, X87) => Memory,
        (X87Up, X87Up) => X87Up,
        (X87Up, Integer) | (Integer, X87Up) => Memory,
        (X87Up, SSE) | (SSE, X87Up) => Memory,
        // SSEUp + X87 family -> Memory (mixed)
        (SSEUp, X87) | (X87, SSEUp) => Memory,
        (SSEUp, X87Up) | (X87Up, SSEUp) => Memory,
        // X87 + SSEUp already covered above
        // ComplexX87 pairs
        (ComplexX87, _) | (_, ComplexX87) => ComplexX87,
    }
}

/// Post-merger cleanup per AMD64 ABI §3.2.3 paragraph 5.
///
/// (a) If the size of the aggregate exceeds two eightbytes and the first
///     eightbyte is not SSE or any other eightbyte is not SSEUp, the whole
///     thing is passed in memory.
/// (b) If the size is exactly two eightbytes, enforce SSE + SSEUp pattern:
///     SSEUp only valid as the second eightbyte after SSE in the first.
fn post_merger_cleanup(classes: &mut Vec<X86ArgClass>, _total_size: u64) {
    if classes.is_empty() {
        return;
    }

    let num_eightbytes = classes.len();

    // Rule (a): if > 2 eightbytes and not all SSE/SSEUp → Memory
    if num_eightbytes > 2 {
        let all_sse = classes.iter().all(|c| {
            matches!(
                c,
                X86ArgClass::SSE | X86ArgClass::SSEUp | X86ArgClass::NoClass
            )
        });
        let first_is_sse = matches!(classes[0], X86ArgClass::SSE);
        if !(all_sse && first_is_sse) {
            for c in classes.iter_mut() {
                *c = X86ArgClass::Memory;
            }
            return;
        }
    }

    // Rule (b): SSEUp is only valid as second eightbyte after SSE
    for i in 0..num_eightbytes {
        if classes[i] == X86ArgClass::SSEUp {
            if i == 0 || classes[i - 1] != X86ArgClass::SSE {
                classes[i] = X86ArgClass::SSE;
            }
        }
    }

    // Rule (c): Only the first two eightbytes can be in registers;
    // everything beyond goes to memory (already handled by rule (a) for > 2).
    // For exactly 2 eightbytes, validate the pairing.
    if num_eightbytes == 2 {
        if classes[0] == X86ArgClass::SSE && classes[1] == X86ArgClass::SSEUp {
            // Valid pair: SSE in XMMn, SSEUp in XMM(n+1)
        } else if classes[0] == X86ArgClass::Integer && classes[1] == X86ArgClass::Integer {
            // Valid pair: both in GPRs
        } else if classes[0] == X86ArgClass::NoClass && classes[1] == X86ArgClass::Integer {
            // First eightbyte is empty → second goes in a GPR
        } else if classes[0] == X86ArgClass::Integer && classes[1] == X86ArgClass::NoClass {
            // Only first eightbyte used
        } else if classes[0] == X86ArgClass::SSE && classes[1] == X86ArgClass::NoClass {
            // Only first eightbyte SSE
        } else {
            // Mixed: pass in memory
            for c in classes.iter_mut() {
                *c = X86ArgClass::Memory;
            }
        }
    }
}

// ============================================================================
// System V AMD64 ABI argument assignment
// ============================================================================

/// Assign arguments per System V AMD64 ABI.
pub fn assign_sysv_args(
    args: &[Type],
    type_map: &HashMap<TypeId, Type>,
) -> (Vec<X86ArgInfo>, X86CallFrame) {
    let int_regs = vec![RDI, RSI, RDX, RCX, R8, R9];
    let sse_regs = vec![XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];

    let mut arg_infos = Vec::new();
    let mut int_used = 0usize;
    let mut sse_used = 0usize;
    let mut stack_offset = 8i64; // First stack arg is above the return address
    let mut arg_offsets = Vec::new();

    for ty in args {
        let size = type_size(ty, type_map);
        let align = type_alignment(ty, type_map);
        let classes = classify_arg_type(ty, 0, type_map);

        let mut info = X86ArgInfo {
            size: size as u32,
            alignment: align as u32,
            ..Default::default()
        };

        if classes.iter().any(|c| *c == X86ArgClass::Memory) {
            // Pass on stack
            let padding = if stack_offset % (align as i64) != 0 {
                (align as i64) - (stack_offset % (align as i64))
            } else {
                0
            };
            stack_offset += padding;
            info.stack_offset = stack_offset;
            info.padding = padding as u32;
            info.is_byval = ty.is_struct();
            stack_offset += size as i64;
            arg_offsets.push(info.stack_offset);
        } else {
            // Try to assign to registers
            let int_needed = classes
                .iter()
                .filter(|c| **c == X86ArgClass::Integer)
                .count();
            let sse_needed = classes
                .iter()
                .filter(|c| matches!(c, X86ArgClass::SSE | X86ArgClass::SSEUp))
                .count();

            if int_used + int_needed <= int_regs.len() && sse_used + sse_needed <= sse_regs.len() {
                info.in_reg = true;
                let mut ridx = int_used;
                for cls in &classes {
                    match cls {
                        X86ArgClass::Integer => {
                            if ridx < int_regs.len() {
                                info.regs.push(int_regs[ridx]);
                                ridx += 1;
                            }
                        }
                        X86ArgClass::SSE | X86ArgClass::SSEUp => {
                            if sse_used < sse_regs.len() {
                                info.regs.push(sse_regs[sse_used]);
                                sse_used += 1;
                            }
                        }
                        X86ArgClass::NoClass => {}
                        _ => {}
                    }
                }
                int_used += int_needed;
                // sse_used already incremented in the loop
                info.stack_offset = 0; // Not on stack
                arg_offsets.push(-1); // Sentinel
            } else {
                // Not enough registers → pass on stack
                let padding = if stack_offset % (align as i64) != 0 {
                    (align as i64) - (stack_offset % (align as i64))
                } else {
                    0
                };
                stack_offset += padding;
                info.stack_offset = stack_offset;
                info.padding = padding as u32;
                info.is_byval = ty.is_struct();
                stack_offset += size as i64;
                arg_offsets.push(info.stack_offset);
            }
        }

        arg_infos.push(info);
    }

    // Align stack to 16 bytes
    let alignment = 16i64;
    let padding = if stack_offset % alignment != 0 {
        alignment - (stack_offset % alignment)
    } else {
        0
    };

    let frame = X86CallFrame {
        stack_size: stack_offset + padding,
        arg_offsets,
        return_save_area: None,
        shadow_store_size: 0,
        alignment_padding: padding,
    };

    (arg_infos, frame)
}

/// Determine return registers for System V from the classified classes.
fn sysv_return_regs_from_classes(classes: &[X86ArgClass]) -> Vec<u16> {
    let mut regs = Vec::new();

    for cls in classes {
        match cls {
            X86ArgClass::Integer => {
                if regs.is_empty() {
                    regs.push(RAX);
                } else if regs.len() == 1 {
                    regs.push(RDX);
                }
            }
            X86ArgClass::SSE | X86ArgClass::SSEUp => {
                if regs.is_empty() {
                    regs.push(XMM0);
                } else if regs.len() == 1 {
                    regs.push(XMM1);
                }
            }
            X86ArgClass::X87 => {
                regs.push(ST0);
            }
            X86ArgClass::Memory => {
                // Hidden pointer in RAX
                regs.push(RAX);
            }
            _ => {}
        }
    }

    if regs.is_empty() {
        regs.push(RAX); // Default for single integers
    }

    regs
}

// ============================================================================
// Microsoft x64 ABI argument assignment
// ============================================================================

/// Assign arguments per Microsoft x64 calling convention.
///
/// Integer and floating-point arguments share the same slot counter:
/// - Slot 0 → RCX (int) / XMM0 (float)
/// - Slot 1 → RDX (int) / XMM1 (float)
/// - Slot 2 → R8  (int) / XMM2 (float)
/// - Slot 3 → R9  (int) / XMM3 (float)
fn assign_win64_args(
    args: &[Type],
    type_map: &HashMap<TypeId, Type>,
) -> (Vec<X86ArgInfo>, X86CallFrame) {
    let int_regs = vec![RCX, RDX, R8, R9];
    let sse_regs = vec![XMM0, XMM1, XMM2, XMM3];
    let shadow_size: i64 = 32;

    let mut arg_infos = Vec::new();
    let mut slot = 0usize; // Shared argument slot (0-3 for registers)
    let mut stack_offset = shadow_size + 8; // After shadow store + return address
    let mut arg_offsets = Vec::new();

    for ty in args {
        let size = type_size(ty, type_map);
        let align = type_alignment(ty, type_map).max(8);

        let mut info = X86ArgInfo {
            size: size as u32,
            alignment: align as u32,
            ..Default::default()
        };

        if ty.is_floating_point() && size <= 8 {
            // Float/double in XMM at the current slot
            if slot < sse_regs.len() {
                info.in_reg = true;
                info.regs.push(sse_regs[slot]);
                slot += 1;
            } else {
                // Stack spill
                stack_offset = align_to_i64(stack_offset, align as i64);
                info.stack_offset = stack_offset;
                stack_offset += 8;
                arg_offsets.push(info.stack_offset);
                arg_infos.push(info);
                continue;
            }
        } else if size <= 8 {
            // Integer or pointer
            if slot < int_regs.len() {
                info.in_reg = true;
                info.regs.push(int_regs[slot]);
                slot += 1;
            } else {
                stack_offset = align_to_i64(stack_offset, align as i64);
                info.stack_offset = stack_offset;
                stack_offset += 8;
            }
        } else if size <= 16 && (ty.is_struct() || ty.is_vector()) {
            // __m128 or small struct — try registers
            if slot < int_regs.len() {
                info.in_reg = true;
                info.regs.push(int_regs[slot]);
                slot += 1;
                // May need second register
                if size > 8 && slot < int_regs.len() {
                    info.regs.push(int_regs[slot]);
                    slot += 1;
                }
            } else {
                stack_offset = align_to_i64(stack_offset, align as i64);
                info.stack_offset = stack_offset;
                info.is_byval = true;
                stack_offset += size as i64;
            }
        } else {
            // Large aggregate: pass by pointer (hidden copy)
            if slot < int_regs.len() {
                info.in_reg = true;
                info.regs.push(int_regs[slot]);
                info.is_byval = true;
                slot += 1;
            } else {
                stack_offset = align_to_i64(stack_offset, 8);
                info.stack_offset = stack_offset;
                info.is_byval = true;
                stack_offset += 8;
            }
        }

        if !info.in_reg {
            arg_offsets.push(info.stack_offset);
        } else {
            arg_offsets.push(-1);
        }

        arg_infos.push(info);
    }

    // Stack must be 16-byte aligned
    let alignment = 16i64;
    let padding = if stack_offset % alignment != 0 {
        alignment - (stack_offset % alignment)
    } else {
        0
    };

    let frame = X86CallFrame {
        stack_size: stack_offset + padding,
        arg_offsets,
        return_save_area: None,
        shadow_store_size: shadow_size,
        alignment_padding: padding,
    };

    (arg_infos, frame)
}

/// Win64 return value register assignment.
fn win64_return_regs(ty: &Type, size: u64) -> Vec<u16> {
    if ty.is_floating_point() && size <= 8 {
        vec![XMM0]
    } else if size <= 8 {
        vec![RAX]
    } else if size <= 16 && (ty.is_struct() || ty.is_vector()) {
        vec![RAX, RDX]
    } else {
        // Hidden pointer returned in RAX
        vec![RAX]
    }
}

// ============================================================================
// 32-bit calling convention argument assignment
// ============================================================================

/// Assign arguments for cdecl (all on stack, caller cleans).
fn assign_cdecl_args(
    args: &[Type],
    type_map: &HashMap<TypeId, Type>,
) -> (Vec<X86ArgInfo>, X86CallFrame) {
    assign_stack_only_args(args, type_map)
}

/// Assign arguments for stdcall (all on stack, callee cleans).
fn assign_stdcall_args(
    args: &[Type],
    type_map: &HashMap<TypeId, Type>,
) -> (Vec<X86ArgInfo>, X86CallFrame) {
    assign_stack_only_args(args, type_map)
}

/// Assign arguments for 32-bit fastcall (ECX, EDX then stack).
fn assign_fastcall_args(
    args: &[Type],
    type_map: &HashMap<TypeId, Type>,
) -> (Vec<X86ArgInfo>, X86CallFrame) {
    let int_regs = vec![ECX, EDX];
    let mut arg_infos = Vec::new();
    let mut int_used = 0usize;
    let mut stack_offset = 4i64; // Above return address (32-bit)
    let mut arg_offsets = Vec::new();

    for ty in args {
        let size = type_size(ty, type_map);
        let align = type_alignment(ty, type_map).max(4);

        let mut info = X86ArgInfo {
            size: size as u32,
            alignment: align as u32,
            ..Default::default()
        };

        if size <= 4 && int_used < int_regs.len() {
            info.in_reg = true;
            info.regs.push(int_regs[int_used]);
            int_used += 1;
            arg_offsets.push(-1);
        } else {
            let padding = if stack_offset % (align as i64) != 0 {
                (align as i64) - (stack_offset % (align as i64))
            } else {
                0
            };
            stack_offset += padding;
            info.stack_offset = stack_offset;
            info.padding = padding as u32;
            stack_offset += size as i64;
            arg_offsets.push(info.stack_offset);
        }

        arg_infos.push(info);
    }

    let frame = X86CallFrame {
        stack_size: stack_offset,
        arg_offsets,
        return_save_area: None,
        shadow_store_size: 0,
        alignment_padding: 0,
    };

    (arg_infos, frame)
}

/// Assign arguments for 32-bit thiscall (ECX = this, rest on stack).
fn assign_thiscall_args(
    args: &[Type],
    type_map: &HashMap<TypeId, Type>,
) -> (Vec<X86ArgInfo>, X86CallFrame) {
    let mut arg_infos = Vec::new();
    let mut this_assigned = false;
    let mut stack_offset = 4i64;
    let mut arg_offsets = Vec::new();

    for ty in args {
        let size = type_size(ty, type_map);
        let align = type_alignment(ty, type_map).max(4);

        let mut info = X86ArgInfo {
            size: size as u32,
            alignment: align as u32,
            ..Default::default()
        };

        if !this_assigned {
            info.in_reg = true;
            info.regs.push(ECX);
            this_assigned = true;
            arg_offsets.push(-1);
        } else {
            let padding = if stack_offset % (align as i64) != 0 {
                (align as i64) - (stack_offset % (align as i64))
            } else {
                0
            };
            stack_offset += padding;
            info.stack_offset = stack_offset;
            info.padding = padding as u32;
            stack_offset += size as i64;
            arg_offsets.push(info.stack_offset);
        }

        arg_infos.push(info);
    }

    let frame = X86CallFrame {
        stack_size: stack_offset,
        arg_offsets,
        return_save_area: None,
        shadow_store_size: 0,
        alignment_padding: 0,
    };

    (arg_infos, frame)
}

/// Assign arguments for 32-bit vectorcall (XMM0-5 for SIMD, ECX/EDX for int).
fn assign_vectorcall_args(
    args: &[Type],
    type_map: &HashMap<TypeId, Type>,
) -> (Vec<X86ArgInfo>, X86CallFrame) {
    let int_regs = vec![ECX, EDX];
    let xmm_regs = vec![XMM0, XMM1, XMM2, XMM3, XMM4, XMM5];
    let mut arg_infos = Vec::new();
    let mut int_used = 0usize;
    let mut xmm_used = 0usize;
    let mut stack_offset = 4i64;
    let mut arg_offsets = Vec::new();

    for ty in args {
        let size = type_size(ty, type_map);
        let align = type_alignment(ty, type_map).max(4);

        let mut info = X86ArgInfo {
            size: size as u32,
            alignment: align as u32,
            ..Default::default()
        };

        if ty.is_vector() && xmm_used < xmm_regs.len() {
            info.in_reg = true;
            info.regs.push(xmm_regs[xmm_used]);
            xmm_used += 1;
            arg_offsets.push(-1);
        } else if size <= 4 && int_used < int_regs.len() {
            info.in_reg = true;
            info.regs.push(int_regs[int_used]);
            int_used += 1;
            arg_offsets.push(-1);
        } else {
            let padding = if stack_offset % (align as i64) != 0 {
                (align as i64) - (stack_offset % (align as i64))
            } else {
                0
            };
            stack_offset += padding;
            info.stack_offset = stack_offset;
            info.padding = padding as u32;
            stack_offset += size as i64;
            arg_offsets.push(info.stack_offset);
        }

        arg_infos.push(info);
    }

    let frame = X86CallFrame {
        stack_size: stack_offset,
        arg_offsets,
        return_save_area: None,
        shadow_store_size: 0,
        alignment_padding: 0,
    };

    (arg_infos, frame)
}

/// Assign all arguments on the stack (used for cdecl, stdcall, and fallback).
fn assign_stack_only_args(
    args: &[Type],
    type_map: &HashMap<TypeId, Type>,
) -> (Vec<X86ArgInfo>, X86CallFrame) {
    let mut arg_infos = Vec::new();
    let mut stack_offset = 4i64; // Above return address (32-bit) or 8 (64-bit)
    let mut arg_offsets = Vec::new();

    // Detect 64-bit by checking pointer size in type_map
    let ptr_size: i64 = 8; // Default to 64-bit

    for ty in args {
        let size = type_size(ty, type_map);
        let align = type_alignment(ty, type_map);

        let padding = if stack_offset % (align as i64) != 0 {
            (align as i64) - (stack_offset % (align as i64))
        } else {
            0
        };
        stack_offset += padding;

        let info = X86ArgInfo {
            in_reg: false,
            stack_offset,
            size: size as u32,
            alignment: align as u32,
            is_byval: ty.is_struct() && size > ptr_size as u64,
            is_sret: false,
            padding: padding as u32,
            ..Default::default()
        };

        stack_offset += size as i64;
        arg_offsets.push(info.stack_offset);
        arg_infos.push(info);
    }

    let frame = X86CallFrame {
        stack_size: stack_offset,
        arg_offsets,
        return_save_area: None,
        shadow_store_size: 0,
        alignment_padding: 0,
    };

    (arg_infos, frame)
}

/// 32-bit return value registers: EAX for int/ptr, EDX:EAX for i64, ST0 for x87.
fn cdecl_return_regs(ty: &Type, type_map: &HashMap<TypeId, Type>) -> Vec<u16> {
    match &ty.kind {
        TypeKind::Void => vec![],
        TypeKind::X86FP80 => vec![ST0],
        TypeKind::Float | TypeKind::Double => {
            // Return in ST0 (x87) for 32-bit; in SSE for modern targets
            // Use XMM0 for SSE-enabled 32-bit
            vec![XMM0]
        }
        TypeKind::Integer { bits } if *bits <= 32 => vec![EAX],
        TypeKind::Integer { bits } if *bits <= 64 => vec![EDX, EAX],
        TypeKind::Pointer { .. } => vec![EAX],
        _ => {
            let size = type_size(ty, type_map);
            if size <= 4 {
                vec![EAX]
            } else if size <= 8 {
                vec![EDX, EAX]
            } else {
                // Hidden pointer in EAX
                vec![EAX]
            }
        }
    }
}

/// i64 align_to for signed values.
fn align_to_i64(value: i64, alignment: i64) -> i64 {
    if alignment == 0 {
        return value;
    }
    ((value + alignment - 1) / alignment) * alignment
}

// ============================================================================
// x86-64 System V: Full Eightbyte Classification
// ============================================================================

/// The x86-64 System V ABI classifies each eightbyte of an aggregate type
/// into one of these classes, which determines how it is passed.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum EightByteClass {
    /// No class (padding or uninitialized).
    NO_CLASS,
    /// Pass in a general-purpose register (or on stack if registers exhausted).
    INTEGER,
    /// Pass in an SSE register (XMM).
    SSE,
    /// Pass in an SSEUP register (the upper half of an XMM pair).
    SSEUP,
    /// Pass in an X87 floating-point register (87-class).
    X87,
    /// Pass in an X87UP register.
    X87UP,
    /// Pass in a pair of registers (COMPLEX_X87).
    COMPLEX_X87,
    /// Pass in memory (on the stack).
    MEMORY,
}

impl EightByteClass {
    /// Check if this class is a register-passing class.
    pub fn is_register_class(&self) -> bool {
        matches!(
            self,
            Self::INTEGER | Self::SSE | Self::SSEUP | Self::X87 | Self::X87UP
        )
    }

    /// Check if two classes can be merged (per ABI post-merging rules).
    pub fn can_merge_with(&self, other: &Self) -> bool {
        match (self, other) {
            // INTEGER + SSE = MEMORY
            (Self::INTEGER, Self::SSE) | (Self::SSE, Self::INTEGER) => false,
            // INTEGER + INTEGER = INTEGER
            (Self::INTEGER, Self::INTEGER) => true,
            // SSE + SSEUP = SSE
            (Self::SSE, Self::SSEUP) | (Self::SSEUP, Self::SSE) => true,
            // X87 + X87UP = X87
            (Self::X87, Self::X87UP) | (Self::X87UP, Self::X87) => true,
            // Two SSE = SSE
            (Self::SSE, Self::SSE) => true,
            // Two INTEGER (both INTEGER or INTEGER + NO_CLASS) = INTEGER
            (Self::INTEGER, Self::NO_CLASS) | (Self::NO_CLASS, Self::INTEGER) => true,
            (Self::SSE, Self::NO_CLASS) | (Self::NO_CLASS, Self::SSE) => true,
            // Same classes
            (a, b) if a == b => true,
            _ => false,
        }
    }

    /// Post-merging cleanup: simplify class pairs to canonical form.
    pub fn post_merge(a: Self, b: Self) -> (Self, Self) {
        match (a, b) {
            (Self::MEMORY, _) | (_, Self::MEMORY) => (Self::MEMORY, Self::MEMORY),
            (Self::INTEGER, Self::SSE) | (Self::SSE, Self::INTEGER) => (Self::MEMORY, Self::MEMORY),
            (Self::SSEUP, Self::SSE) => (Self::SSE, Self::SSEUP),
            (Self::X87UP, Self::X87) => (Self::X87, Self::X87UP),
            // Two SSEUP → SSE + SSEUP
            (Self::SSEUP, Self::SSEUP) => (Self::SSE, Self::SSEUP),
            // Two X87UP → X87 + X87UP
            (Self::X87UP, Self::X87UP) => (Self::X87, Self::X87UP),
            other => other,
        }
    }
}

/// A complete eightbyte classification result for a struct/union.
#[derive(Debug, Clone)]
pub struct EightByteClassification {
    /// Classification for each eightbyte (0-3 eightbytes for up to 32-byte types).
    pub classes: [EightByteClass; 4],
    /// Number of valid eightbytes.
    pub num_eightbytes: u8,
    /// Whether this type must be passed in memory (indirect).
    pub is_indirect: bool,
    /// Whether this is a homogeneous floating-point aggregate (HFA).
    pub is_hfa: bool,
    /// For HFAs: the number of homogeneous elements.
    pub hfa_count: u8,
}

impl EightByteClassification {
    pub fn new() -> Self {
        Self {
            classes: [EightByteClass::NO_CLASS; 4],
            num_eightbytes: 0,
            is_indirect: false,
            is_hfa: false,
            hfa_count: 0,
        }
    }

    /// Classify as memory (indirect).
    pub fn memory() -> Self {
        Self {
            classes: [EightByteClass::MEMORY; 4],
            num_eightbytes: 0,
            is_indirect: true,
            is_hfa: false,
            hfa_count: 0,
        }
    }

    /// Check if this classification requires sret (hidden struct return).
    pub fn needs_sret(&self) -> bool {
        self.is_indirect || self.classes[0] == EightByteClass::MEMORY
    }

    /// Get the GPR count needed (number of INTEGER eightbytes).
    pub fn gpr_count(&self) -> u8 {
        self.classes
            .iter()
            .take(self.num_eightbytes as usize)
            .filter(|c| **c == EightByteClass::INTEGER)
            .count() as u8
    }

    /// Get the SSE register count needed.
    pub fn sse_count(&self) -> u8 {
        self.classes
            .iter()
            .take(self.num_eightbytes as usize)
            .filter(|c| matches!(c, EightByteClass::SSE | EightByteClass::SSEUP))
            .count() as u8
    }
}

impl Default for EightByteClassification {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// HFA (Homogeneous Floating-point Aggregate) Detection
// ============================================================================

/// Detects whether a struct/union is an HFA or HVA (Homogeneous Vector Aggregate).
/// HFAs are structs composed entirely of the same floating-point type and
/// are passed in SIMD/FP registers instead of on the stack.
#[derive(Debug, Clone)]
pub struct HFADetector;

impl HFADetector {
    /// Check if a type is an HFA.
    /// Returns (base_type, count) if it is, None otherwise.
    pub fn detect_hfa(fields: &[HfaFieldInfo]) -> Option<(HfaBaseType, u8)> {
        if fields.is_empty() {
            return None;
        }

        if fields.len() > 4 {
            return None; // Max 4 members for HFA on x86-64
        }

        let base = fields[0].base_type;
        if base == HfaBaseType::None {
            return None;
        }

        // All fields must have the same base type
        for field in fields.iter().skip(1) {
            if field.base_type != base {
                return None;
            }
        }

        let count = fields.len() as u8;
        Some((base, count))
    }
}

/// Base types for HFA detection.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum HfaBaseType {
    None,
    Float,
    Double,
    Float128,
    Float16,
    BFloat16,
    Vector64,
    Vector128,
}

/// Information about a struct field for HFA detection.
#[derive(Debug, Clone, Copy)]
pub struct HfaFieldInfo {
    pub base_type: HfaBaseType,
    pub offset: u32,
    pub size: u32,
}

// ============================================================================
// Microsoft x64 Calling Convention
// ============================================================================

/// Microsoft x64 calling convention parameters.
#[derive(Debug, Clone)]
pub struct MicrosoftX64CC {
    /// Shadow space (home space) size: 32 bytes (4 QWORDs) for the first 4 args.
    pub shadow_space: u32,
    /// Whether this is __vectorcall (uses XMM registers for SIMD args).
    pub is_vectorcall: bool,
    /// Whether this is __fastcall (first 2 args in RCX, RDX).
    pub is_fastcall: bool,
    /// Required stack alignment.
    pub stack_alignment: u32,
}

impl MicrosoftX64CC {
    pub fn standard() -> Self {
        Self {
            shadow_space: 32,
            is_vectorcall: false,
            is_fastcall: false,
            stack_alignment: 16,
        }
    }

    pub fn vectorcall() -> Self {
        Self {
            shadow_space: 32,
            is_vectorcall: true,
            is_fastcall: false,
            stack_alignment: 16,
        }
    }

    pub fn fastcall() -> Self {
        Self {
            shadow_space: 32,
            is_vectorcall: false,
            is_fastcall: true,
            stack_alignment: 16,
        }
    }

    /// Get the integer parameter registers for MS x64.
    pub fn int_arg_regs(&self) -> &[u16] {
        if self.is_fastcall {
            &[RCX, RDX]
        } else {
            &[RCX, RDX, R8, R9]
        }
    }

    /// Get the XMM parameter registers for vectorcall.
    pub fn xmm_arg_regs(&self) -> &[u16] {
        if self.is_vectorcall {
            &[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]
        } else {
            &[XMM0, XMM1, XMM2, XMM3]
        }
    }

    /// Get the caller-saved (volatile) registers for MS x64.
    pub fn caller_saved_regs(&self) -> Vec<u16> {
        vec![RAX, RCX, RDX, R8, R9, R10, R11]
    }

    /// Get the callee-saved (non-volatile) registers for MS x64.
    pub fn callee_saved_regs(&self) -> Vec<u16> {
        vec![RBX, RBP, RDI, RSI, R12, R13, R14, R15]
    }

    /// Get the required shadow space size.
    pub fn shadow_space_size(&self) -> u32 {
        self.shadow_space
    }

    /// Check if a type is passed indirectly (by pointer) in MS x64.
    pub fn is_indirect(&self, size: u32) -> bool {
        // MS x64 passes types larger than 8 bytes indirectly,
        // unless they are powers of 2 (1,2,4,8) and not aggregates.
        size > 8 && !size.is_power_of_two()
    }
}

// ============================================================================
// X86-32 Calling Conventions: cdecl, stdcall, fastcall, thiscall, vectorcall
// ============================================================================

/// X86-32 calling convention enumeration.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum X86_32CallingConvention {
    /// cdecl: caller cleans stack, all args on stack.
    CDecl,
    /// stdcall: callee cleans stack, all args on stack.
    StdCall,
    /// fastcall: first 2 args in ECX, EDX; rest on stack.
    FastCall,
    /// thiscall: 'this' pointer in ECX; rest on stack (MSVC).
    ThisCallMSVC,
    /// thiscall: 'this' pointer in ECX; rest on stack (GNU).
    ThisCallGNU,
    /// vectorcall: first 6 args in ECX,EDX + XMM0-XMM3; rest on stack.
    VectorCall,
    /// regcall: all args in registers if possible.
    RegCall,
    /// Pascal: left-to-right evaluation, callee cleans.
    Pascal,
}

impl X86_32CallingConvention {
    /// Get the name of this convention.
    pub fn name(&self) -> &'static str {
        match self {
            Self::CDecl => "cdecl",
            Self::StdCall => "stdcall",
            Self::FastCall => "fastcall",
            Self::ThisCallMSVC => "thiscall (MSVC)",
            Self::ThisCallGNU => "thiscall (GNU)",
            Self::VectorCall => "vectorcall",
            Self::RegCall => "regcall",
            Self::Pascal => "pascal",
        }
    }

    /// Whether the callee cleans the stack.
    pub fn callee_cleans_stack(&self) -> bool {
        matches!(
            self,
            Self::StdCall | Self::FastCall | Self::ThisCallMSVC | Self::Pascal
        )
    }

    /// Get the integer argument registers for this convention.
    pub fn int_arg_regs(&self) -> &[u16] {
        match self {
            Self::FastCall | Self::ThisCallMSVC => &[ECX, EDX],
            Self::ThisCallGNU => &[ECX],
            Self::VectorCall => &[ECX, EDX],
            Self::RegCall => &[EAX, ECX, EDX, EDI, ESI],
            _ => &[],
        }
    }

    /// Get the XMM argument registers (vectorcall only).
    pub fn xmm_arg_regs(&self) -> &[u16] {
        match self {
            Self::VectorCall => &[XMM0, XMM1, XMM2, XMM3],
            _ => &[],
        }
    }

    /// Minimum stack argument alignment.
    pub fn stack_alignment(&self) -> u32 {
        match self {
            Self::VectorCall => 16,
            _ => 4,
        }
    }

    /// Check if this convention passes 'this' pointer in ECX.
    pub fn has_this_in_ecx(&self) -> bool {
        matches!(self, Self::ThisCallMSVC | Self::ThisCallGNU)
    }
}

// ============================================================================
// RegCall: __regcall with register parameter assignment
// ============================================================================

/// __regcall convention: attempts to pass arguments in registers.
/// Uses up to 5 GPRs and 8 XMM registers before spilling to stack.
#[derive(Debug, Clone)]
pub struct RegCallConvention {
    /// Integer argument registers (in order): EAX, ECX, EDX, EDI, ESI
    pub int_regs: Vec<u16>,
    /// XMM argument registers: XMM0-XMM7
    pub xmm_regs: Vec<u16>,
    /// Return register: EAX (or EDX:EAX for 64-bit returns)
    pub ret_regs: Vec<u16>,
}

impl RegCallConvention {
    pub fn new_32() -> Self {
        Self {
            int_regs: vec![EAX, ECX, EDX, EDI, ESI],
            xmm_regs: vec![XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
            ret_regs: vec![EAX, EDX],
        }
    }

    /// Assign a parameter to the next available register.
    pub fn assign_param(
        &self,
        used_int: &mut usize,
        used_xmm: &mut usize,
        is_fp: bool,
    ) -> Option<u16> {
        if is_fp && *used_xmm < self.xmm_regs.len() {
            let reg = self.xmm_regs[*used_xmm];
            *used_xmm += 1;
            Some(reg)
        } else if !is_fp && *used_int < self.int_regs.len() {
            let reg = self.int_regs[*used_int];
            *used_int += 1;
            Some(reg)
        } else {
            None
        }
    }

    /// How many integer registers remain.
    pub fn remaining_int(&self, used: usize) -> usize {
        self.int_regs.len().saturating_sub(used)
    }

    /// How many XMM registers remain.
    pub fn remaining_xmm(&self, used: usize) -> usize {
        self.xmm_regs.len().saturating_sub(used)
    }
}

// ============================================================================
// X32 ABI (ILP32 on x86-64)
// ============================================================================

/// X32 ABI: ILP32 programming model on x86-64.
/// Uses 32-bit pointers but allows access to 64-bit registers and instructions.
#[derive(Debug, Clone)]
pub struct X32ABI {
    /// Pointer size in bytes (4 for ILP32).
    pub pointer_size: u8,
    /// Size of long type.
    pub long_size: u8,
    /// Size of size_t.
    pub size_t_size: u8,
    /// Stack alignment.
    pub stack_alignment: u32,
}

impl X32ABI {
    pub fn new() -> Self {
        Self {
            pointer_size: 4,
            long_size: 4,
            size_t_size: 4,
            stack_alignment: 16,
        }
    }

    /// Check if this target uses the X32 ABI.
    pub fn is_x32(&self) -> bool {
        self.pointer_size == 4 && self.size_t_size == 4
    }

    /// Get the register class for a pointer (32-bit GPR in X32).
    pub fn pointer_register_class(&self) -> &'static str {
        "r32"
    }

    /// For X32, arguments are zero-extended to 32 bits when passed in registers.
    pub fn zero_extend_args(&self) -> bool {
        true
    }

    /// X32 still uses the full 64-bit register file, just with 32-bit values.
    pub fn available_gprs(&self) -> u8 {
        16 // full set of 64-bit GPRs available
    }
}

impl Default for X32ABI {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// Return Value Lowering: sret, multiple registers, varargs
// ============================================================================

/// Describes how a function return value is lowered to machine registers/memory.
#[derive(Debug, Clone)]
pub struct ReturnValueLowering {
    /// If Some, the value is returned via a hidden sret pointer.
    pub sret_pointer: Option<u16>,
    /// Register(s) used for the return value.
    pub ret_regs: Vec<ReturnRegister>,
    /// Whether the return value spans multiple registers.
    pub is_multi_reg: bool,
    /// Total size of the return value in bytes.
    pub size: u32,
}

/// A single register used in a return value.
#[derive(Debug, Clone, Copy)]
pub struct ReturnRegister {
    /// The physical register number.
    pub reg: u16,
    /// The byte offset into the return value.
    pub offset: u32,
    /// The size of this portion.
    pub size: u8,
    /// Whether this is a GPR or XMM register.
    pub is_xmm: bool,
}

impl ReturnValueLowering {
    pub fn new() -> Self {
        Self {
            sret_pointer: None,
            ret_regs: Vec::new(),
            is_multi_reg: false,
            size: 0,
        }
    }

    /// Set up sret (indirect) return.
    pub fn sret() -> Self {
        Self {
            sret_pointer: Some(RDI), // sret pointer passed in RDI on SysV
            ret_regs: Vec::new(),
            is_multi_reg: false,
            size: 0,
        }
    }

    /// Single integer return value in RAX.
    pub fn int_ret_rax(size: u8) -> Self {
        Self {
            sret_pointer: None,
            ret_regs: vec![ReturnRegister {
                reg: RAX,
                offset: 0,
                size,
                is_xmm: false,
            }],
            is_multi_reg: false,
            size: size as u32,
        }
    }

    /// Double-width return in RAX:RDX.
    pub fn pair_ret_rax_rdx(size: u32) -> Self {
        let half = (size / 2) as u8;
        Self {
            sret_pointer: None,
            ret_regs: vec![
                ReturnRegister {
                    reg: RAX,
                    offset: 0,
                    size: half,
                    is_xmm: false,
                },
                ReturnRegister {
                    reg: RDX,
                    offset: half as u32,
                    size: half,
                    is_xmm: false,
                },
            ],
            is_multi_reg: true,
            size,
        }
    }

    /// Floating-point return in XMM0.
    pub fn fp_ret_xmm0() -> Self {
        Self {
            sret_pointer: None,
            ret_regs: vec![ReturnRegister {
                reg: XMM0,
                offset: 0,
                size: 8,
                is_xmm: true,
            }],
            is_multi_reg: false,
            size: 8,
        }
    }

    /// HFA return: multiple XMM registers.
    pub fn hfa_ret(count: u8) -> Self {
        let xmm_regs = [XMM0, XMM1, XMM2, XMM3];
        let mut ret_regs = Vec::new();
        for i in 0..count.min(4) {
            ret_regs.push(ReturnRegister {
                reg: xmm_regs[i as usize],
                offset: (i as u32) * 8,
                size: 8,
                is_xmm: true,
            });
        }
        Self {
            sret_pointer: None,
            ret_regs,
            is_multi_reg: count > 1,
            size: count as u32 * 8,
        }
    }
}

impl Default for ReturnValueLowering {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// Varargs Handling: va_list, register save area, overflow_arg_area
// ============================================================================

/// Varargs frame setup for x86-64 System V ABI.
/// Describes the va_list structure layout and argument access.
#[derive(Debug, Clone)]
pub struct VarArgsInfo {
    /// Offset of gp_offset field in va_list.
    pub gp_offset_offset: u32,
    /// Offset of fp_offset field in va_list.
    pub fp_offset_offset: u32,
    /// Offset of overflow_arg_area pointer in va_list.
    pub overflow_arg_area_offset: u32,
    /// Offset of reg_save_area pointer in va_list.
    pub reg_save_area_offset: u32,
    /// Total size of the va_list structure.
    pub va_list_size: u32,
    /// Number of GPRs used for register save area.
    pub num_gpr_save: u8,
    /// Number of XMM registers used for register save area.
    pub num_xmm_save: u8,
    /// Size of the register save area.
    pub reg_save_area_size: u32,
}

impl VarArgsInfo {
    /// Create varargs info for x86-64 System V.
    pub fn sysv_64() -> Self {
        Self {
            gp_offset_offset: 0,
            fp_offset_offset: 4,
            overflow_arg_area_offset: 8,
            reg_save_area_offset: 16,
            va_list_size: 24,
            num_gpr_save: 6,
            num_xmm_save: 8,
            reg_save_area_size: 6 * 8 + 8 * 16, // 6 GPRs * 8 bytes + 8 XMMs * 16 bytes
        }
    }

    /// Create varargs info for Microsoft x64.
    pub fn ms_64() -> Self {
        Self {
            gp_offset_offset: 0,
            fp_offset_offset: 4,
            overflow_arg_area_offset: 8,
            reg_save_area_offset: 16,
            va_list_size: 24,
            num_gpr_save: 4,
            num_xmm_save: 4,
            reg_save_area_size: 4 * 8 + 4 * 16,
        }
    }

    /// Create varargs info for x86-32 (cdecl).
    pub fn x86_32() -> Self {
        Self {
            gp_offset_offset: 0,
            fp_offset_offset: 0,
            overflow_arg_area_offset: 4,
            reg_save_area_offset: 0,
            va_list_size: 8,
            num_gpr_save: 0,
            num_xmm_save: 0,
            reg_save_area_size: 0,
        }
    }

    /// Compute the register save area layout.
    pub fn compute_reg_save_area(&self) -> Vec<(u16, u32, u32)> {
        // Returns (register, offset, size) for each saved register
        let mut area = Vec::new();
        let mut offset: u32 = 0;

        // GPR save area
        let gprs = [RDI, RSI, RDX, RCX, R8, R9];
        for i in 0..self.num_gpr_save.min(6) {
            area.push((gprs[i as usize], offset, 8));
            offset += 8;
        }

        // XMM save area
        let xmms = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
        for i in 0..self.num_xmm_save.min(8) {
            area.push((xmms[i as usize], offset, 16));
            offset += 16;
        }

        area
    }
}

// ============================================================================
// Calling Convention: Full Stack Frame Layout
// ============================================================================

/// Describes the full stack frame layout for a function call.
#[derive(Debug, Clone)]
pub struct StackFrameLayout {
    /// Total frame size.
    pub frame_size: u32,
    /// Offset of return address from RSP on entry.
    pub return_address_offset: i32,
    /// Saved frame pointer offset (from RBP or frame base).
    pub saved_rbp_offset: i32,
    /// Offset where callee-saved registers begin.
    pub callee_saved_start: i32,
    /// Size of the callee-saved register area.
    pub callee_saved_size: u32,
    /// Offset of local variables area.
    pub locals_offset: i32,
    /// Size of local variables area.
    pub locals_size: u32,
    /// Offset of outgoing argument area (for calls made by this function).
    pub outgoing_args_offset: i32,
    /// Size of outgoing argument area.
    pub outgoing_args_size: u32,
    /// Whether this function has a red zone (128 bytes for SysV x86-64).
    pub has_red_zone: bool,
    /// Red zone size.
    pub red_zone_size: u32,
    /// Required stack alignment.
    pub stack_alignment: u32,
}

impl StackFrameLayout {
    pub fn new() -> Self {
        Self {
            frame_size: 0,
            return_address_offset: 8,
            saved_rbp_offset: 0,
            callee_saved_start: 0,
            callee_saved_size: 0,
            locals_offset: 0,
            locals_size: 0,
            outgoing_args_offset: 0,
            outgoing_args_size: 0,
            has_red_zone: true,
            red_zone_size: 128,
            stack_alignment: 16,
        }
    }

    /// Compute the final frame size with alignment.
    pub fn compute_frame_size(&mut self) {
        let mut size = self.callee_saved_size + self.locals_size + self.outgoing_args_size;
        // Align to required boundary
        if size % self.stack_alignment != 0 {
            size = (size + self.stack_alignment - 1) / self.stack_alignment * self.stack_alignment;
        }
        self.frame_size = size;
    }

    /// Calculate the offset of a stack-allocated local from RBP.
    pub fn local_offset_from_rbp(&self, index: usize, size: u32) -> i32 {
        let base = -((index + 1) as i32) * size as i32;
        base - self.callee_saved_size as i32
    }

    /// Get the offset from RSP to the given stack argument.
    pub fn arg_offset_from_rsp(&self, arg_index: usize) -> i32 {
        // Arguments beyond the register-passed ones are at positive offsets from RSP
        // after the return address and saved registers
        8 + self.callee_saved_size as i32 + (arg_index * 8) as i32
    }

    /// Check if a leaf function can avoid setting up a frame pointer.
    pub fn can_omit_frame_pointer(&self) -> bool {
        self.locals_size == 0 && self.callee_saved_size == 0 && self.outgoing_args_size == 0
    }

    /// Disable red zone (for kernel code or when frame is large).
    pub fn disable_red_zone(&mut self) {
        self.has_red_zone = false;
        self.red_zone_size = 0;
    }
}

impl Default for StackFrameLayout {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// Calling Convention: Parameter Assignment Helpers
// ============================================================================

/// Helper to split a large aggregate parameter into register-sized chunks.
#[derive(Debug, Clone)]
pub struct ParameterSplitter {
    /// Chunks of the parameter, each with register class and offset.
    pub chunks: Vec<ParamChunk>,
    /// Total parameter size in bytes.
    pub total_size: u32,
}

/// A single chunk of a split parameter.
#[derive(Debug, Clone, Copy)]
pub struct ParamChunk {
    /// The register class for this chunk.
    pub reg_class: ParamRegClass,
    /// Offset within the parameter (in bytes).
    pub offset: u32,
    /// Size of this chunk (usually 8).
    pub size: u8,
}

/// Register class for parameter chunks.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum ParamRegClass {
    /// General-purpose register (INTEGER class).
    GPR,
    /// SSE register.
    SSE,
    /// Memory (not passed in register).
    Memory,
}

impl ParameterSplitter {
    pub fn new() -> Self {
        Self {
            chunks: Vec::new(),
            total_size: 0,
        }
    }

    /// Split a parameter into eightbyte chunks per SysV ABI classification.
    pub fn split_into_eightbytes(size: u32, classification: &EightByteClassification) -> Self {
        let mut splitter = Self::new();
        splitter.total_size = size;

        let num_eightbytes = (size + 7) / 8;
        for i in 0..num_eightbytes {
            let class = if (i as usize) < classification.classes.len() {
                classification.classes[i as usize]
            } else {
                EightByteClass::NO_CLASS
            };

            let reg_class = match class {
                EightByteClass::INTEGER => ParamRegClass::GPR,
                EightByteClass::SSE | EightByteClass::SSEUP => ParamRegClass::SSE,
                EightByteClass::MEMORY => ParamRegClass::Memory,
                _ => ParamRegClass::Memory,
            };

            let chunk_size = if i == num_eightbytes - 1 && size % 8 != 0 {
                (size % 8) as u8
            } else {
                8
            };

            splitter.chunks.push(ParamChunk {
                reg_class,
                offset: i * 8,
                size: chunk_size,
            });
        }

        splitter
    }

    /// Get the number of GPRs needed for this parameter.
    pub fn gpr_needed(&self) -> u8 {
        self.chunks
            .iter()
            .filter(|c| c.reg_class == ParamRegClass::GPR)
            .count() as u8
    }

    /// Get the number of SSE registers needed.
    pub fn sse_needed(&self) -> u8 {
        self.chunks
            .iter()
            .filter(|c| c.reg_class == ParamRegClass::SSE)
            .count() as u8
    }

    /// Whether this parameter must go in memory (too many chunks).
    pub fn must_use_memory(&self, available_gprs: u8, available_sse: u8) -> bool {
        self.gpr_needed() > available_gprs || self.sse_needed() > available_sse
    }
}

impl Default for ParameterSplitter {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;
    use crate::types::{Type, TypeId, TypeKind, TypeStore};

    /// Helper to create a type map with primitive types for testing.
    fn make_type_map() -> HashMap<TypeId, Type> {
        let mut store = TypeStore::new();
        let mut map = HashMap::new();

        // Insert all the types via the store and populate the map
        let types: Vec<Type> = vec![
            Type::void(),
            Type::i1(),
            Type::i8(),
            Type::i16(),
            Type::i32(),
            Type::i64(),
            Type::i128(),
            Type::float(),
            Type::double(),
            Type::half(),
            Type::bfloat(),
            Type::fp128(),
            Type::x86_fp80(),
            Type::ppc_fp128(),
            Type::x86_mmx(),
            Type::pointer(0),
        ];

        for ty in types {
            let uniqued = store.insert_or_get(ty.clone());
            map.insert(uniqued.id, uniqued);
        }

        map
    }

    /// Register a compound type (struct, array, vector) and return its TypeId.
    fn register_type(ty: Type, store: &mut TypeStore, map: &mut HashMap<TypeId, Type>) -> TypeId {
        let uniqued = store.insert_or_get(ty);
        let id = uniqued.id;
        map.insert(id, uniqued);
        id
    }

    // ==========================================================================
    // X86ArgClass tests
    // ==========================================================================

    #[test]
    fn test_arg_class_is_register_class() {
        assert!(X86ArgClass::Integer.is_register_class());
        assert!(X86ArgClass::SSE.is_register_class());
        assert!(X86ArgClass::SSEUp.is_register_class());
        assert!(X86ArgClass::X87.is_register_class());
        assert!(!X86ArgClass::NoClass.is_register_class());
        assert!(!X86ArgClass::Memory.is_register_class());
        assert!(!X86ArgClass::X87Up.is_register_class());
        assert!(!X86ArgClass::ComplexX87.is_register_class());
    }

    #[test]
    fn test_arg_class_needs_xmm() {
        assert!(X86ArgClass::SSE.needs_xmm());
        assert!(X86ArgClass::SSEUp.needs_xmm());
        assert!(!X86ArgClass::Integer.needs_xmm());
        assert!(!X86ArgClass::NoClass.needs_xmm());
    }

    // ==========================================================================
    // X86CallingConvention method tests
    // ==========================================================================

    #[test]
    fn test_cc_name() {
        assert_eq!(X86CallingConvention::C.name(), "cdecl");
        assert_eq!(X86CallingConvention::Fast.name(), "fastcall");
        assert_eq!(X86CallingConvention::StdCall.name(), "stdcall");
        assert_eq!(X86CallingConvention::ThisCall.name(), "thiscall");
        assert_eq!(X86CallingConvention::VectorCall.name(), "vectorcall");
        assert_eq!(X86CallingConvention::X86_64_SysV.name(), "System V AMD64");
        assert_eq!(X86CallingConvention::Win64.name(), "Microsoft x64");
        assert_eq!(X86CallingConvention::X86_RegCall.name(), "regcall");
        assert_eq!(X86CallingConvention::PreserveAll.name(), "preserve_all");
        assert_eq!(X86CallingConvention::PreserveMost.name(), "preserve_most");
        assert_eq!(X86CallingConvention::GHC.name(), "GHC");
        assert_eq!(X86CallingConvention::AnyReg.name(), "anyreg");
    }

    #[test]
    fn test_cc_is_64bit() {
        assert!(X86CallingConvention::X86_64_SysV.is_64bit());
        assert!(X86CallingConvention::Win64.is_64bit());
        assert!(X86CallingConvention::X86_RegCall.is_64bit());
        assert!(!X86CallingConvention::C.is_64bit());
        assert!(!X86CallingConvention::Fast.is_64bit());
        assert!(!X86CallingConvention::StdCall.is_64bit());
        assert!(!X86CallingConvention::ThisCall.is_64bit());
    }

    #[test]
    fn test_cc_callee_cleans_stack() {
        assert!(!X86CallingConvention::C.callee_cleans_stack());
        assert!(X86CallingConvention::StdCall.callee_cleans_stack());
        assert!(X86CallingConvention::ThisCall.callee_cleans_stack());
        assert!(X86CallingConvention::Fast.callee_cleans_stack());
        assert!(!X86CallingConvention::X86_64_SysV.callee_cleans_stack());
    }

    #[test]
    fn test_cc_num_int_param_regs() {
        assert_eq!(X86CallingConvention::C.get_num_int_param_regs(), 0);
        assert_eq!(X86CallingConvention::Fast.get_num_int_param_regs(), 2);
        assert_eq!(X86CallingConvention::ThisCall.get_num_int_param_regs(), 1);
        assert_eq!(
            X86CallingConvention::X86_64_SysV.get_num_int_param_regs(),
            6
        );
        assert_eq!(X86CallingConvention::Win64.get_num_int_param_regs(), 4);
        assert_eq!(
            X86CallingConvention::X86_RegCall.get_num_int_param_regs(),
            5
        );
    }

    #[test]
    fn test_cc_num_sse_param_regs() {
        assert_eq!(X86CallingConvention::C.get_num_sse_param_regs(), 0);
        assert_eq!(X86CallingConvention::VectorCall.get_num_sse_param_regs(), 6);
        assert_eq!(
            X86CallingConvention::X86_64_SysV.get_num_sse_param_regs(),
            8
        );
        assert_eq!(X86CallingConvention::Win64.get_num_sse_param_regs(), 4);
    }

    #[test]
    fn test_cc_get_int_param_regs_sysv() {
        let regs = X86CallingConvention::X86_64_SysV.get_int_param_regs();
        assert_eq!(regs, vec![RDI, RSI, RDX, RCX, R8, R9]);
    }

    #[test]
    fn test_cc_get_int_param_regs_win64() {
        let regs = X86CallingConvention::Win64.get_int_param_regs();
        assert_eq!(regs, vec![RCX, RDX, R8, R9]);
    }

    #[test]
    fn test_cc_get_sse_param_regs_sysv() {
        let regs = X86CallingConvention::X86_64_SysV.get_sse_param_regs();
        assert_eq!(regs, vec![XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]);
    }

    #[test]
    fn test_cc_get_stack_alignment() {
        assert_eq!(X86CallingConvention::X86_64_SysV.get_stack_alignment(), 16);
        assert_eq!(X86CallingConvention::Win64.get_stack_alignment(), 16);
        assert_eq!(X86CallingConvention::C.get_stack_alignment(), 4);
    }

    #[test]
    fn test_cc_get_shadow_store_size() {
        assert_eq!(X86CallingConvention::Win64.get_shadow_store_size(), 32);
        assert_eq!(X86CallingConvention::X86_64_SysV.get_shadow_store_size(), 0);
        assert_eq!(X86CallingConvention::C.get_shadow_store_size(), 0);
    }

    #[test]
    fn test_cc_uses_register_params() {
        assert!(!X86CallingConvention::C.uses_register_params());
        assert!(X86CallingConvention::Fast.uses_register_params());
        assert!(!X86CallingConvention::StdCall.uses_register_params());
        assert!(X86CallingConvention::ThisCall.uses_register_params());
        assert!(X86CallingConvention::X86_64_SysV.uses_register_params());
        assert!(X86CallingConvention::Win64.uses_register_params());
    }

    // ==========================================================================
    // Type size/alignment computation tests
    // ==========================================================================

    #[test]
    fn test_type_size_primitives() {
        let map = make_type_map();

        assert_eq!(type_size(&Type::void(), &map), 0);
        assert_eq!(type_size(&Type::i1(), &map), 1);
        assert_eq!(type_size(&Type::i8(), &map), 1);
        assert_eq!(type_size(&Type::i16(), &map), 2);
        assert_eq!(type_size(&Type::i32(), &map), 4);
        assert_eq!(type_size(&Type::i64(), &map), 8);
        assert_eq!(type_size(&Type::i128(), &map), 16);
        assert_eq!(type_size(&Type::float(), &map), 4);
        assert_eq!(type_size(&Type::double(), &map), 8);
        assert_eq!(type_size(&Type::half(), &map), 2);
        assert_eq!(type_size(&Type::fp128(), &map), 16);
        assert_eq!(type_size(&Type::x86_fp80(), &map), 16);
        assert_eq!(type_size(&Type::pointer(0), &map), 8);
        assert_eq!(type_size(&Type::x86_mmx(), &map), 8);
    }

    #[test]
    fn test_type_alignment_primitives() {
        let map = make_type_map();

        assert_eq!(type_alignment(&Type::i8(), &map), 1);
        assert_eq!(type_alignment(&Type::i16(), &map), 2);
        assert_eq!(type_alignment(&Type::i32(), &map), 4);
        assert_eq!(type_alignment(&Type::i64(), &map), 8);
        assert_eq!(type_alignment(&Type::i128(), &map), 16);
        assert_eq!(type_alignment(&Type::float(), &map), 4);
        assert_eq!(type_alignment(&Type::double(), &map), 8);
        assert_eq!(type_alignment(&Type::fp128(), &map), 16);
        assert_eq!(type_alignment(&Type::pointer(0), &map), 8);
    }

    #[test]
    fn test_type_size_array() {
        let mut store = TypeStore::new();
        let mut map = make_type_map();

        let i32_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Integer { bits: 32 }))
            .map(|(id, _)| *id)
            .unwrap();

        let arr_ty = Type::array_with(10, i32_id);
        let arr_id = register_type(arr_ty, &mut store, &mut map);

        let arr = resolve_type(arr_id, &map);
        assert_eq!(type_size(&arr, &map), 40);
    }

    #[test]
    fn test_type_size_struct() {
        let mut store = TypeStore::new();
        let mut map = make_type_map();

        let i32_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Integer { bits: 32 }))
            .map(|(id, _)| *id)
            .unwrap();
        let i64_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Integer { bits: 64 }))
            .map(|(id, _)| *id)
            .unwrap();

        // struct { i32, i64 } — i32 at offset 0, i64 at offset 8 (aligned), total 16
        let struct_ty = Type::struct_literal_with(false, vec![i32_id, i64_id]);
        let struct_id = register_type(struct_ty, &mut store, &mut map);
        let s = resolve_type(struct_id, &map);
        assert_eq!(type_size(&s, &map), 16);

        // Packed struct { i32, i64 } — total 12
        let packed_ty = Type::struct_literal_with(true, vec![i32_id, i64_id]);
        let packed_id = register_type(packed_ty, &mut store, &mut map);
        let ps = resolve_type(packed_id, &map);
        assert_eq!(type_size(&ps, &map), 12);
    }

    #[test]
    fn test_type_size_vector() {
        let mut store = TypeStore::new();
        let mut map = make_type_map();

        let f32_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Float))
            .map(|(id, _)| *id)
            .unwrap();

        // <4 x float> = 16 bytes
        let vec_ty = Type::fixed_vector_with(4, f32_id);
        let vec_id = register_type(vec_ty, &mut store, &mut map);
        let v = resolve_type(vec_id, &map);
        assert_eq!(type_size(&v, &map), 16);
        assert_eq!(type_alignment(&v, &map), 16);
    }

    // ==========================================================================
    // System V AMD64 ABI classification tests
    // ==========================================================================

    #[test]
    fn test_sysv_classify_integer_primitives() {
        let map = make_type_map();

        let classes = classify_arg_type(&Type::i32(), 0, &map);
        assert_eq!(classes, vec![X86ArgClass::Integer]);

        let classes = classify_arg_type(&Type::i64(), 0, &map);
        assert_eq!(classes, vec![X86ArgClass::Integer]);

        let classes = classify_arg_type(&Type::i128(), 0, &map);
        assert_eq!(classes.len(), 2);
        assert_eq!(classes[0], X86ArgClass::Integer);
        assert_eq!(classes[1], X86ArgClass::Integer);
    }

    #[test]
    fn test_sysv_classify_pointer() {
        let map = make_type_map();
        let classes = classify_arg_type(&Type::pointer(0), 0, &map);
        assert_eq!(classes, vec![X86ArgClass::Integer]);
    }

    #[test]
    fn test_sysv_classify_sse_primitives() {
        let map = make_type_map();

        assert_eq!(
            classify_arg_type(&Type::float(), 0, &map),
            vec![X86ArgClass::SSE]
        );
        assert_eq!(
            classify_arg_type(&Type::double(), 0, &map),
            vec![X86ArgClass::SSE]
        );
    }

    #[test]
    fn test_sysv_classify_fp128() {
        let map = make_type_map();
        let classes = classify_arg_type(&Type::fp128(), 0, &map);
        assert_eq!(classes, vec![X86ArgClass::SSE, X86ArgClass::SSEUp]);
    }

    #[test]
    fn test_sysv_classify_x86_fp80() {
        let map = make_type_map();
        // Aligned to 0 mod 16 → X87
        let classes = classify_arg_type(&Type::x86_fp80(), 0, &map);
        assert_eq!(classes, vec![X86ArgClass::X87]);

        // Not aligned to 0 mod 16 → Memory
        let classes = classify_arg_type(&Type::x86_fp80(), 8, &map);
        assert_eq!(classes, vec![X86ArgClass::Memory]);
    }

    #[test]
    fn test_sysv_classify_simple_struct() {
        let mut store = TypeStore::new();
        let mut map = make_type_map();

        let i32_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Integer { bits: 32 }))
            .map(|(id, _)| *id)
            .unwrap();
        let i32_id_2 = i32_id; // Same type, reused

        // struct { i32, i32 } — 8 bytes, two ints → one eightbyte, INTEGER
        let struct_ty = Type::struct_literal_with(false, vec![i32_id, i32_id_2]);
        let struct_id = register_type(struct_ty, &mut store, &mut map);
        let s = resolve_type(struct_id, &map);
        let classes = classify_aggregate_type(&s, &map);
        assert_eq!(classes.len(), 1);
        assert_eq!(classes[0], X86ArgClass::Integer);
    }

    #[test]
    fn test_sysv_classify_struct_with_float() {
        let mut store = TypeStore::new();
        let mut map = make_type_map();

        let f32_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Float))
            .map(|(id, _)| *id)
            .unwrap();

        // struct { float, float } — 8 bytes → one eightbyte SSE
        let struct_ty = Type::struct_literal_with(false, vec![f32_id, f32_id]);
        let struct_id = register_type(struct_ty, &mut store, &mut map);
        let s = resolve_type(struct_id, &map);
        let classes = classify_aggregate_type(&s, &map);
        assert_eq!(classes.len(), 1);
        assert_eq!(classes[0], X86ArgClass::SSE);
    }

    #[test]
    fn test_sysv_classify_large_struct() {
        let mut store = TypeStore::new();
        let mut map = make_type_map();

        let i64_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Integer { bits: 64 }))
            .map(|(id, _)| *id)
            .unwrap();

        // struct { i64, i64, i64, i64 } — 32 bytes, > 2 eightbytes → MEMORY
        let struct_ty = Type::struct_literal_with(false, vec![i64_id, i64_id, i64_id, i64_id]);
        let struct_id = register_type(struct_ty, &mut store, &mut map);
        let s = resolve_type(struct_id, &map);
        let classes = classify_aggregate_type(&s, &map);
        // > 2 eightbytes, not all SSE → Memory
        assert!(classes.iter().all(|c| *c == X86ArgClass::Memory));
    }

    #[test]
    fn test_sysv_classify_mixed_struct_sse_int() {
        let mut store = TypeStore::new();
        let mut map = make_type_map();

        let f64_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Double))
            .map(|(id, _)| *id)
            .unwrap();
        let i64_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Integer { bits: 64 }))
            .map(|(id, _)| *id)
            .unwrap();

        // struct { double, i64 } — 16 bytes, SSE + Integer → mixed → Memory
        let struct_ty = Type::struct_literal_with(false, vec![f64_id, i64_id]);
        let struct_id = register_type(struct_ty, &mut store, &mut map);
        let s = resolve_type(struct_id, &map);
        let classes = classify_aggregate_type(&s, &map);
        // SSE + Integer = SSE (SSE wins), but Integer in second → check cleanup
        // Post-merger: SSE in first, Integer in second → not SSE+SSEUp → Memory
        assert!(classes.iter().any(|c| *c == X86ArgClass::Memory));
    }

    // ==========================================================================
    // System V AMD64 argument assignment tests
    // ==========================================================================

    #[test]
    fn test_sysv_assign_reg_args() {
        let map = make_type_map();
        let args = vec![Type::i32(), Type::i64(), Type::float(), Type::double()];
        let (infos, _frame) = X86CallingConvention::X86_64_SysV.assign_args(&args, &map);

        // i32 → RDI
        assert!(infos[0].in_reg);
        assert_eq!(infos[0].regs, vec![RDI]);

        // i64 → RSI
        assert!(infos[1].in_reg);
        assert_eq!(infos[1].regs, vec![RSI]);

        // float → XMM0
        assert!(infos[2].in_reg);
        assert_eq!(infos[2].regs, vec![XMM0]);

        // double → XMM1
        assert!(infos[3].in_reg);
        assert_eq!(infos[3].regs, vec![XMM1]);
    }

    #[test]
    fn test_sysv_assign_stack_args_when_regs_exhausted() {
        let map = make_type_map();
        // 8 integer args: should exhaust RDI,RSI,RDX,RCX,R8,R9; 7th and 8th on stack
        let args = vec![
            Type::i64(),
            Type::i64(),
            Type::i64(),
            Type::i64(),
            Type::i64(),
            Type::i64(),
            Type::i64(),
            Type::i64(),
        ];
        let (infos, _frame) = X86CallingConvention::X86_64_SysV.assign_args(&args, &map);

        // First 6 in registers
        for i in 0..6 {
            assert!(infos[i].in_reg, "arg {} should be in reg", i);
        }
        // Last 2 on stack
        assert!(!infos[6].in_reg);
        assert!(!infos[7].in_reg);
        assert!(infos[6].stack_offset > 0);
        assert!(infos[7].stack_offset > infos[6].stack_offset);
    }

    #[test]
    fn test_sysv_return_regs_integer() {
        let map = make_type_map();
        let regs = X86CallingConvention::X86_64_SysV.get_return_regs(&Type::i64(), &map);
        assert_eq!(regs, vec![RAX]);

        let regs = X86CallingConvention::X86_64_SysV.get_return_regs(&Type::i128(), &map);
        assert_eq!(regs, vec![RAX, RDX]);
    }

    #[test]
    fn test_sysv_return_regs_sse() {
        let map = make_type_map();
        let regs = X86CallingConvention::X86_64_SysV.get_return_regs(&Type::float(), &map);
        assert_eq!(regs, vec![XMM0]);

        let regs = X86CallingConvention::X86_64_SysV.get_return_regs(&Type::double(), &map);
        assert_eq!(regs, vec![XMM0]);
    }

    #[test]
    fn test_sysv_return_regs_fp128() {
        let map = make_type_map();
        let regs = X86CallingConvention::X86_64_SysV.get_return_regs(&Type::fp128(), &map);
        assert_eq!(regs, vec![XMM0, XMM1]);
    }

    // ==========================================================================
    // Microsoft x64 ABI tests
    // ==========================================================================

    #[test]
    fn test_win64_assign_reg_args() {
        let map = make_type_map();
        let args = vec![Type::i32(), Type::i64(), Type::float(), Type::double()];
        let (infos, frame) = X86CallingConvention::Win64.assign_args(&args, &map);

        // i32 → RCX
        assert!(infos[0].in_reg);
        assert_eq!(infos[0].regs, vec![RCX]);

        // i64 → RDX
        assert!(infos[1].in_reg);
        assert_eq!(infos[1].regs, vec![RDX]);

        // float → XMM2 (integer slot 2 already used)
        assert!(infos[2].in_reg);
        assert_eq!(infos[2].regs, vec![XMM2]);

        // double → XMM3
        assert!(infos[3].in_reg);
        assert_eq!(infos[3].regs, vec![XMM3]);

        // Win64 has shadow space
        assert_eq!(frame.shadow_store_size, 32);
    }

    #[test]
    fn test_win64_shadow_store() {
        let map = make_type_map();
        let args = vec![Type::i32()];
        let (_infos, frame) = X86CallingConvention::Win64.assign_args(&args, &map);
        assert_eq!(frame.shadow_store_size, 32);
        assert!(frame.stack_size >= 32 + 8); // Shadow + return address + args
    }

    #[test]
    fn test_win64_return_regs() {
        let map = make_type_map();

        let regs = X86CallingConvention::Win64.get_return_regs(&Type::i64(), &map);
        assert_eq!(regs, vec![RAX]);

        let regs = X86CallingConvention::Win64.get_return_regs(&Type::float(), &map);
        assert_eq!(regs, vec![XMM0]);

        let regs = X86CallingConvention::Win64.get_return_regs(&Type::double(), &map);
        assert_eq!(regs, vec![XMM0]);
    }

    // ==========================================================================
    // 32-bit calling convention tests
    // ==========================================================================

    #[test]
    fn test_cdecl_all_stack() {
        let map = make_type_map();
        let args = vec![Type::i32(), Type::i32(), Type::i32()];
        let (infos, _frame) = X86CallingConvention::C.assign_args(&args, &map);

        for info in &infos {
            assert!(!info.in_reg);
            assert!(info.stack_offset > 0);
        }
    }

    #[test]
    fn test_fastcall_reg_args() {
        let map = make_type_map();
        let args = vec![Type::i32(), Type::i32(), Type::i32(), Type::i32()];
        let (infos, _frame) = X86CallingConvention::Fast.assign_args(&args, &map);

        // First two in ECX, EDX
        assert!(infos[0].in_reg);
        assert_eq!(infos[0].regs, vec![ECX]);
        assert!(infos[1].in_reg);
        assert_eq!(infos[1].regs, vec![EDX]);

        // Rest on stack
        assert!(!infos[2].in_reg);
        assert!(!infos[3].in_reg);
    }

    #[test]
    fn test_thiscall_ecx_first() {
        let map = make_type_map();
        let args = vec![Type::pointer(0), Type::i32()];
        let (infos, _frame) = X86CallingConvention::ThisCall.assign_args(&args, &map);

        // First arg (this) in ECX
        assert!(infos[0].in_reg);
        assert_eq!(infos[0].regs, vec![ECX]);

        // Second arg on stack
        assert!(!infos[1].in_reg);
    }

    #[test]
    fn test_vectorcall_simd_regs() {
        let mut store = TypeStore::new();
        let mut map = make_type_map();

        let f32_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Float))
            .map(|(id, _)| *id)
            .unwrap();

        let vec_ty = Type::fixed_vector_with(4, f32_id);
        let vec_id = register_type(vec_ty, &mut store, &mut map);
        let vec = resolve_type(vec_id, &map);

        let args = vec![vec.clone(), vec.clone(), vec.clone()];
        let (infos, _frame) = X86CallingConvention::VectorCall.assign_args(&args, &map);

        // First three vectors in XMM0, XMM1, XMM2
        assert!(infos[0].in_reg);
        assert_eq!(infos[0].regs, vec![XMM0]);
        assert!(infos[1].in_reg);
        assert_eq!(infos[1].regs, vec![XMM1]);
        assert!(infos[2].in_reg);
        assert_eq!(infos[2].regs, vec![XMM2]);
    }

    #[test]
    fn test_32bit_return_regs() {
        let map = make_type_map();

        let regs = cdecl_return_regs(&Type::i32(), &map);
        assert_eq!(regs, vec![EAX]);

        let regs = cdecl_return_regs(&Type::i64(), &map);
        assert_eq!(regs, vec![EDX, EAX]);

        let regs = cdecl_return_regs(&Type::float(), &map);
        assert_eq!(regs, vec![XMM0]);

        let regs = cdecl_return_regs(&Type::x86_fp80(), &map);
        assert_eq!(regs, vec![ST0]);
    }

    // ==========================================================================
    // X86ArgInfo and X86CallFrame tests
    // ==========================================================================

    #[test]
    fn test_arg_info_default() {
        let info = X86ArgInfo::default();
        assert!(!info.in_reg);
        assert!(info.regs.is_empty());
        assert_eq!(info.stack_offset, 0);
        assert_eq!(info.size, 0);
        assert_eq!(info.alignment, 1);
        assert!(!info.is_byval);
        assert!(!info.is_sret);
        assert_eq!(info.padding, 0);
    }

    #[test]
    fn test_call_frame_default() {
        let frame = X86CallFrame::default();
        assert_eq!(frame.stack_size, 0);
        assert!(frame.arg_offsets.is_empty());
        assert!(frame.return_save_area.is_none());
        assert_eq!(frame.shadow_store_size, 0);
        assert_eq!(frame.alignment_padding, 0);
    }

    // ==========================================================================
    // Merge classes ​tests
    // ==========================================================================

    #[test]
    fn test_merge_classes_basic() {
        use X86ArgClass::*;

        // NoClass + anything = anything
        assert_eq!(merge_classes(NoClass, Integer), Integer);
        assert_eq!(merge_classes(Integer, NoClass), Integer);

        // Integer + Integer = Integer
        assert_eq!(merge_classes(Integer, Integer), Integer);

        // SSE + SSE = SSE
        assert_eq!(merge_classes(SSE, SSE), SSE);

        // SSE + SSEUp = SSE
        assert_eq!(merge_classes(SSE, SSEUp), SSE);
        assert_eq!(merge_classes(SSEUp, SSE), SSE);

        // Integer + SSE = SSE (SSE wins)
        assert_eq!(merge_classes(Integer, SSE), SSE);
        assert_eq!(merge_classes(SSE, Integer), SSE);

        // Anything + Memory = Memory
        assert_eq!(merge_classes(Integer, Memory), Memory);
        assert_eq!(merge_classes(SSE, Memory), Memory);
        assert_eq!(merge_classes(Memory, NoClass), Memory);
    }

    // ==========================================================================
    // Post-merger cleanup tests
    // ==========================================================================

    #[test]
    fn test_post_merger_cleanup_two_eightbytes_valid_sse() {
        let mut classes = vec![X86ArgClass::SSE, X86ArgClass::SSEUp];
        post_merger_cleanup(&mut classes, 16);
        assert_eq!(classes, vec![X86ArgClass::SSE, X86ArgClass::SSEUp]);
    }

    #[test]
    fn test_post_merger_cleanup_two_eightbytes_mixed() {
        // SSE + Integer → Memory (not valid SSE pair)
        let mut classes = vec![X86ArgClass::SSE, X86ArgClass::Integer];
        post_merger_cleanup(&mut classes, 16);
        assert!(classes.iter().all(|c| *c == X86ArgClass::Memory));
    }

    #[test]
    fn test_post_merger_cleanup_more_than_two_not_all_sse() {
        let mut classes = vec![
            X86ArgClass::Integer,
            X86ArgClass::Integer,
            X86ArgClass::Integer,
        ];
        post_merger_cleanup(&mut classes, 24);
        assert!(classes.iter().all(|c| *c == X86ArgClass::Memory));
    }

    #[test]
    fn test_post_merger_cleanup_empty() {
        let mut classes: Vec<X86ArgClass> = vec![];
        post_merger_cleanup(&mut classes, 0);
        assert!(classes.is_empty());
    }

    // ==========================================================================
    // Needs hidden sret tests
    // ==========================================================================

    #[test]
    fn test_sysv_needs_hidden_sret() {
        let mut store = TypeStore::new();
        let mut map = make_type_map();

        let i64_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Integer { bits: 64 }))
            .map(|(id, _)| *id)
            .unwrap();

        // struct { i64 } — 8 bytes, single INTEGER eightbyte → no sret
        let small_struct = Type::struct_literal_with(false, vec![i64_id]);
        let small_id = register_type(small_struct, &mut store, &mut map);
        let small = resolve_type(small_id, &map);
        assert!(!X86CallingConvention::X86_64_SysV.needs_hidden_sret(&small, &map));

        // struct { i64, i64, i64 } — 24 bytes → sret
        let large_struct = Type::struct_literal_with(false, vec![i64_id, i64_id, i64_id]);
        let large_id = register_type(large_struct, &mut store, &mut map);
        let large = resolve_type(large_id, &map);
        assert!(X86CallingConvention::X86_64_SysV.needs_hidden_sret(&large, &map));
    }

    #[test]
    fn test_win64_needs_hidden_sret() {
        let mut store = TypeStore::new();
        let mut map = make_type_map();

        let i64_id = map
            .iter()
            .find(|(_, ty)| matches!(ty.kind, TypeKind::Integer { bits: 64 }))
            .map(|(id, _)| *id)
            .unwrap();

        // struct { i64 } — 8 bytes → fits in RAX, no sret
        let small_struct = Type::struct_literal_with(false, vec![i64_id]);
        let small_id = register_type(small_struct, &mut store, &mut map);
        let small = resolve_type(small_id, &map);
        assert!(!X86CallingConvention::Win64.needs_hidden_sret(&small, &map));

        // struct { i64, i64 } — 16 bytes → > 8 → sret
        let medium_struct = Type::struct_literal_with(false, vec![i64_id, i64_id]);
        let medium_id = register_type(medium_struct, &mut store, &mut map);
        let medium = resolve_type(medium_id, &map);
        assert!(X86CallingConvention::Win64.needs_hidden_sret(&medium, &map));
    }

    // ==========================================================================
    // Assign_args integration tests for all conventions
    // ==========================================================================

    #[test]
    fn test_stdcall_assign_all_stack() {
        let map = make_type_map();
        let args = vec![Type::i32(), Type::i32(), Type::i32()];
        let (infos, _frame) = X86CallingConvention::StdCall.assign_args(&args, &map);

        // Stdcall: all on stack (same as cdecl for arg placement)
        for info in &infos {
            assert!(!info.in_reg);
            assert!(info.stack_offset > 0);
        }
    }

    #[test]
    fn test_preserve_all_assign() {
        let map = make_type_map();
        let args = vec![Type::i32(), Type::i64()];
        let (_infos, _frame) = X86CallingConvention::PreserveAll.assign_args(&args, &map);
        // Should complete without panicking
    }
}