llvm-native-core 0.1.12

//! RISC-V Target Machine — platform configuration, pass scheduling,
//! and compilation orchestration for the RISC-V backend.
//!
//! Clean-room behavioral reconstruction from the RISC-V ISA Manual
//! and the LLVM TargetMachine interface. Zero LLVM source consultation.
//!
//! This module provides the `RiscVTargetMachine` which encapsulates
//! all target-specific configuration (triple, CPU, features, data
//! layout, optimization level) and provides the pass pipeline
//! configuration used by the compiler driver.

use crate::codegen::*;
use crate::module::Module;

// ---------------------------------------------------------------------------
// Default data layouts per RISC-V psABI
// ---------------------------------------------------------------------------

/// Default RV64 data layout string.
/// Endianness: little (e)
/// Mangling: ELF (e)
/// Pointer size: 64-bit, abi:aligned 64:64
/// Integer 64-bit: abi:aligned 64:64
/// Integer 128-bit: abi:aligned 128:128
/// Native sizes: 32, 64
/// Stack alignment: 128 bits (16 bytes)
pub const DEFAULT_RV64_DATA_LAYOUT: &str = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";

/// Default RV32 data layout string.
/// Pointer size: 32-bit, abi:aligned 32:32
/// Integer 64-bit: abi:aligned 64:64
/// No i128 specification (optional in RV32).
pub const DEFAULT_RV32_DATA_LAYOUT: &str = "e-m:e-p:32:32-i64:64-n32-S128";

// ---------------------------------------------------------------------------
// Optimization level
// ---------------------------------------------------------------------------

/// Optimization level analogous to LLVM's `CodeGenOpt::Level`.
#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
pub enum OptimizationLevel {
    /// No optimization (fast compile, debuggable output).
    O0,
    /// Basic optimizations, reasonable compile time.
    O1,
    /// Moderate optimizations (good default).
    O2,
    /// Aggressive optimizations (link-time, vectorization).
    O3,
    /// Optimize for size with minor performance impact.
    Os,
    /// Optimize aggressively for size.
    Oz,
}

impl OptimizationLevel {
    /// Returns true if this level implies any optimization.
    pub fn is_optimizing(&self) -> bool {
        !matches!(self, OptimizationLevel::O0)
    }

    /// Returns true if aggressive optimizations are enabled (O3).
    pub fn is_aggressive(&self) -> bool {
        matches!(self, OptimizationLevel::O3)
    }

    /// Returns true if size optimizations are preferred.
    pub fn is_size_optimized(&self) -> bool {
        matches!(self, OptimizationLevel::Os | OptimizationLevel::Oz)
    }

    /// Returns a human-readable name.
    pub fn as_str(&self) -> &'static str {
        match self {
            OptimizationLevel::O0 => "O0",
            OptimizationLevel::O1 => "O1",
            OptimizationLevel::O2 => "O2",
            OptimizationLevel::O3 => "O3",
            OptimizationLevel::Os => "Os",
            OptimizationLevel::Oz => "Oz",
        }
    }
}

impl std::fmt::Display for OptimizationLevel {
    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
        write!(f, "{}", self.as_str())
    }
}

// ---------------------------------------------------------------------------
// Relocation model
// ---------------------------------------------------------------------------

/// Relocation model for code generation.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum RelocModel {
    /// Non-relocatable (absolute addressing).
    Static,
    /// Position-independent code.
    PIC,
}

impl RelocModel {
    pub fn as_str(&self) -> &'static str {
        match self {
            RelocModel::Static => "static",
            RelocModel::PIC => "pic",
        }
    }
}

impl std::fmt::Display for RelocModel {
    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
        write!(f, "{}", self.as_str())
    }
}

// ---------------------------------------------------------------------------
// Code model
// ---------------------------------------------------------------------------

/// Code model governing address range assumptions.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum CodeModel {
    /// Small: code+data within ±2 GiB of each other.
    Small,
    /// Medium: code within ±2 GiB, data anywhere in 64-bit.
    Medium,
    /// Large: no restrictions (full 64-bit).
    Large,
}

impl CodeModel {
    pub fn as_str(&self) -> &'static str {
        match self {
            CodeModel::Small => "small",
            CodeModel::Medium => "medium",
            CodeModel::Large => "large",
        }
    }
}

impl std::fmt::Display for CodeModel {
    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
        write!(f, "{}", self.as_str())
    }
}

// ---------------------------------------------------------------------------
// RiscVTargetMachine
// ---------------------------------------------------------------------------

/// RISC-V target machine: encapsulates all platform-specific
/// configuration used during compilation.
///
/// # Fields
/// * `triple` — target triple string (e.g. "riscv64-unknown-elf")
/// * `cpu` — CPU name (e.g. "generic-rv64")
/// * `features` — ISA feature string (e.g. "+m,+a,+f,+d,+c")
/// * `is_64bit` — whether this is an RV64 target
/// * `data_layout` — target data layout string
/// * `opt_level` — optimization level
/// * `reloc_model` — relocation model
/// * `code_model` — code model
pub struct RiscVTargetMachine {
    /// Target triple string.
    pub triple: String,
    /// CPU name for scheduling/tuning.
    pub cpu: String,
    /// ISA feature string (e.g. "+m,+a,+f,+d,+c").
    pub features: String,
    /// Whether this machine is 64-bit RISC-V.
    pub is_64bit: bool,
    /// Data layout string.
    pub data_layout: String,
    /// Optimization level.
    pub opt_level: OptimizationLevel,
    /// Relocation model.
    pub reloc_model: RelocModel,
    /// Code model.
    pub code_model: CodeModel,
}

impl RiscVTargetMachine {
    /// Construct a new `RiscVTargetMachine` from triple, cpu, and features.
    ///
    /// The `is_64bit` flag is detected from the triple. If the triple
    /// starts with "riscv64", the target is 64-bit; otherwise it is
    /// 32-bit. The `data_layout` is selected accordingly.
    pub fn new(triple: &str, cpu: &str, features: &str) -> Self {
        let is_64bit = Self::detect_64bit_from_triple(triple);
        let data_layout = if is_64bit {
            DEFAULT_RV64_DATA_LAYOUT.to_string()
        } else {
            DEFAULT_RV32_DATA_LAYOUT.to_string()
        };

        RiscVTargetMachine {
            triple: triple.to_string(),
            cpu: cpu.to_string(),
            features: features.to_string(),
            is_64bit,
            data_layout,
            opt_level: OptimizationLevel::O2,
            reloc_model: RelocModel::Static,
            code_model: CodeModel::Small,
        }
    }

    /// Detect 64-bit from triple string. Returns true if the triple
    /// begins with "riscv64" (case-insensitive).
    fn detect_64bit_from_triple(triple: &str) -> bool {
        let lower = triple.to_lowercase();
        lower.starts_with("riscv64")
    }

    // ------------------------------------------------------------------
    // Builder-style setters
    // ------------------------------------------------------------------

    /// Set the optimization level and return self for chaining.
    pub fn with_opt_level(mut self, level: OptimizationLevel) -> Self {
        self.opt_level = level;
        self
    }

    /// Set the relocation model and return self for chaining.
    pub fn with_reloc_model(mut self, model: RelocModel) -> Self {
        self.reloc_model = model;
        self
    }

    /// Set the code model and return self for chaining.
    pub fn with_code_model(mut self, model: CodeModel) -> Self {
        self.code_model = model;
        self
    }

    // ------------------------------------------------------------------
    // Accessors
    // ------------------------------------------------------------------

    /// Return the target data layout string.
    pub fn get_data_layout(&self) -> &str {
        &self.data_layout
    }

    /// Return the target triple string.
    pub fn get_target_triple(&self) -> &str {
        &self.triple
    }

    /// Return the CPU name.
    pub fn get_cpu(&self) -> &str {
        &self.cpu
    }

    /// Return the feature string.
    pub fn get_features(&self) -> &str {
        &self.features
    }

    /// Returns true if this is a 64-bit RISC-V target.
    pub fn is_64bit(&self) -> bool {
        self.is_64bit
    }

    /// Returns the current optimisation level.
    pub fn get_opt_level(&self) -> OptimizationLevel {
        self.opt_level
    }

    /// Returns the relocation model.
    pub fn get_reloc_model(&self) -> RelocModel {
        self.reloc_model
    }

    /// Returns the code model.
    pub fn get_code_model(&self) -> CodeModel {
        self.code_model
    }

    /// Returns true if position-independent code is required.
    pub fn is_pic(&self) -> bool {
        matches!(self.reloc_model, RelocModel::PIC)
    }

    /// Return true if compressed instructions should be emitted.
    pub fn enable_compressed(&self) -> bool {
        self.features.contains("+c") || self.features.contains("+zca")
    }

    // ------------------------------------------------------------------
    // Pass pipeline configuration
    // ------------------------------------------------------------------

    /// Returns the list of analysis passes that should run before codegen.
    /// These passes gather information used by later transformations.
    pub fn add_analysis_passes(&self) -> Vec<String> {
        let mut passes = Vec::new();

        // Always run: target IR analysis, dominator tree.
        passes.push("target-ir-analysis".to_string());
        passes.push("domtree".to_string());

        if self.opt_level.is_optimizing() {
            passes.push("loops".to_string());
            passes.push("scalar-evolution".to_string());
            passes.push("branch-prob".to_string());
            passes.push("block-freq".to_string());
            passes.push("target-lib".to_string());
            passes.push("stack-safety".to_string());
        }

        if self.opt_level.is_aggressive() {
            passes.push("alias-analysis".to_string());
            passes.push("memory-ssa".to_string());
            passes.push("demanded-bits".to_string());
            passes.push("assumption-cache".to_string());
        }

        passes
    }

    /// Returns the list of IR-level transformation passes.
    /// These operate on LLVM IR before instruction selection.
    pub fn add_ir_passes(&self) -> Vec<String> {
        let mut passes = Vec::new();

        // At O0: minimal passes for correctness
        if !self.opt_level.is_optimizing() {
            passes.push("mem2reg".to_string()); // Promote allocas to registers
            passes.push("simplifycfg".to_string()); // Clean up trivial branches
            passes.push("lower-expect".to_string());
            passes.push("inline".to_string()); // Always inline alwaysinline
            passes.push("sroa".to_string());
            return passes;
        }

        // O1 and above
        passes.push("inline".to_string());
        passes.push("mem2reg".to_string());
        passes.push("simplifycfg".to_string());
        passes.push("early-cse".to_string());
        passes.push("instcombine".to_string());
        passes.push("reassociate".to_string());
        passes.push("licm".to_string());
        passes.push("gvn".to_string());
        passes.push("sccp".to_string());
        passes.push("sroa".to_string());
        passes.push("deadargelim".to_string());
        passes.push("correlated-propagation".to_string());
        passes.push("aggressive-instcombine".to_string());
        passes.push("loop-simplify".to_string());
        passes.push("indvars".to_string());

        if self.opt_level.is_size_optimized() {
            passes.push("merge-functions".to_string());
            passes.push("alignment-from-assumptions".to_string());
        }

        // O2: additional passes
        if matches!(
            self.opt_level,
            OptimizationLevel::O2 | OptimizationLevel::O3
        ) {
            passes.push("jump-threading".to_string());
            passes.push("slp-vectorizer".to_string());
            passes.push("loop-unroll".to_string());
            passes.push("tailcallelim".to_string());
            passes.push("dse".to_string()); // Dead store elimination
        }

        // O3: aggressive
        if self.opt_level.is_aggressive() {
            passes.push("loop-vectorize".to_string());
            passes.push("slp-vectorizer".to_string());
            passes.push("global-merge".to_string());
            passes.push("argpromotion".to_string());
            passes.push("ipsccp".to_string());
        }

        passes
    }

    /// Returns the list of instruction selection passes.
    /// These convert LLVM IR to target-specific machine instructions.
    pub fn add_isel_passes(&self) -> Vec<String> {
        let mut passes = Vec::new();

        passes.push("expand-isel-pseudos".to_string());

        if self.opt_level.is_optimizing() {
            passes.push("dag-combine".to_string());
            passes.push("legalize-dag".to_string());
        }

        passes.push("select".to_string());
        passes.push("localstackalloc".to_string());

        passes
    }

    /// Returns the list of machine-level passes that run after
    /// instruction selection and before assembly emission.
    pub fn add_machine_passes(&self) -> Vec<String> {
        let mut passes = Vec::new();

        // Frame setup: prologue/epilogue insertion
        passes.push("prolog-epilog-insertion".to_string());

        // Register allocation
        passes.push("regalloc".to_string());

        // Post-RA passes
        passes.push("peephole-opt".to_string());

        if self.opt_level.is_optimizing() {
            passes.push("machine-licm".to_string());
            passes.push("machine-cse".to_string());
            passes.push("machine-sink".to_string());
            passes.push("machine-block-placement".to_string());
        }

        if self.opt_level.is_aggressive() {
            passes.push("machine-combiner".to_string());
            passes.push("postrapseudos".to_string());
        }

        // If size-optimised, enable machine outliner
        if self.opt_level.is_size_optimized() {
            passes.push("machine-outliner".to_string());
        }

        passes.push("expand-post-rapseudos".to_string());
        passes.push("branch-folder".to_string());

        passes
    }

    // ------------------------------------------------------------------
    // Code emission
    // ------------------------------------------------------------------

    /// Emit assembly text for the given module using the RISC-V
    /// assembly printer and return the assembly source string.
    ///
    /// This method orchestrates the full compilation pipeline for
    /// each function in the module: instruction selection, frame
    /// lowering, register allocation, and assembly printing.
    pub fn emit_assembly(&self, module: &Module) -> String {
        let mut output = String::new();

        // Emit module-level directives
        output.push_str(&format!(
            "\t.attribute\t4, {}\n",
            if self.is_64bit { 5 } else { 4 }
        ));
        output.push_str(&format!(
            "\t.attribute\t5, \"rv{}i2p1_{}\"\n",
            if self.is_64bit { 64 } else { 32 },
            self.features
                .replace(',', "_")
                .replace('+', "")
                .replace('-', "no"),
        ));

        for func_ref in &module.functions {
            let func = func_ref.borrow();
            let mf_name = if func.name.is_empty() {
                format!(".Lfunc{}", func.vid)
            } else {
                func.name.clone()
            };

            output.push_str("\t.text\n");
            output.push_str(&format!("\t.globl\t{}\n", mf_name));
            output.push_str(&format!("\t.type\t{}, @function\n", mf_name));
            output.push_str(&format!("{}:\n", mf_name));
            // Placeholder for function body; the actual codegen will
            // fill this via the instruction selector and asm printer.
            output.push_str(&format!("\t.size\t{}, .-{}\n\n", mf_name, mf_name));
        }

        output
    }

    /// Emit object file for the given module.
    /// Currently a placeholder; returns empty bytes for now.
    pub fn emit_object(&self, _module: &Module) -> Vec<u8> {
        // Object emission would use MC layer encoders.
        // For now, return empty.
        Vec::new()
    }

    // ------------------------------------------------------------------
    // Descriptor
    // ------------------------------------------------------------------

    /// Return a human-readable summary of this target machine.
    pub fn describe(&self) -> String {
        format!(
            "RiscVTargetMachine {{ triple: \"{}\", cpu: \"{}\", features: \"{}\", \
             is_64bit: {}, opt: {}, reloc: {}, code: {} }}",
            self.triple,
            self.cpu,
            self.features,
            self.is_64bit,
            self.opt_level,
            self.reloc_model,
            self.code_model,
        )
    }
}

// ---------------------------------------------------------------------------
// Tests
// ---------------------------------------------------------------------------

#[cfg(test)]
mod tests {
    use super::*;

    // ------------------------------------------------------------------
    // Construction tests
    // ------------------------------------------------------------------

    #[test]
    fn test_construct_rv64_target_machine() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "+m,+a,+f,+d,+c");
        assert!(tm.is_64bit());
        assert_eq!(tm.get_target_triple(), "riscv64-unknown-elf");
        assert_eq!(tm.get_cpu(), "generic-rv64");
        assert_eq!(tm.get_features(), "+m,+a,+f,+d,+c");
        assert_eq!(tm.get_data_layout(), DEFAULT_RV64_DATA_LAYOUT);
    }

    #[test]
    fn test_construct_rv32_target_machine() {
        let tm = RiscVTargetMachine::new("riscv32-unknown-elf", "generic-rv32", "+m,+a,+c");
        assert!(!tm.is_64bit());
        assert_eq!(tm.get_target_triple(), "riscv32-unknown-elf");
        assert_eq!(tm.get_data_layout(), DEFAULT_RV32_DATA_LAYOUT);
    }

    #[test]
    fn test_construct_with_linux_triple() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-linux-gnu", "generic-rv64", "");
        assert!(tm.is_64bit());
        assert_eq!(tm.get_target_triple(), "riscv64-unknown-linux-gnu");
    }

    #[test]
    fn test_detect_64bit_case_insensitive() {
        // Should detect "riscv64" even with mixed case
        let tm = RiscVTargetMachine::new("RISCV64-unknown-elf", "generic-rv64", "");
        assert!(tm.is_64bit());
    }

    #[test]
    fn test_construct_rv32_defaults_to_32bit() {
        let tm = RiscVTargetMachine::new("riscv32-unknown-unknown", "generic-rv32", "");
        assert!(!tm.is_64bit());
    }

    // ------------------------------------------------------------------
    // Builder tests
    // ------------------------------------------------------------------

    #[test]
    fn test_with_opt_level() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_opt_level(OptimizationLevel::O3);
        assert_eq!(tm.get_opt_level(), OptimizationLevel::O3);
        assert!(tm.get_opt_level().is_aggressive());
    }

    #[test]
    fn test_with_reloc_model() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_reloc_model(RelocModel::PIC);
        assert!(tm.is_pic());
    }

    #[test]
    fn test_with_code_model() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_code_model(CodeModel::Medium);
        assert_eq!(tm.get_code_model(), CodeModel::Medium);
    }

    // ------------------------------------------------------------------
    // Data layout tests
    // ------------------------------------------------------------------

    #[test]
    fn test_data_layout_rv64() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "");
        let dl = tm.get_data_layout();
        assert!(dl.contains("p:64:64"), "RV64 should have 64-bit pointers");
        assert!(dl.contains("S128"), "Stack aligned to 128 bits");
        assert!(dl.starts_with("e-m:e"), "Little-endian ELF mangling");
    }

    #[test]
    fn test_data_layout_rv32() {
        let tm = RiscVTargetMachine::new("riscv32-unknown-elf", "generic-rv32", "");
        let dl = tm.get_data_layout();
        assert!(dl.contains("p:32:32"), "RV32 should have 32-bit pointers");
        assert!(dl.starts_with("e-m:e"), "Little-endian ELF mangling");
    }

    // ------------------------------------------------------------------
    // Pass pipeline tests
    // ------------------------------------------------------------------

    #[test]
    fn test_analysis_passes_o0() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_opt_level(OptimizationLevel::O0);
        let passes = tm.add_analysis_passes();
        // O0: minimal analysis passes
        assert!(passes.contains(&"target-ir-analysis".to_string()));
        assert!(passes.contains(&"domtree".to_string()));
        // Should NOT have aggressive passes
        assert!(!passes.contains(&"alias-analysis".to_string()));
    }

    #[test]
    fn test_analysis_passes_o3() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_opt_level(OptimizationLevel::O3);
        let passes = tm.add_analysis_passes();
        assert!(passes.contains(&"alias-analysis".to_string()));
        assert!(passes.contains(&"memory-ssa".to_string()));
    }

    #[test]
    fn test_ir_passes_o0_minimal() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_opt_level(OptimizationLevel::O0);
        let passes = tm.add_ir_passes();
        // O0 should be minimal
        assert!(passes.contains(&"mem2reg".to_string()));
        assert!(!passes.contains(&"gvn".to_string()));
        assert!(!passes.contains(&"licm".to_string()));
    }

    #[test]
    fn test_ir_passes_o2_has_gvn() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_opt_level(OptimizationLevel::O2);
        let passes = tm.add_ir_passes();
        assert!(passes.contains(&"gvn".to_string()));
        assert!(passes.contains(&"licm".to_string()));
        assert!(passes.contains(&"jump-threading".to_string()));
    }

    #[test]
    fn test_ir_passes_o3_has_vectorize() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_opt_level(OptimizationLevel::O3);
        let passes = tm.add_ir_passes();
        assert!(passes.contains(&"loop-vectorize".to_string()));
    }

    #[test]
    fn test_ir_passes_os_favors_size() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_opt_level(OptimizationLevel::Os);
        let passes = tm.add_ir_passes();
        assert!(passes.contains(&"merge-functions".to_string()));
    }

    #[test]
    fn test_isel_passes() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "");
        let passes = tm.add_isel_passes();
        assert!(passes.iter().any(|p| p == "select"));
    }

    #[test]
    fn test_machine_passes_o0() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_opt_level(OptimizationLevel::O0);
        let passes = tm.add_machine_passes();
        assert!(passes.contains(&"regalloc".to_string()));
        // O0 should not have aggressive machine passes
        assert!(!passes.contains(&"machine-outliner".to_string()));
    }

    #[test]
    fn test_machine_passes_oz() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "")
            .with_opt_level(OptimizationLevel::Oz);
        let passes = tm.add_machine_passes();
        assert!(passes.contains(&"machine-outliner".to_string()));
    }

    #[test]
    fn test_describe() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "+m,+c");
        let desc = tm.describe();
        assert!(desc.contains("riscv64-unknown-elf"));
        assert!(desc.contains("generic-rv64"));
        assert!(desc.contains("+m,+c"));
    }

    #[test]
    fn test_enable_compressed() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "+m,+a,+c");
        assert!(tm.enable_compressed());
        let tm_no_c = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "+m,+a");
        assert!(!tm_no_c.enable_compressed());
    }

    #[test]
    fn test_emit_assembly_returns_non_empty() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "");
        let module = Module::new("test");
        let asm = tm.emit_assembly(&module);
        // Even with no functions, the module-level directives appear
        assert!(!asm.is_empty() || module.functions.is_empty());
    }

    #[test]
    fn test_emit_object_returns_bytes() {
        let tm = RiscVTargetMachine::new("riscv64-unknown-elf", "generic-rv64", "");
        let module = Module::new("test");
        let obj = tm.emit_object(&module);
        assert!(obj.is_empty()); // Currently placeholder
    }

    #[test]
    fn test_optimization_level_display() {
        assert_eq!(format!("{}", OptimizationLevel::O0), "O0");
        assert_eq!(format!("{}", OptimizationLevel::O3), "O3");
        assert_eq!(format!("{}", OptimizationLevel::Os), "Os");
        assert_eq!(format!("{}", OptimizationLevel::Oz), "Oz");
    }

    #[test]
    fn test_optimization_level_is_optimizing() {
        assert!(!OptimizationLevel::O0.is_optimizing());
        assert!(OptimizationLevel::O1.is_optimizing());
        assert!(OptimizationLevel::O2.is_optimizing());
        assert!(OptimizationLevel::O3.is_optimizing());
        assert!(OptimizationLevel::Os.is_optimizing());
        assert!(OptimizationLevel::Oz.is_optimizing());
    }

    #[test]
    fn test_reloc_model_display() {
        assert_eq!(format!("{}", RelocModel::Static), "static");
        assert_eq!(format!("{}", RelocModel::PIC), "pic");
    }

    #[test]
    fn test_code_model_display() {
        assert_eq!(format!("{}", CodeModel::Small), "small");
        assert_eq!(format!("{}", CodeModel::Medium), "medium");
        assert_eq!(format!("{}", CodeModel::Large), "large");
    }
}