llvm-native-core 0.1.12

//! RISC-V Register Information — complete register definitions for
//! RV32 and RV64 integer and floating-point register files per the
//! RISC-V ISA Manual, Volume I: Unprivileged Architecture, and the
//! RISC-V ELF psABI specification.
//!
//! Register categories:
//! - RV64/RV32 General Purpose Registers: X0-X31 (64-bit on RV64, 32-bit on RV32)
//! - RV32F/RV64F/D Floating Point Registers: F0-F31 (32-bit for F, 64-bit for D)
//!
//! ABI names per the RISC-V psABI:
//!   zero | ra | sp | gp | tp | t0-t2 | s0/fp | s1 | a0-a7
//!   s2-s11 | t3-t6
//!
//! FP ABI names:
//!   ft0-ft7 | fs0-fs1 | fa0-fa7 | fs2-fs11 | ft8-ft11
//!
//! Clean-room reconstruction from the RISC-V ISA Manual and psABI.
//! Zero LLVM source code consultation.

// ============================================================================
// Register Identifiers — flat numbering scheme starting at 3000
// ============================================================================

/// All RISC-V physical register IDs are `u16` constants.
/// Integer registers use IDs 3000–3031.
/// Floating-point registers use IDs 3050–3081.

// ============================================================================
// RV64/RV32 Integer General Purpose Registers (3000–3031)
// ============================================================================

pub const X0: u16 = 3000;
pub const ZERO: u16 = 3000;
pub const X1: u16 = 3001;
pub const RA: u16 = 3001;
pub const X2: u16 = 3002;
pub const SP: u16 = 3002;
pub const X3: u16 = 3003;
pub const GP: u16 = 3003;
pub const X4: u16 = 3004;
pub const TP: u16 = 3004;
pub const X5: u16 = 3005;
pub const T0: u16 = 3005;
pub const X6: u16 = 3006;
pub const T1: u16 = 3006;
pub const X7: u16 = 3007;
pub const T2: u16 = 3007;
pub const X8: u16 = 3008;
pub const S0: u16 = 3008;
pub const FP: u16 = 3008;
pub const X9: u16 = 3009;
pub const S1: u16 = 3009;
pub const X10: u16 = 3010;
pub const A0: u16 = 3010;
pub const X11: u16 = 3011;
pub const A1: u16 = 3011;
pub const X12: u16 = 3012;
pub const A2: u16 = 3012;
pub const X13: u16 = 3013;
pub const A3: u16 = 3013;
pub const X14: u16 = 3014;
pub const A4: u16 = 3014;
pub const X15: u16 = 3015;
pub const A5: u16 = 3015;
pub const X16: u16 = 3016;
pub const A6: u16 = 3016;
pub const X17: u16 = 3017;
pub const A7: u16 = 3017;
pub const X18: u16 = 3018;
pub const S2: u16 = 3018;
pub const X19: u16 = 3019;
pub const S3: u16 = 3019;
pub const X20: u16 = 3020;
pub const S4: u16 = 3020;
pub const X21: u16 = 3021;
pub const S5: u16 = 3021;
pub const X22: u16 = 3022;
pub const S6: u16 = 3022;
pub const X23: u16 = 3023;
pub const S7: u16 = 3023;
pub const X24: u16 = 3024;
pub const S8: u16 = 3024;
pub const X25: u16 = 3025;
pub const S9: u16 = 3025;
pub const X26: u16 = 3026;
pub const S10: u16 = 3026;
pub const X27: u16 = 3027;
pub const S11: u16 = 3027;
pub const X28: u16 = 3028;
pub const T3: u16 = 3028;
pub const X29: u16 = 3029;
pub const T4: u16 = 3029;
pub const X30: u16 = 3030;
pub const T5: u16 = 3030;
pub const X31: u16 = 3031;
pub const T6: u16 = 3031;

// ============================================================================
// RV32F/RV64F/D Floating-Point Registers (3050–3081)
// ============================================================================

pub const F0: u16 = 3050;
pub const FT0: u16 = 3050;
pub const F1: u16 = 3051;
pub const FT1: u16 = 3051;
pub const F2: u16 = 3052;
pub const FT2: u16 = 3052;
pub const F3: u16 = 3053;
pub const FT3: u16 = 3053;
pub const F4: u16 = 3054;
pub const FT4: u16 = 3054;
pub const F5: u16 = 3055;
pub const FT5: u16 = 3055;
pub const F6: u16 = 3056;
pub const FT6: u16 = 3056;
pub const F7: u16 = 3057;
pub const FT7: u16 = 3057;
pub const F8: u16 = 3058;
pub const FS0: u16 = 3058;
pub const F9: u16 = 3059;
pub const FS1: u16 = 3059;
pub const F10: u16 = 3060;
pub const FA0: u16 = 3060;
pub const F11: u16 = 3061;
pub const FA1: u16 = 3061;
pub const F12: u16 = 3062;
pub const FA2: u16 = 3062;
pub const F13: u16 = 3063;
pub const FA3: u16 = 3063;
pub const F14: u16 = 3064;
pub const FA4: u16 = 3064;
pub const F15: u16 = 3065;
pub const FA5: u16 = 3065;
pub const F16: u16 = 3066;
pub const FA6: u16 = 3066;
pub const F17: u16 = 3067;
pub const FA7: u16 = 3067;
pub const F18: u16 = 3068;
pub const FS2: u16 = 3068;
pub const F19: u16 = 3069;
pub const FS3: u16 = 3069;
pub const F20: u16 = 3070;
pub const FS4: u16 = 3070;
pub const F21: u16 = 3071;
pub const FS5: u16 = 3071;
pub const F22: u16 = 3072;
pub const FS6: u16 = 3072;
pub const F23: u16 = 3073;
pub const FS7: u16 = 3073;
pub const F24: u16 = 3074;
pub const FS8: u16 = 3074;
pub const F25: u16 = 3075;
pub const FS9: u16 = 3075;
pub const F26: u16 = 3076;
pub const FS10: u16 = 3076;
pub const F27: u16 = 3077;
pub const FS11: u16 = 3077;
pub const F28: u16 = 3078;
pub const FT8: u16 = 3078;
pub const F29: u16 = 3079;
pub const FT9: u16 = 3079;
pub const F30: u16 = 3080;
pub const FT10: u16 = 3080;
pub const F31: u16 = 3081;
pub const FT11: u16 = 3081;

// ============================================================================
// Register counts
// ============================================================================

/// Number of integer (GPR) registers in the RISC-V register file.
pub const RV_GPR_COUNT: usize = 32;

/// Number of floating-point registers in the RISC-V register file.
pub const RV_FPR_COUNT: usize = 32;

/// Maximum register ID used in this backend.
pub const RV_MAX_REG_ID: u16 = 3081;

/// Base ID for integer registers.
pub const GPR_BASE: u16 = 3000;

/// Base ID for floating-point registers.
pub const FPR_BASE: u16 = 3050;

// ============================================================================
// Register Class Enum
// ============================================================================

/// RISC-V register class.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum RiscVRegClass {
    /// General Purpose Register (integer, 32-bit or 64-bit).
    GPR,
    /// Floating-Point Register (32-bit, single precision).
    FPR32,
    /// Floating-Point Register (64-bit, double precision).
    FPR64,
}

impl std::fmt::Display for RiscVRegClass {
    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
        match self {
            RiscVRegClass::GPR => write!(f, "GPR"),
            RiscVRegClass::FPR32 => write!(f, "FPR32"),
            RiscVRegClass::FPR64 => write!(f, "FPR64"),
        }
    }
}

// ============================================================================
// RiscVRegisterInfo
// ============================================================================

/// RISC-V register information provider.
///
/// Provides assembly names, ABI names, register classes, widths,
/// DWARF numbers, and callee/caller-saved classification per the
/// RISC-V ISA Manual and psABI specification.
pub struct RiscVRegisterInfo;

impl RiscVRegisterInfo {
    /// Get the assembly name for a register.
    ///
    /// Integer registers return their architectural name (e.g., "x0", "ra").
    /// FP registers return "f0" through "f31".
    pub fn get_asm_name(reg_id: u16) -> &'static str {
        match reg_id {
            X0 => "zero",
            X1 => "ra",
            X2 => "sp",
            X3 => "gp",
            X4 => "tp",
            X5 => "t0",
            X6 => "t1",
            X7 => "t2",
            X8 => "s0",
            X9 => "s1",
            X10 => "a0",
            X11 => "a1",
            X12 => "a2",
            X13 => "a3",
            X14 => "a4",
            X15 => "a5",
            X16 => "a6",
            X17 => "a7",
            X18 => "s2",
            X19 => "s3",
            X20 => "s4",
            X21 => "s5",
            X22 => "s6",
            X23 => "s7",
            X24 => "s8",
            X25 => "s9",
            X26 => "s10",
            X27 => "s11",
            X28 => "t3",
            X29 => "t4",
            X30 => "t5",
            X31 => "t6",
            // FP registers
            F0 => "f0",
            F1 => "f1",
            F2 => "f2",
            F3 => "f3",
            F4 => "f4",
            F5 => "f5",
            F6 => "f6",
            F7 => "f7",
            F8 => "f8",
            F9 => "f9",
            F10 => "f10",
            F11 => "f11",
            F12 => "f12",
            F13 => "f13",
            F14 => "f14",
            F15 => "f15",
            F16 => "f16",
            F17 => "f17",
            F18 => "f18",
            F19 => "f19",
            F20 => "f20",
            F21 => "f21",
            F22 => "f22",
            F23 => "f23",
            F24 => "f24",
            F25 => "f25",
            F26 => "f26",
            F27 => "f27",
            F28 => "f28",
            F29 => "f29",
            F30 => "f30",
            F31 => "f31",
            _ => "?",
        }
    }

    /// Get the ABI name for a register.
    ///
    /// Returns the psABI name: zero, ra, sp, gp, tp, t0-t6, s0-s11, a0-a7
    /// for GPRs; ft0-ft11, fs0-fs11, fa0-fa7 for FPRs.
    pub fn get_abi_name(reg_id: u16) -> &'static str {
        match reg_id {
            X0 => "zero",
            X1 => "ra",
            X2 => "sp",
            X3 => "gp",
            X4 => "tp",
            X5 => "t0",
            X6 => "t1",
            X7 => "t2",
            X8 => "s0",
            X9 => "s1",
            X10 => "a0",
            X11 => "a1",
            X12 => "a2",
            X13 => "a3",
            X14 => "a4",
            X15 => "a5",
            X16 => "a6",
            X17 => "a7",
            X18 => "s2",
            X19 => "s3",
            X20 => "s4",
            X21 => "s5",
            X22 => "s6",
            X23 => "s7",
            X24 => "s8",
            X25 => "s9",
            X26 => "s10",
            X27 => "s11",
            X28 => "t3",
            X29 => "t4",
            X30 => "t5",
            X31 => "t6",
            // FP ABI names
            F0 => "ft0",
            F1 => "ft1",
            F2 => "ft2",
            F3 => "ft3",
            F4 => "ft4",
            F5 => "ft5",
            F6 => "ft6",
            F7 => "ft7",
            F8 => "fs0",
            F9 => "fs1",
            F10 => "fa0",
            F11 => "fa1",
            F12 => "fa2",
            F13 => "fa3",
            F14 => "fa4",
            F15 => "fa5",
            F16 => "fa6",
            F17 => "fa7",
            F18 => "fs2",
            F19 => "fs3",
            F20 => "fs4",
            F21 => "fs5",
            F22 => "fs6",
            F23 => "fs7",
            F24 => "fs8",
            F25 => "fs9",
            F26 => "fs10",
            F27 => "fs11",
            F28 => "ft8",
            F29 => "ft9",
            F30 => "ft10",
            F31 => "ft11",
            _ => "?",
        }
    }

    /// Get the register class for a register ID.
    pub fn get_reg_class(reg_id: u16) -> RiscVRegClass {
        match reg_id {
            3000..=3031 => RiscVRegClass::GPR,
            3050..=3081 => RiscVRegClass::FPR64,
            _ => RiscVRegClass::GPR,
        }
    }

    /// Get the register width in bits.
    ///
    /// For GPRs, returns 64 (on RV64) or 32 (on RV32) based on the `is_rv64` flag.
    /// Defaults to 64. For FPRs, returns 64 (double-precision capable) or 32 on request.
    pub fn get_reg_width(reg_id: u16, is_rv64: bool) -> u16 {
        match reg_id {
            3000..=3031 => {
                if is_rv64 {
                    64
                } else {
                    32
                }
            }
            3050..=3081 => 64, // FPRs are 64-bit on D-capable hardware; also usable as 32-bit
            _ => 64,
        }
    }

    /// Get the DWARF register number for the given register ID.
    ///
    /// Per the RISC-V DWARF specification:
    /// - x0–x31 map to DWARF numbers 0–31
    /// - f0–f31 map to DWARF numbers 32–63
    pub fn get_dwarf_num(reg_id: u16) -> i16 {
        match reg_id {
            3000..=3031 => (reg_id - 3000) as i16,
            3050..=3081 => (32 + (reg_id - 3050)) as i16,
            _ => -1,
        }
    }

    /// Returns true if the register is callee-saved per the psABI.
    ///
    /// Callee-saved integer registers: sp, s0-s11 (x2, x8-x9, x18-x27)
    /// Callee-saved FP registers: fs0-fs11 (f8-f9, f18-f27)
    pub fn is_callee_saved(reg_id: u16) -> bool {
        match reg_id {
            SP => true,
            X8 | S0 | FP => true,
            X9 | S1 => true,
            X18..=X27 => true, // s2–s11
            F8 | FS0 => true,
            F9 | FS1 => true,
            F18..=F27 => true, // fs2–fs11
            _ => false,
        }
    }

    /// Returns true if the register is caller-saved per the psABI.
    ///
    /// Caller-saved integer registers: ra, t0-t6, a0-a7 (x1, x5-x7, x10-x17, x28-x31)
    /// Caller-saved FP registers: ft0-ft11, fa0-fa7 (f0-f7, f10-f17, f28-f31)
    pub fn is_caller_saved(reg_id: u16) -> bool {
        match reg_id {
            X1 | RA => true,
            X5..=X7 => true,   // t0–t2
            X10..=X17 => true, // a0–a7
            X28..=X31 => true, // t3–t6
            F0..=F7 => true,   // ft0–ft7
            F10..=F17 => true, // fa0–fa7
            F28..=F31 => true, // ft8–ft11
            _ => false,
        }
    }

    /// Returns true if the register is reserved (cannot be allocated by the register allocator).
    ///
    /// Reserved registers: zero (x0), sp (x2), gp (x3), tp (x4)
    pub fn is_reserved(reg_id: u16) -> bool {
        matches!(reg_id, X0 | ZERO | X2 | SP | X3 | GP | X4 | TP)
    }

    /// Get the list of allocatable integer registers.
    ///
    /// Excludes: zero, sp, gp, tp, ra (treated separately), fp (used as frame pointer).
    /// Returns: x5-x7, x10-x17, x18-x27, x28-x31 (excluding x8/s0/fp when used as frame pointer).
    /// For register allocation, we make the full set available and let the allocator reserve sp/fp/gp/tp.
    pub fn get_allocatable_gprs() -> Vec<u16> {
        let mut regs = Vec::with_capacity(32);
        for id in 3000u16..=3031u16 {
            // Exclude reserved and special registers
            if !RiscVRegisterInfo::is_reserved(id) && id != RA {
                regs.push(id);
            }
        }
        regs
    }

    /// Get the list of allocatable floating-point registers.
    ///
    /// Returns all 32 FPRs (f0-f31). The register allocator handles
    /// callee/caller-saved conventions.
    pub fn get_allocatable_fprs() -> Vec<u16> {
        (3050u16..=3081u16).collect()
    }

    /// Get integer argument registers (a0-a7, per the psABI).
    pub fn get_argument_regs() -> Vec<u16> {
        vec![A0, A1, A2, A3, A4, A5, A6, A7]
    }

    /// Get floating-point argument registers (fa0-fa7).
    pub fn get_fp_argument_regs() -> Vec<u16> {
        vec![FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7]
    }

    /// Get integer return registers.
    ///
    /// For values up to XLEN bits: a0.
    /// For values up to 2×XLEN bits: a0, a1.
    pub fn get_return_regs() -> Vec<u16> {
        vec![A0, A1]
    }

    /// Get floating-point return registers (fa0, fa1 for complex double).
    pub fn get_fp_return_regs() -> Vec<u16> {
        vec![FA0, FA1]
    }

    /// Get the frame pointer register (s0/fp = x8).
    pub fn get_frame_pointer_reg() -> u16 {
        S0
    }

    /// Get the return address register (ra = x1).
    pub fn get_return_address_reg() -> u16 {
        RA
    }

    /// Get the stack pointer register (sp = x2).
    pub fn get_stack_pointer_reg() -> u16 {
        SP
    }

    /// Get the global pointer register (gp = x3).
    pub fn get_global_pointer_reg() -> u16 {
        GP
    }

    /// Get the thread pointer register (tp = x4).
    pub fn get_thread_pointer_reg() -> u16 {
        TP
    }

    /// Get the zero register (x0).
    pub fn get_zero_reg() -> u16 {
        ZERO
    }

    /// Check if a register ID belongs to the integer register file.
    pub fn is_gpr(reg_id: u16) -> bool {
        (3000..=3031).contains(&reg_id)
    }

    /// Check if a register ID belongs to the floating-point register file.
    pub fn is_fpr(reg_id: u16) -> bool {
        (3050..=3081).contains(&reg_id)
    }

    /// Get the register index (0–31) within its register class.
    pub fn get_reg_index(reg_id: u16) -> u8 {
        match reg_id {
            3000..=3031 => (reg_id - 3000) as u8,
            3050..=3081 => (reg_id - 3050) as u8,
            _ => 0,
        }
    }

    /// Convert an integer register to its xN name string.
    pub fn get_x_name(reg_id: u16) -> String {
        if RiscVRegisterInfo::is_gpr(reg_id) {
            format!("x{}", RiscVRegisterInfo::get_reg_index(reg_id))
        } else {
            "?".to_string()
        }
    }

    /// Convert an FP register to its fN name string.
    pub fn get_f_name(reg_id: u16) -> String {
        if RiscVRegisterInfo::is_fpr(reg_id) {
            format!("f{}", RiscVRegisterInfo::get_reg_index(reg_id))
        } else {
            "?".to_string()
        }
    }

    /// Check if the register can be used as a base register for memory addressing.
    ///
    /// All GPRs except x0/zero can be used as a base register.
    pub fn can_be_base_reg(reg_id: u16) -> bool {
        RiscVRegisterInfo::is_gpr(reg_id) && reg_id != ZERO
    }

    /// Get all caller-saved GPRs (used for register allocation).
    pub fn get_caller_saved_gprs() -> Vec<u16> {
        vec![
            RA, // x1
            T0, T1, T2, // x5-x7
            A0, A1, A2, A3, A4, A5, A6, A7, // x10-x17
            T3, T4, T5, T6, // x28-x31
        ]
    }

    /// Get all callee-saved GPRs (used for register allocation).
    pub fn get_callee_saved_gprs() -> Vec<u16> {
        vec![
            SP, // x2
            S0, S1, // x8-x9
            S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, // x18-x27
        ]
    }

    /// Get all caller-saved FPRs.
    pub fn get_caller_saved_fprs() -> Vec<u16> {
        vec![
            FT0, FT1, FT2, FT3, FT4, FT5, FT6, FT7, // f0-f7
            FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7, // f10-f17
            FT8, FT9, FT10, FT11, // f28-f31
        ]
    }

    /// Get all callee-saved FPRs.
    pub fn get_callee_saved_fprs() -> Vec<u16> {
        vec![
            FS0, FS1, // f8-f9
            FS2, FS3, FS4, FS5, FS6, FS7, FS8, FS9, FS10, FS11, // f18-f27
        ]
    }
}

// ============================================================================
// Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_register_count_constants() {
        assert_eq!(RV_GPR_COUNT, 32);
        assert_eq!(RV_FPR_COUNT, 32);
        assert_eq!(RV_MAX_REG_ID, 3081);
        assert_eq!(GPR_BASE, 3000);
        assert_eq!(FPR_BASE, 3050);
    }

    #[test]
    fn test_register_ids_unique() {
        // All GPR consts should be unique within 3000-3031
        let gpr_ids = [
            X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18,
            X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31,
        ];
        let mut sorted: Vec<u16> = gpr_ids.to_vec();
        sorted.sort_unstable();
        sorted.dedup();
        assert_eq!(sorted.len(), 32);

        // All FPR consts should be unique within 3050-3081
        let fpr_ids = [
            F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18,
            F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31,
        ];
        let mut sorted_fpr: Vec<u16> = fpr_ids.to_vec();
        sorted_fpr.sort_unstable();
        sorted_fpr.dedup();
        assert_eq!(sorted_fpr.len(), 32);
    }

    #[test]
    fn test_abi_name_aliases() {
        // Aliases should resolve to the same IDs
        assert_eq!(ZERO, X0);
        assert_eq!(RA, X1);
        assert_eq!(SP, X2);
        assert_eq!(GP, X3);
        assert_eq!(TP, X4);
        assert_eq!(T0, X5);
        assert_eq!(T1, X6);
        assert_eq!(T2, X7);
        assert_eq!(S0, X8);
        assert_eq!(FP, X8);
        assert_eq!(S1, X9);
        assert_eq!(A0, X10);
        assert_eq!(A1, X11);
        assert_eq!(A2, X12);
        assert_eq!(A3, X13);
        assert_eq!(A4, X14);
        assert_eq!(A5, X15);
        assert_eq!(A6, X16);
        assert_eq!(A7, X17);
        assert_eq!(S2, X18);
        assert_eq!(S3, X19);
        assert_eq!(S4, X20);
        assert_eq!(S5, X21);
        assert_eq!(S6, X22);
        assert_eq!(S7, X23);
        assert_eq!(S8, X24);
        assert_eq!(S9, X25);
        assert_eq!(S10, X26);
        assert_eq!(S11, X27);
        assert_eq!(T3, X28);
        assert_eq!(T4, X29);
        assert_eq!(T5, X30);
        assert_eq!(T6, X31);
    }

    #[test]
    fn test_fpr_name_aliases() {
        assert_eq!(FT0, F0);
        assert_eq!(FT1, F1);
        assert_eq!(FT2, F2);
        assert_eq!(FT3, F3);
        assert_eq!(FT4, F4);
        assert_eq!(FT5, F5);
        assert_eq!(FT6, F6);
        assert_eq!(FT7, F7);
        assert_eq!(FS0, F8);
        assert_eq!(FS1, F9);
        assert_eq!(FA0, F10);
        assert_eq!(FA1, F11);
        assert_eq!(FA2, F12);
        assert_eq!(FA3, F13);
        assert_eq!(FA4, F14);
        assert_eq!(FA5, F15);
        assert_eq!(FA6, F16);
        assert_eq!(FA7, F17);
        assert_eq!(FS2, F18);
        assert_eq!(FS3, F19);
        assert_eq!(FS4, F20);
        assert_eq!(FS5, F21);
        assert_eq!(FS6, F22);
        assert_eq!(FS7, F23);
        assert_eq!(FS8, F24);
        assert_eq!(FS9, F25);
        assert_eq!(FS10, F26);
        assert_eq!(FS11, F27);
        assert_eq!(FT8, F28);
        assert_eq!(FT9, F29);
        assert_eq!(FT10, F30);
        assert_eq!(FT11, F31);
    }

    #[test]
    fn test_get_asm_name() {
        assert_eq!(RiscVRegisterInfo::get_asm_name(X0), "zero");
        assert_eq!(RiscVRegisterInfo::get_asm_name(RA), "ra");
        assert_eq!(RiscVRegisterInfo::get_asm_name(SP), "sp");
        assert_eq!(RiscVRegisterInfo::get_asm_name(GP), "gp");
        assert_eq!(RiscVRegisterInfo::get_asm_name(TP), "tp");
        assert_eq!(RiscVRegisterInfo::get_asm_name(T0), "t0");
        assert_eq!(RiscVRegisterInfo::get_asm_name(S0), "s0");
        assert_eq!(RiscVRegisterInfo::get_asm_name(A0), "a0");
        assert_eq!(RiscVRegisterInfo::get_asm_name(A7), "a7");
        assert_eq!(RiscVRegisterInfo::get_asm_name(T6), "t6");
        assert_eq!(RiscVRegisterInfo::get_asm_name(F0), "f0");
        assert_eq!(RiscVRegisterInfo::get_asm_name(F31), "f31");
        assert_eq!(RiscVRegisterInfo::get_asm_name(9999), "?");
    }

    #[test]
    fn test_get_abi_name() {
        assert_eq!(RiscVRegisterInfo::get_abi_name(X0), "zero");
        assert_eq!(RiscVRegisterInfo::get_abi_name(RA), "ra");
        assert_eq!(RiscVRegisterInfo::get_abi_name(SP), "sp");
        assert_eq!(RiscVRegisterInfo::get_abi_name(T0), "t0");
        assert_eq!(RiscVRegisterInfo::get_abi_name(S0), "s0");
        assert_eq!(RiscVRegisterInfo::get_abi_name(A0), "a0");
        assert_eq!(RiscVRegisterInfo::get_abi_name(FT0), "ft0");
        assert_eq!(RiscVRegisterInfo::get_abi_name(FS0), "fs0");
        assert_eq!(RiscVRegisterInfo::get_abi_name(FA0), "fa0");
        assert_eq!(RiscVRegisterInfo::get_abi_name(FT11), "ft11");
    }

    #[test]
    fn test_get_reg_class() {
        assert_eq!(RiscVRegisterInfo::get_reg_class(X0), RiscVRegClass::GPR);
        assert_eq!(RiscVRegisterInfo::get_reg_class(X31), RiscVRegClass::GPR);
        assert_eq!(RiscVRegisterInfo::get_reg_class(A0), RiscVRegClass::GPR);
        assert_eq!(RiscVRegisterInfo::get_reg_class(SP), RiscVRegClass::GPR);
        assert_eq!(RiscVRegisterInfo::get_reg_class(F0), RiscVRegClass::FPR64);
        assert_eq!(RiscVRegisterInfo::get_reg_class(F31), RiscVRegClass::FPR64);
    }

    #[test]
    fn test_get_reg_width() {
        // RV64
        assert_eq!(RiscVRegisterInfo::get_reg_width(X0, true), 64);
        assert_eq!(RiscVRegisterInfo::get_reg_width(A0, true), 64);
        // RV32
        assert_eq!(RiscVRegisterInfo::get_reg_width(X0, false), 32);
        assert_eq!(RiscVRegisterInfo::get_reg_width(A1, false), 32);
        // FPRs
        assert_eq!(RiscVRegisterInfo::get_reg_width(F0, true), 64);
        assert_eq!(RiscVRegisterInfo::get_reg_width(F31, false), 64);
    }

    #[test]
    fn test_get_dwarf_num() {
        // Integer DWARF numbers: x0→0, x1→1, ..., x31→31
        assert_eq!(RiscVRegisterInfo::get_dwarf_num(X0), 0);
        assert_eq!(RiscVRegisterInfo::get_dwarf_num(X1), 1);
        assert_eq!(RiscVRegisterInfo::get_dwarf_num(X31), 31);
        // FP DWARF numbers: f0→32, f1→33, ..., f31→63
        assert_eq!(RiscVRegisterInfo::get_dwarf_num(F0), 32);
        assert_eq!(RiscVRegisterInfo::get_dwarf_num(F1), 33);
        assert_eq!(RiscVRegisterInfo::get_dwarf_num(F31), 63);
        // Unknown
        assert_eq!(RiscVRegisterInfo::get_dwarf_num(9999), -1);
    }

    #[test]
    fn test_is_callee_saved() {
        // Callee-saved integer
        assert!(RiscVRegisterInfo::is_callee_saved(SP));
        assert!(RiscVRegisterInfo::is_callee_saved(S0));
        assert!(RiscVRegisterInfo::is_callee_saved(FP));
        assert!(RiscVRegisterInfo::is_callee_saved(S1));
        assert!(RiscVRegisterInfo::is_callee_saved(S2));
        assert!(RiscVRegisterInfo::is_callee_saved(S11));
        // Callee-saved FP
        assert!(RiscVRegisterInfo::is_callee_saved(FS0));
        assert!(RiscVRegisterInfo::is_callee_saved(FS1));
        assert!(RiscVRegisterInfo::is_callee_saved(FS2));
        assert!(RiscVRegisterInfo::is_callee_saved(FS11));
        // Not callee-saved
        assert!(!RiscVRegisterInfo::is_callee_saved(X0));
        assert!(!RiscVRegisterInfo::is_callee_saved(RA));
        assert!(!RiscVRegisterInfo::is_callee_saved(A0));
        assert!(!RiscVRegisterInfo::is_callee_saved(T0));
        assert!(!RiscVRegisterInfo::is_callee_saved(FT0));
        assert!(!RiscVRegisterInfo::is_callee_saved(FA0));
    }

    #[test]
    fn test_is_caller_saved() {
        // Caller-saved integer
        assert!(RiscVRegisterInfo::is_caller_saved(RA));
        assert!(RiscVRegisterInfo::is_caller_saved(T0));
        assert!(RiscVRegisterInfo::is_caller_saved(T2));
        assert!(RiscVRegisterInfo::is_caller_saved(A0));
        assert!(RiscVRegisterInfo::is_caller_saved(A7));
        assert!(RiscVRegisterInfo::is_caller_saved(T3));
        assert!(RiscVRegisterInfo::is_caller_saved(T6));
        // Caller-saved FP
        assert!(RiscVRegisterInfo::is_caller_saved(FT0));
        assert!(RiscVRegisterInfo::is_caller_saved(FT7));
        assert!(RiscVRegisterInfo::is_caller_saved(FA0));
        assert!(RiscVRegisterInfo::is_caller_saved(FA7));
        assert!(RiscVRegisterInfo::is_caller_saved(FT8));
        assert!(RiscVRegisterInfo::is_caller_saved(FT11));
        // Not caller-saved
        assert!(!RiscVRegisterInfo::is_caller_saved(SP));
        assert!(!RiscVRegisterInfo::is_caller_saved(S0));
        assert!(!RiscVRegisterInfo::is_caller_saved(FS0));
        assert!(!RiscVRegisterInfo::is_caller_saved(X0));
    }

    #[test]
    fn test_is_reserved() {
        assert!(RiscVRegisterInfo::is_reserved(ZERO));
        assert!(RiscVRegisterInfo::is_reserved(SP));
        assert!(RiscVRegisterInfo::is_reserved(GP));
        assert!(RiscVRegisterInfo::is_reserved(TP));
        // Not reserved
        assert!(!RiscVRegisterInfo::is_reserved(RA));
        assert!(!RiscVRegisterInfo::is_reserved(A0));
        assert!(!RiscVRegisterInfo::is_reserved(T0));
        assert!(!RiscVRegisterInfo::is_reserved(F0));
    }

    #[test]
    fn test_get_allocatable_gprs() {
        let gprs = RiscVRegisterInfo::get_allocatable_gprs();
        // Should not contain reserved registers
        assert!(!gprs.contains(&ZERO));
        assert!(!gprs.contains(&SP));
        assert!(!gprs.contains(&GP));
        assert!(!gprs.contains(&TP));
        // Should not contain RA (handled separately)
        assert!(!gprs.contains(&RA));
        // Should contain argument and temporary registers
        assert!(gprs.contains(&A0));
        assert!(gprs.contains(&T0));
        assert!(gprs.contains(&S0));
    }

    #[test]
    fn test_get_allocatable_fprs() {
        let fprs = RiscVRegisterInfo::get_allocatable_fprs();
        assert_eq!(fprs.len(), 32);
        assert!(fprs.contains(&F0));
        assert!(fprs.contains(&F31));
    }

    #[test]
    fn test_get_argument_regs() {
        let arg_regs = RiscVRegisterInfo::get_argument_regs();
        assert_eq!(arg_regs.len(), 8);
        assert_eq!(arg_regs[0], A0);
        assert_eq!(arg_regs[7], A7);
    }

    #[test]
    fn test_get_fp_argument_regs() {
        let fp_arg_regs = RiscVRegisterInfo::get_fp_argument_regs();
        assert_eq!(fp_arg_regs.len(), 8);
        assert_eq!(fp_arg_regs[0], FA0);
        assert_eq!(fp_arg_regs[7], FA7);
    }

    #[test]
    fn test_get_return_regs() {
        let ret_regs = RiscVRegisterInfo::get_return_regs();
        assert_eq!(ret_regs.len(), 2);
        assert_eq!(ret_regs[0], A0);
        assert_eq!(ret_regs[1], A1);
    }

    #[test]
    fn test_get_fp_return_regs() {
        let fp_ret_regs = RiscVRegisterInfo::get_fp_return_regs();
        assert_eq!(fp_ret_regs.len(), 2);
        assert_eq!(fp_ret_regs[0], FA0);
        assert_eq!(fp_ret_regs[1], FA1);
    }

    #[test]
    fn test_special_regs() {
        assert_eq!(RiscVRegisterInfo::get_frame_pointer_reg(), S0);
        assert_eq!(RiscVRegisterInfo::get_return_address_reg(), RA);
        assert_eq!(RiscVRegisterInfo::get_stack_pointer_reg(), SP);
        assert_eq!(RiscVRegisterInfo::get_global_pointer_reg(), GP);
        assert_eq!(RiscVRegisterInfo::get_thread_pointer_reg(), TP);
        assert_eq!(RiscVRegisterInfo::get_zero_reg(), ZERO);
    }

    #[test]
    fn test_is_gpr_and_fpr() {
        assert!(RiscVRegisterInfo::is_gpr(X0));
        assert!(RiscVRegisterInfo::is_gpr(X31));
        assert!(!RiscVRegisterInfo::is_gpr(F0));

        assert!(RiscVRegisterInfo::is_fpr(F0));
        assert!(RiscVRegisterInfo::is_fpr(F31));
        assert!(!RiscVRegisterInfo::is_fpr(X0));
    }

    #[test]
    fn test_get_reg_index() {
        assert_eq!(RiscVRegisterInfo::get_reg_index(X0), 0);
        assert_eq!(RiscVRegisterInfo::get_reg_index(X31), 31);
        assert_eq!(RiscVRegisterInfo::get_reg_index(A0), 10);
        assert_eq!(RiscVRegisterInfo::get_reg_index(F0), 0);
        assert_eq!(RiscVRegisterInfo::get_reg_index(F31), 31);
    }

    #[test]
    fn test_get_x_name() {
        assert_eq!(RiscVRegisterInfo::get_x_name(X0), "x0");
        assert_eq!(RiscVRegisterInfo::get_x_name(X10), "x10");
        assert_eq!(RiscVRegisterInfo::get_x_name(X31), "x31");
        assert_eq!(RiscVRegisterInfo::get_x_name(SP), "x2");
        assert_eq!(RiscVRegisterInfo::get_x_name(F0), "?");
    }

    #[test]
    fn test_get_f_name() {
        assert_eq!(RiscVRegisterInfo::get_f_name(F0), "f0");
        assert_eq!(RiscVRegisterInfo::get_f_name(F15), "f15");
        assert_eq!(RiscVRegisterInfo::get_f_name(F31), "f31");
        assert_eq!(RiscVRegisterInfo::get_f_name(X0), "?");
    }

    #[test]
    fn test_can_be_base_reg() {
        assert!(!RiscVRegisterInfo::can_be_base_reg(X0));
        assert!(!RiscVRegisterInfo::can_be_base_reg(ZERO));
        assert!(RiscVRegisterInfo::can_be_base_reg(X1));
        assert!(RiscVRegisterInfo::can_be_base_reg(SP));
        assert!(RiscVRegisterInfo::can_be_base_reg(A0));
        assert!(!RiscVRegisterInfo::can_be_base_reg(F0));
    }

    #[test]
    fn test_reg_class_display() {
        assert_eq!(format!("{}", RiscVRegClass::GPR), "GPR");
        assert_eq!(format!("{}", RiscVRegClass::FPR32), "FPR32");
        assert_eq!(format!("{}", RiscVRegClass::FPR64), "FPR64");
    }

    #[test]
    fn test_caller_saved_gprs_count() {
        let regs = RiscVRegisterInfo::get_caller_saved_gprs();
        // ra + t0-t2 + a0-a7 + t3-t6 = 1 + 3 + 8 + 4 = 16
        assert_eq!(regs.len(), 16);
    }

    #[test]
    fn test_callee_saved_gprs_count() {
        let regs = RiscVRegisterInfo::get_callee_saved_gprs();
        // sp + s0-s1 + s2-s11 = 1 + 2 + 10 = 13
        assert_eq!(regs.len(), 13);
    }

    #[test]
    fn test_caller_saved_fprs_count() {
        let regs = RiscVRegisterInfo::get_caller_saved_fprs();
        // ft0-ft7 + fa0-fa7 + ft8-ft11 = 8 + 8 + 4 = 20
        assert_eq!(regs.len(), 20);
    }

    #[test]
    fn test_callee_saved_fprs_count() {
        let regs = RiscVRegisterInfo::get_callee_saved_fprs();
        // fs0-fs1 + fs2-fs11 = 2 + 10 = 12
        assert_eq!(regs.len(), 12);
    }

    #[test]
    fn test_all_gpr_ids_in_range() {
        for id in 3000u16..=3031u16 {
            assert!(RiscVRegisterInfo::is_gpr(id));
            assert!(!RiscVRegisterInfo::is_fpr(id));
        }
    }

    #[test]
    fn test_all_fpr_ids_in_range() {
        for id in 3050u16..=3081u16 {
            assert!(RiscVRegisterInfo::is_fpr(id));
            assert!(!RiscVRegisterInfo::is_gpr(id));
        }
    }
}