librsmsx 0.3.13

#![allow(non_snake_case, unused_variables)]
// /*

// Copyright (c) 2010 Andrea Fazzi

// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// 8
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// */
use crate::libs::memory::Memory;

use super::util::join_bytes;
use super::z80_base::{Z80Data, SHIFT_0X_CB, SHIFT_0X_DD, SHIFT_0X_DDCB, SHIFT_0X_ED, SHIFT_0X_FD};

#[allow(non_snake_case)]
pub fn disassemble_map(data: &mut Z80Data, memory: &mut Memory, opcode: u16) {
    match opcode {
        0 => {
            /* NOP */
            disassemble__NOP(data, memory);
        }
        1 => {
            /* LD BC,nnnn */
            disassemble__LD_BC_NNNN(data, memory);
        }
        0x02 => {
            /* LD (BC),A */
            disassemble__LD_iBC_A(data, memory);
        }

        0x03 => {
            /* INC BC */
            disassemble__INC_BC(data, memory);
        }

        0x04 => {
            /* INC B */
            disassemble__INC_B(data, memory);
        }

        0x05 => {
            /* DEC B */
            disassemble__DEC_B(data, memory);
        }

        0x06 => {
            /* LD B,nn */
            disassemble__LD_B_NN(data, memory);
        }

        0x07 => {
            /* RLCA */
            disassemble__RLCA(data, memory);
        }

        0x08 => {
            /* EX AF,AF' */
            disassemble__EX_AF_AF(data, memory);
        }

        0x09 => {
            /* ADD HL,BC */
            disassemble__ADD_HL_BC(data, memory);
        }

        0x0a => {
            /* LD A,(BC) */
            disassemble__LD_A_iBC(data, memory);
        }

        0x0b => {
            /* DEC BC */
            disassemble__DEC_BC(data, memory);
        }

        0x0c => {
            /* INC C */
            disassemble__INC_C(data, memory);
        }

        0x0d => {
            /* DEC C */
            disassemble__DEC_C(data, memory);
        }

        0x0e => {
            /* LD C,nn */
            disassemble__LD_C_NN(data, memory);
        }

        0x0f => {
            /* RRCA */
            disassemble__RRCA(data, memory);
        }

        0x10 => {
            /* DJNZ offset */
            disassemble__DJNZ_OFFSET(data, memory);
        }

        0x11 => {
            /* LD DE,nnnn */
            disassemble__LD_DE_NNNN(data, memory);
        }

        0x12 => {
            /* LD (DE),A */
            disassemble__LD_iDE_A(data, memory);
        }

        0x13 => {
            /* INC DE */
            disassemble__INC_DE(data, memory);
        }

        0x14 => {
            /* INC D */
            disassemble__INC_D(data, memory);
        }

        0x15 => {
            /* DEC D */
            disassemble__DEC_D(data, memory);
        }

        0x16 => {
            /* LD D,nn */
            disassemble__LD_D_NN(data, memory);
        }

        0x17 => {
            /* RLA */
            disassemble__RLA(data, memory);
        }

        0x18 => {
            /* JR offset */
            disassemble__JR_OFFSET(data, memory);
        }

        0x19 => {
            /* ADD HL,DE */
            disassemble__ADD_HL_DE(data, memory);
        }

        0x1a => {
            /* LD A,(DE) */
            disassemble__LD_A_iDE(data, memory);
        }

        0x1b => {
            /* DEC DE */
            disassemble__DEC_DE(data, memory);
        }

        0x1c => {
            /* INC E */
            disassemble__INC_E(data, memory);
        }

        0x1d => {
            /* DEC E */
            disassemble__DEC_E(data, memory);
        }

        0x1e => {
            /* LD E,nn */
            disassemble__LD_E_NN(data, memory);
        }

        0x1f => {
            /* RRA */
            disassemble__RRA(data, memory);
        }

        0x20 => {
            /* JR NZ,offset */
            disassemble__JR_NZ_OFFSET(data, memory);
        }

        0x21 => {
            /* LD HL,nnnn */
            disassemble__LD_HL_NNNN(data, memory);
        }

        0x22 => {
            /* LD (nnnn),HL */
            disassemble__LD_iNNNN_HL(data, memory);
        }

        0x23 => {
            /* INC HL */
            disassemble__INC_HL(data, memory);
        }

        0x24 => {
            /* INC H */
            disassemble__INC_H(data, memory);
        }

        0x25 => {
            /* DEC H */
            disassemble__DEC_H(data, memory);
        }

        0x26 => {
            /* LD H,nn */
            disassemble__LD_H_NN(data, memory);
        }

        0x27 => {
            /* DAA */
            disassemble__DAA(data, memory);
        }

        0x28 => {
            /* JR Z,offset */
            disassemble__JR_Z_OFFSET(data, memory);
        }

        0x29 => {
            /* ADD HL,HL */
            disassemble__ADD_HL_HL(data, memory);
        }

        0x2a => {
            /* LD HL,(nnnn) */
            disassemble__LD_HL_iNNNN(data, memory);
        }

        0x2b => {
            /* DEC HL */
            disassemble__DEC_HL(data, memory);
        }

        0x2c => {
            /* INC L */
            disassemble__INC_L(data, memory);
        }

        0x2d => {
            /* DEC L */
            disassemble__DEC_L(data, memory);
        }

        0x2e => {
            /* LD L,nn */
            disassemble__LD_L_NN(data, memory);
        }

        0x2f => {
            /* CPL */
            disassemble__CPL(data, memory);
        }

        0x30 => {
            /* JR NC,offset */
            disassemble__JR_NC_OFFSET(data, memory);
        }

        0x31 => {
            /* LD SP,nnnn */
            disassemble__LD_SP_NNNN(data, memory);
        }

        0x32 => {
            /* LD (nnnn),A */
            disassemble__LD_iNNNN_A(data, memory);
        }

        0x33 => {
            /* INC SP */
            disassemble__INC_SP(data, memory);
        }

        0x34 => {
            /* INC (HL) */
            disassemble__INC_iHL(data, memory);
        }

        0x35 => {
            /* DEC (HL) */
            disassemble__DEC_iHL(data, memory);
        }

        0x36 => {
            /* LD (HL),nn */
            disassemble__LD_iHL_NN(data, memory);
        }

        0x37 => {
            /* SCF */
            disassemble__SCF(data, memory);
        }

        0x38 => {
            /* JR C,offset */
            disassemble__JR_C_OFFSET(data, memory);
        }

        0x39 => {
            /* ADD HL,SP */
            disassemble__ADD_HL_SP(data, memory);
        }

        0x3a => {
            /* LD A,(nnnn) */
            disassemble__LD_A_iNNNN(data, memory);
        }

        0x3b => {
            /* DEC SP */
            disassemble__DEC_SP(data, memory);
        }

        0x3c => {
            /* INC A */
            disassemble__INC_A(data, memory);
        }

        0x3d => {
            /* DEC A */
            disassemble__DEC_A(data, memory);
        }

        0x3e => {
            /* LD A,nn */
            disassemble__LD_A_NN(data, memory);
        }

        0x3f => {
            /* CCF */
            disassemble__CCF(data, memory);
        }

        0x40 => {
            /* LD B,B */
            disassemble__LD_B_B(data, memory);
        }

        0x41 => {
            /* LD B,C */
            disassemble__LD_B_C(data, memory);
        }

        0x42 => {
            /* LD B,D */
            disassemble__LD_B_D(data, memory);
        }

        0x43 => {
            /* LD B,E */
            disassemble__LD_B_E(data, memory);
        }

        0x44 => {
            /* LD B,H */
            disassemble__LD_B_H(data, memory);
        }

        0x45 => {
            /* LD B,L */
            disassemble__LD_B_L(data, memory);
        }

        0x46 => {
            /* LD B,(HL) */
            disassemble__LD_B_iHL(data, memory);
        }

        0x47 => {
            /* LD B,A */
            disassemble__LD_B_A(data, memory);
        }

        0x48 => {
            /* LD C,B */
            disassemble__LD_C_B(data, memory);
        }

        0x49 => {
            /* LD C,C */
            disassemble__LD_C_C(data, memory);
        }

        0x4a => {
            /* LD C,D */
            disassemble__LD_C_D(data, memory);
        }

        0x4b => {
            /* LD C,E */
            disassemble__LD_C_E(data, memory);
        }

        0x4c => {
            /* LD C,H */
            disassemble__LD_C_H(data, memory);
        }

        0x4d => {
            /* LD C,L */
            disassemble__LD_C_L(data, memory);
        }

        0x4e => {
            /* LD C,(HL) */
            disassemble__LD_C_iHL(data, memory);
        }

        0x4f => {
            /* LD C,A */
            disassemble__LD_C_A(data, memory);
        }

        0x50 => {
            /* LD D,B */
            disassemble__LD_D_B(data, memory);
        }

        0x51 => {
            /* LD D,C */
            disassemble__LD_D_C(data, memory);
        }

        0x52 => {
            /* LD D,D */
            disassemble__LD_D_D(data, memory);
        }

        0x53 => {
            /* LD D,E */
            disassemble__LD_D_E(data, memory);
        }

        0x54 => {
            /* LD D,H */
            disassemble__LD_D_H(data, memory);
        }

        0x55 => {
            /* LD D,L */
            disassemble__LD_D_L(data, memory);
        }

        0x56 => {
            /* LD D,(HL) */
            disassemble__LD_D_iHL(data, memory);
        }

        0x57 => {
            /* LD D,A */
            disassemble__LD_D_A(data, memory);
        }

        0x58 => {
            /* LD E,B */
            disassemble__LD_E_B(data, memory);
        }

        0x59 => {
            /* LD E,C */
            disassemble__LD_E_C(data, memory);
        }

        0x5a => {
            /* LD E,D */
            disassemble__LD_E_D(data, memory);
        }

        0x5b => {
            /* LD E,E */
            disassemble__LD_E_E(data, memory);
        }

        0x5c => {
            /* LD E,H */
            disassemble__LD_E_H(data, memory);
        }

        0x5d => {
            /* LD E,L */
            disassemble__LD_E_L(data, memory);
        }

        0x5e => {
            /* LD E,(HL) */
            disassemble__LD_E_iHL(data, memory);
        }

        0x5f => {
            /* LD E,A */
            disassemble__LD_E_A(data, memory);
        }

        0x60 => {
            /* LD H,B */
            disassemble__LD_H_B(data, memory);
        }

        0x61 => {
            /* LD H,C */
            disassemble__LD_H_C(data, memory);
        }

        0x62 => {
            /* LD H,D */
            disassemble__LD_H_D(data, memory);
        }

        0x63 => {
            /* LD H,E */
            disassemble__LD_H_E(data, memory);
        }

        0x64 => {
            /* LD H,H */
            disassemble__LD_H_H(data, memory);
        }

        0x65 => {
            /* LD H,L */
            disassemble__LD_H_L(data, memory);
        }

        0x66 => {
            /* LD H,(HL) */
            disassemble__LD_H_iHL(data, memory);
        }

        0x67 => {
            /* LD H,A */
            disassemble__LD_H_A(data, memory);
        }

        0x68 => {
            /* LD L,B */
            disassemble__LD_L_B(data, memory);
        }

        0x69 => {
            /* LD L,C */
            disassemble__LD_L_C(data, memory);
        }

        0x6a => {
            /* LD L,D */
            disassemble__LD_L_D(data, memory);
        }

        0x6b => {
            /* LD L,E */
            disassemble__LD_L_E(data, memory);
        }

        0x6c => {
            /* LD L,H */
            disassemble__LD_L_H(data, memory);
        }

        0x6d => {
            /* LD L,L */
            disassemble__LD_L_L(data, memory);
        }

        0x6e => {
            /* LD L,(HL) */
            disassemble__LD_L_iHL(data, memory);
        }

        0x6f => {
            /* LD L,A */
            disassemble__LD_L_A(data, memory);
        }

        0x70 => {
            /* LD (HL),B */
            disassemble__LD_iHL_B(data, memory);
        }

        0x71 => {
            /* LD (HL),C */
            disassemble__LD_iHL_C(data, memory);
        }

        0x72 => {
            /* LD (HL),D */
            disassemble__LD_iHL_D(data, memory);
        }

        0x73 => {
            /* LD (HL),E */
            disassemble__LD_iHL_E(data, memory);
        }

        0x74 => {
            /* LD (HL),H */
            disassemble__LD_iHL_H(data, memory);
        }

        0x75 => {
            /* LD (HL),L */
            disassemble__LD_iHL_L(data, memory);
        }

        0x76 => {
            /* HALT */
            disassemble__HALT(data, memory);
        }

        0x77 => {
            /* LD (HL),A */
            disassemble__LD_iHL_A(data, memory);
        }

        0x78 => {
            /* LD A,B */
            disassemble__LD_A_B(data, memory);
        }

        0x79 => {
            /* LD A,C */
            disassemble__LD_A_C(data, memory);
        }

        0x7a => {
            /* LD A,D */
            disassemble__LD_A_D(data, memory);
        }

        0x7b => {
            /* LD A,E */
            disassemble__LD_A_E(data, memory);
        }

        0x7c => {
            /* LD A,H */
            disassemble__LD_A_H(data, memory);
        }

        0x7d => {
            /* LD A,L */
            disassemble__LD_A_L(data, memory);
        }

        0x7e => {
            /* LD A,(HL) */
            disassemble__LD_A_iHL(data, memory);
        }

        0x7f => {
            /* LD A,A */
            disassemble__LD_A_A(data, memory);
        }

        0x80 => {
            /* ADD A,B */
            disassemble__ADD_A_B(data, memory);
        }

        0x81 => {
            /* ADD A,C */
            disassemble__ADD_A_C(data, memory);
        }

        0x82 => {
            /* ADD A,D */
            disassemble__ADD_A_D(data, memory);
        }

        0x83 => {
            /* ADD A,E */
            disassemble__ADD_A_E(data, memory);
        }

        0x84 => {
            /* ADD A,H */
            disassemble__ADD_A_H(data, memory);
        }

        0x85 => {
            /* ADD A,L */
            disassemble__ADD_A_L(data, memory);
        }

        0x86 => {
            /* ADD A,(HL) */
            disassemble__ADD_A_iHL(data, memory);
        }

        0x87 => {
            /* ADD A,A */
            disassemble__ADD_A_A(data, memory);
        }

        0x88 => {
            /* ADC A,B */
            disassemble__ADC_A_B(data, memory);
        }

        0x89 => {
            /* ADC A,C */
            disassemble__ADC_A_C(data, memory);
        }

        0x8a => {
            /* ADC A,D */
            disassemble__ADC_A_D(data, memory);
        }

        0x8b => {
            /* ADC A,E */
            disassemble__ADC_A_E(data, memory);
        }

        0x8c => {
            /* ADC A,H */
            disassemble__ADC_A_H(data, memory);
        }

        0x8d => {
            /* ADC A,L */
            disassemble__ADC_A_L(data, memory);
        }

        0x8e => {
            /* ADC A,(HL) */
            disassemble__ADC_A_iHL(data, memory);
        }

        0x8f => {
            /* ADC A,A */
            disassemble__ADC_A_A(data, memory);
        }

        0x90 => {
            /* SUB A,B */
            disassemble__SUB_A_B(data, memory);
        }

        0x91 => {
            /* SUB A,C */
            disassemble__SUB_A_C(data, memory);
        }

        0x92 => {
            /* SUB A,D */
            disassemble__SUB_A_D(data, memory);
        }

        0x93 => {
            /* SUB A,E */
            disassemble__SUB_A_E(data, memory);
        }

        0x94 => {
            /* SUB A,H */
            disassemble__SUB_A_H(data, memory);
        }

        0x95 => {
            /* SUB A,L */
            disassemble__SUB_A_L(data, memory);
        }

        0x96 => {
            /* SUB A,(HL) */
            disassemble__SUB_A_iHL(data, memory);
        }

        0x97 => {
            /* SUB A,A */
            disassemble__SUB_A_A(data, memory);
        }

        0x98 => {
            /* SBC A,B */
            disassemble__SBC_A_B(data, memory);
        }

        0x99 => {
            /* SBC A,C */
            disassemble__SBC_A_C(data, memory);
        }

        0x9a => {
            /* SBC A,D */
            disassemble__SBC_A_D(data, memory);
        }

        0x9b => {
            /* SBC A,E */
            disassemble__SBC_A_E(data, memory);
        }

        0x9c => {
            /* SBC A,H */
            disassemble__SBC_A_H(data, memory);
        }

        0x9d => {
            /* SBC A,L */
            disassemble__SBC_A_L(data, memory);
        }

        0x9e => {
            /* SBC A,(HL) */
            disassemble__SBC_A_iHL(data, memory);
        }

        0x9f => {
            /* SBC A,A */
            disassemble__SBC_A_A(data, memory);
        }

        0xa0 => {
            /* AND A,B */
            disassemble__AND_A_B(data, memory);
        }

        0xa1 => {
            /* AND A,C */
            disassemble__AND_A_C(data, memory);
        }

        0xa2 => {
            /* AND A,D */
            disassemble__AND_A_D(data, memory);
        }

        0xa3 => {
            /* AND A,E */
            disassemble__AND_A_E(data, memory);
        }

        0xa4 => {
            /* AND A,H */
            disassemble__AND_A_H(data, memory);
        }

        0xa5 => {
            /* AND A,L */
            disassemble__AND_A_L(data, memory);
        }

        0xa6 => {
            /* AND A,(HL) */
            disassemble__AND_A_iHL(data, memory);
        }

        0xa7 => {
            /* AND A,A */
            disassemble__AND_A_A(data, memory);
        }

        0xa8 => {
            /* XOR A,B */
            disassemble__XOR_A_B(data, memory);
        }

        0xa9 => {
            /* XOR A,C */
            disassemble__XOR_A_C(data, memory);
        }

        0xaa => {
            /* XOR A,D */
            disassemble__XOR_A_D(data, memory);
        }

        0xab => {
            /* XOR A,E */
            disassemble__XOR_A_E(data, memory);
        }

        0xac => {
            /* XOR A,H */
            disassemble__XOR_A_H(data, memory);
        }

        0xad => {
            /* XOR A,L */
            disassemble__XOR_A_L(data, memory);
        }

        0xae => {
            /* XOR A,(HL) */
            disassemble__XOR_A_iHL(data, memory);
        }

        0xaf => {
            /* XOR A,A */
            disassemble__XOR_A_A(data, memory);
        }

        0xb0 => {
            /* OR A,B */
            disassemble__OR_A_B(data, memory);
        }

        0xb1 => {
            /* OR A,C */
            disassemble__OR_A_C(data, memory);
        }

        0xb2 => {
            /* OR A,D */
            disassemble__OR_A_D(data, memory);
        }

        0xb3 => {
            /* OR A,E */
            disassemble__OR_A_E(data, memory);
        }

        0xb4 => {
            /* OR A,H */
            disassemble__OR_A_H(data, memory);
        }

        0xb5 => {
            /* OR A,L */
            disassemble__OR_A_L(data, memory);
        }

        0xb6 => {
            /* OR A,(HL) */
            disassemble__OR_A_iHL(data, memory);
        }

        0xb7 => {
            /* OR A,A */
            disassemble__OR_A_A(data, memory);
        }

        0xb8 => {
            /* CP B */
            disassemble__CP_B(data, memory);
        }

        0xb9 => {
            /* CP C */
            disassemble__CP_C(data, memory);
        }

        0xba => {
            /* CP D */
            disassemble__CP_D(data, memory);
        }

        0xbb => {
            /* CP E */
            disassemble__CP_E(data, memory);
        }

        0xbc => {
            /* CP H */
            disassemble__CP_H(data, memory);
        }

        0xbd => {
            /* CP L */
            disassemble__CP_L(data, memory);
        }

        0xbe => {
            /* CP (HL) */
            disassemble__CP_iHL(data, memory);
        }

        0xbf => {
            /* CP A */
            disassemble__CP_A(data, memory);
        }

        0xc0 => {
            /* RET NZ */
            disassemble__RET_NZ(data, memory);
        }

        0xc1 => {
            /* POP BC */
            disassemble__POP_BC(data, memory);
        }

        0xc2 => {
            /* JP NZ,nnnn */
            disassemble__JP_NZ_NNNN(data, memory);
        }

        0xc3 => {
            /* JP nnnn */
            disassemble__JP_NNNN(data, memory);
        }

        0xc4 => {
            /* CALL NZ,nnnn */
            disassemble__CALL_NZ_NNNN(data, memory);
        }

        0xc5 => {
            /* PUSH BC */
            disassemble__PUSH_BC(data, memory);
        }

        0xc6 => {
            /* ADD A,nn */
            disassemble__ADD_A_NN(data, memory);
        }

        0xc7 => {
            /* RST 00 */
            disassemble__RST_00(data, memory);
        }

        0xc8 => {
            /* RET Z */
            disassemble__RET_Z(data, memory);
        }

        0xc9 => {
            /* RET */
            disassemble__RET(data, memory);
        }

        0xca => {
            /* JP Z,nnnn */
            disassemble__JP_Z_NNNN(data, memory);
        }

        0xcb => {
            /* shift CB */
            disassemble__SHIFT_CB(data, memory);
        }

        0xcc => {
            /* CALL Z,nnnn */
            disassemble__CALL_Z_NNNN(data, memory);
        }

        0xcd => {
            /* CALL nnnn */
            disassemble__CALL_NNNN(data, memory);
        }

        0xce => {
            /* ADC A,nn */
            disassemble__ADC_A_NN(data, memory);
        }

        0xcf => {
            /* RST 8 */
            disassemble__RST_8(data, memory);
        }

        0xd0 => {
            /* RET NC */
            disassemble__RET_NC(data, memory);
        }

        0xd1 => {
            /* POP DE */
            disassemble__POP_DE(data, memory);
        }

        0xd2 => {
            /* JP NC,nnnn */
            disassemble__JP_NC_NNNN(data, memory);
        }

        0xd3 => {
            /* OUT (nn),A */
            disassemble__OUT_iNN_A(data, memory);
        }

        0xd4 => {
            /* CALL NC,nnnn */
            disassemble__CALL_NC_NNNN(data, memory);
        }

        0xd5 => {
            /* PUSH DE */
            disassemble__PUSH_DE(data, memory);
        }

        0xd6 => {
            /* SUB nn */
            disassemble__SUB_NN(data, memory);
        }

        0xd7 => {
            /* RST 10 */
            disassemble__RST_10(data, memory);
        }

        0xd8 => {
            /* RET C */
            disassemble__RET_C(data, memory);
        }

        0xd9 => {
            /* EXX */
            disassemble__EXX(data, memory);
        }

        0xda => {
            /* JP C,nnnn */
            disassemble__JP_C_NNNN(data, memory);
        }

        0xdb => {
            /* IN A,(nn) */
            disassemble__IN_A_iNN(data, memory);
        }

        0xdc => {
            /* CALL C,nnnn */
            disassemble__CALL_C_NNNN(data, memory);
        }

        0xdd => {
            /* shift DD */
            disassemble__SHIFT_DD(data, memory);
        }

        0xde => {
            /* SBC A,nn */
            disassemble__SBC_A_NN(data, memory);
        }

        0xdf => {
            /* RST 18 */
            disassemble__RST_18(data, memory);
        }

        0xe0 => {
            /* RET PO */
            disassemble__RET_PO(data, memory);
        }

        0xe1 => {
            /* POP HL */
            disassemble__POP_HL(data, memory);
        }

        0xe2 => {
            /* JP PO,nnnn */
            disassemble__JP_PO_NNNN(data, memory);
        }

        0xe3 => {
            /* EX (SP),HL */
            disassemble__EX_iSP_HL(data, memory);
        }

        0xe4 => {
            /* CALL PO,nnnn */
            disassemble__CALL_PO_NNNN(data, memory);
        }

        0xe5 => {
            /* PUSH HL */
            disassemble__PUSH_HL(data, memory);
        }

        0xe6 => {
            /* AND nn */
            disassemble__AND_NN(data, memory);
        }

        0xe7 => {
            /* RST 20 */
            disassemble__RST_20(data, memory);
        }

        0xe8 => {
            /* RET PE */
            disassemble__RET_PE(data, memory);
        }

        0xe9 => {
            /* JP HL */
            disassemble__JP_HL(data, memory);
        }

        0xea => {
            /* JP PE,nnnn */
            disassemble__JP_PE_NNNN(data, memory);
        }

        0xeb => {
            /* EX DE,HL */
            disassemble__EX_DE_HL(data, memory);
        }

        0xec => {
            /* CALL PE,nnnn */
            disassemble__CALL_PE_NNNN(data, memory);
        }

        0xed => {
            /* shift ED */
            disassemble__SHIFT_ED(data, memory);
        }

        0xee => {
            /* XOR A,nn */
            disassemble__XOR_A_NN(data, memory);
        }

        0xef => {
            /* RST 28 */
            disassemble__RST_28(data, memory);
        }

        0xf0 => {
            /* RET P */
            disassemble__RET_P(data, memory);
        }

        0xf1 => {
            /* POP AF */
            disassemble__POP_AF(data, memory);
        }

        0xf2 => {
            /* JP P,nnnn */
            disassemble__JP_P_NNNN(data, memory);
        }

        0xf3 => {
            /* DI */
            disassemble__DI(data, memory);
        }

        0xf4 => {
            /* CALL P,nnnn */
            disassemble__CALL_P_NNNN(data, memory);
        }

        0xf5 => {
            /* PUSH AF */
            disassemble__PUSH_AF(data, memory);
        }

        0xf6 => {
            /* OR nn */
            disassemble__OR_NN(data, memory);
        }

        0xf7 => {
            /* RST 30 */
            disassemble__RST_30(data, memory);
        }

        0xf8 => {
            /* RET M */
            disassemble__RET_M(data, memory);
        }

        0xf9 => {
            /* LD SP,HL */
            disassemble__LD_SP_HL(data, memory);
        }

        0xfa => {
            /* JP M,nnnn */
            disassemble__JP_M_NNNN(data, memory);
        }

        0xfb => {
            /* EI */
            disassemble__EI(data, memory);
        }

        0xfc => {
            /* CALL M,nnnn */
            disassemble__CALL_M_NNNN(data, memory);
        }

        0xfd => {
            /* shift FD */
            disassemble__SHIFT_FD(data, memory);
        }

        0xfe => {
            /* CP nn */
            disassemble__CP_NN(data, memory);
        }

        0xff => {
            /* RST 38 */
            disassemble__RST_38(data, memory);
        }

        val if val == SHIFT_0X_CB => {
            /* RLC B */
            disassembleCB__RLC_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x01 => {
            /* RLC C */
            disassembleCB__RLC_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x02 => {
            /* RLC D */
            disassembleCB__RLC_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x03 => {
            /* RLC E */
            disassembleCB__RLC_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x04 => {
            /* RLC H */
            disassembleCB__RLC_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x05 => {
            /* RLC L */
            disassembleCB__RLC_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x06 => {
            /* RLC (HL) */
            disassembleCB__RLC_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x07 => {
            /* RLC A */
            disassembleCB__RLC_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x08 => {
            /* RRC B */
            disassembleCB__RRC_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x09 => {
            /* RRC C */
            disassembleCB__RRC_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x0a => {
            /* RRC D */
            disassembleCB__RRC_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x0b => {
            /* RRC E */
            disassembleCB__RRC_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x0c => {
            /* RRC H */
            disassembleCB__RRC_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x0d => {
            /* RRC L */
            disassembleCB__RRC_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x0e => {
            /* RRC (HL) */
            disassembleCB__RRC_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x0f => {
            /* RRC A */
            disassembleCB__RRC_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x10 => {
            /* RL B */
            disassembleCB__RL_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x11 => {
            /* RL C */
            disassembleCB__RL_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x12 => {
            /* RL D */
            disassembleCB__RL_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x13 => {
            /* RL E */
            disassembleCB__RL_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x14 => {
            /* RL H */
            disassembleCB__RL_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x15 => {
            /* RL L */
            disassembleCB__RL_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x16 => {
            /* RL (HL) */
            disassembleCB__RL_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x17 => {
            /* RL A */
            disassembleCB__RL_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x18 => {
            /* RR B */
            disassembleCB__RR_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x19 => {
            /* RR C */
            disassembleCB__RR_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x1a => {
            /* RR D */
            disassembleCB__RR_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x1b => {
            /* RR E */
            disassembleCB__RR_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x1c => {
            /* RR H */
            disassembleCB__RR_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x1d => {
            /* RR L */
            disassembleCB__RR_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x1e => {
            /* RR (HL) */
            disassembleCB__RR_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x1f => {
            /* RR A */
            disassembleCB__RR_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x20 => {
            /* SLA B */
            disassembleCB__SLA_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x21 => {
            /* SLA C */
            disassembleCB__SLA_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x22 => {
            /* SLA D */
            disassembleCB__SLA_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x23 => {
            /* SLA E */
            disassembleCB__SLA_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x24 => {
            /* SLA H */
            disassembleCB__SLA_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x25 => {
            /* SLA L */
            disassembleCB__SLA_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x26 => {
            /* SLA (HL) */
            disassembleCB__SLA_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x27 => {
            /* SLA A */
            disassembleCB__SLA_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x28 => {
            /* SRA B */
            disassembleCB__SRA_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x29 => {
            /* SRA C */
            disassembleCB__SRA_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x2a => {
            /* SRA D */
            disassembleCB__SRA_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x2b => {
            /* SRA E */
            disassembleCB__SRA_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x2c => {
            /* SRA H */
            disassembleCB__SRA_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x2d => {
            /* SRA L */
            disassembleCB__SRA_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x2e => {
            /* SRA (HL) */
            disassembleCB__SRA_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x2f => {
            /* SRA A */
            disassembleCB__SRA_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x30 => {
            /* SLL B */
            disassembleCB__SLL_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x31 => {
            /* SLL C */
            disassembleCB__SLL_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x32 => {
            /* SLL D */
            disassembleCB__SLL_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x33 => {
            /* SLL E */
            disassembleCB__SLL_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x34 => {
            /* SLL H */
            disassembleCB__SLL_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x35 => {
            /* SLL L */
            disassembleCB__SLL_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x36 => {
            /* SLL (HL) */
            disassembleCB__SLL_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x37 => {
            /* SLL A */
            disassembleCB__SLL_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x38 => {
            /* SRL B */
            disassembleCB__SRL_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x39 => {
            /* SRL C */
            disassembleCB__SRL_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x3a => {
            /* SRL D */
            disassembleCB__SRL_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x3b => {
            /* SRL E */
            disassembleCB__SRL_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x3c => {
            /* SRL H */
            disassembleCB__SRL_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x3d => {
            /* SRL L */
            disassembleCB__SRL_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x3e => {
            /* SRL (HL) */
            disassembleCB__SRL_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x3f => {
            /* SRL A */
            disassembleCB__SRL_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x40 => {
            /* BIT 0,B */
            disassembleCB__BIT_0_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x41 => {
            /* BIT 0,C */
            disassembleCB__BIT_0_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x42 => {
            /* BIT 0,D */
            disassembleCB__BIT_0_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x43 => {
            /* BIT 0,E */
            disassembleCB__BIT_0_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x44 => {
            /* BIT 0,H */
            disassembleCB__BIT_0_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x45 => {
            /* BIT 0,L */
            disassembleCB__BIT_0_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x46 => {
            /* BIT 0,(HL) */
            disassembleCB__BIT_0_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x47 => {
            /* BIT 0,A */
            disassembleCB__BIT_0_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x48 => {
            /* BIT 1,B */
            disassembleCB__BIT_1_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x49 => {
            /* BIT 1,C */
            disassembleCB__BIT_1_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x4a => {
            /* BIT 1,D */
            disassembleCB__BIT_1_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x4b => {
            /* BIT 1,E */
            disassembleCB__BIT_1_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x4c => {
            /* BIT 1,H */
            disassembleCB__BIT_1_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x4d => {
            /* BIT 1,L */
            disassembleCB__BIT_1_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x4e => {
            /* BIT 1,(HL) */
            disassembleCB__BIT_1_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x4f => {
            /* BIT 1,A */
            disassembleCB__BIT_1_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x50 => {
            /* BIT 2,B */
            disassembleCB__BIT_2_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x51 => {
            /* BIT 2,C */
            disassembleCB__BIT_2_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x52 => {
            /* BIT 2,D */
            disassembleCB__BIT_2_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x53 => {
            /* BIT 2,E */
            disassembleCB__BIT_2_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x54 => {
            /* BIT 2,H */
            disassembleCB__BIT_2_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x55 => {
            /* BIT 2,L */
            disassembleCB__BIT_2_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x56 => {
            /* BIT 2,(HL) */
            disassembleCB__BIT_2_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x57 => {
            /* BIT 2,A */
            disassembleCB__BIT_2_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x58 => {
            /* BIT 3,B */
            disassembleCB__BIT_3_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x59 => {
            /* BIT 3,C */
            disassembleCB__BIT_3_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x5a => {
            /* BIT 3,D */
            disassembleCB__BIT_3_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x5b => {
            /* BIT 3,E */
            disassembleCB__BIT_3_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x5c => {
            /* BIT 3,H */
            disassembleCB__BIT_3_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x5d => {
            /* BIT 3,L */
            disassembleCB__BIT_3_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x5e => {
            /* BIT 3,(HL) */
            disassembleCB__BIT_3_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x5f => {
            /* BIT 3,A */
            disassembleCB__BIT_3_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x60 => {
            /* BIT 4,B */
            disassembleCB__BIT_4_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x61 => {
            /* BIT 4,C */
            disassembleCB__BIT_4_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x62 => {
            /* BIT 4,D */
            disassembleCB__BIT_4_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x63 => {
            /* BIT 4,E */
            disassembleCB__BIT_4_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x64 => {
            /* BIT 4,H */
            disassembleCB__BIT_4_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x65 => {
            /* BIT 4,L */
            disassembleCB__BIT_4_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x66 => {
            /* BIT 4,(HL) */
            disassembleCB__BIT_4_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x67 => {
            /* BIT 4,A */
            disassembleCB__BIT_4_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x68 => {
            /* BIT 5,B */
            disassembleCB__BIT_5_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x69 => {
            /* BIT 5,C */
            disassembleCB__BIT_5_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x6a => {
            /* BIT 5,D */
            disassembleCB__BIT_5_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x6b => {
            /* BIT 5,E */
            disassembleCB__BIT_5_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x6c => {
            /* BIT 5,H */
            disassembleCB__BIT_5_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x6d => {
            /* BIT 5,L */
            disassembleCB__BIT_5_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x6e => {
            /* BIT 5,(HL) */
            disassembleCB__BIT_5_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x6f => {
            /* BIT 5,A */
            disassembleCB__BIT_5_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x70 => {
            /* BIT 6,B */
            disassembleCB__BIT_6_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x71 => {
            /* BIT 6,C */
            disassembleCB__BIT_6_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x72 => {
            /* BIT 6,D */
            disassembleCB__BIT_6_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x73 => {
            /* BIT 6,E */
            disassembleCB__BIT_6_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x74 => {
            /* BIT 6,H */
            disassembleCB__BIT_6_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x75 => {
            /* BIT 6,L */
            disassembleCB__BIT_6_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x76 => {
            /* BIT 6,(HL) */
            disassembleCB__BIT_6_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x77 => {
            /* BIT 6,A */
            disassembleCB__BIT_6_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x78 => {
            /* BIT 7,B */
            disassembleCB__BIT_7_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x79 => {
            /* BIT 7,C */
            disassembleCB__BIT_7_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x7a => {
            /* BIT 7,D */
            disassembleCB__BIT_7_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x7b => {
            /* BIT 7,E */
            disassembleCB__BIT_7_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x7c => {
            /* BIT 7,H */
            disassembleCB__BIT_7_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x7d => {
            /* BIT 7,L */
            disassembleCB__BIT_7_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x7e => {
            /* BIT 7,(HL) */
            disassembleCB__BIT_7_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x7f => {
            /* BIT 7,A */
            disassembleCB__BIT_7_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x80 => {
            /* RES 0,B */
            disassembleCB__RES_0_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x81 => {
            /* RES 0,C */
            disassembleCB__RES_0_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x82 => {
            /* RES 0,D */
            disassembleCB__RES_0_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x83 => {
            /* RES 0,E */
            disassembleCB__RES_0_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x84 => {
            /* RES 0,H */
            disassembleCB__RES_0_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x85 => {
            /* RES 0,L */
            disassembleCB__RES_0_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x86 => {
            /* RES 0,(HL) */
            disassembleCB__RES_0_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x87 => {
            /* RES 0,A */
            disassembleCB__RES_0_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x88 => {
            /* RES 1,B */
            disassembleCB__RES_1_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x89 => {
            /* RES 1,C */
            disassembleCB__RES_1_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x8a => {
            /* RES 1,D */
            disassembleCB__RES_1_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x8b => {
            /* RES 1,E */
            disassembleCB__RES_1_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x8c => {
            /* RES 1,H */
            disassembleCB__RES_1_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x8d => {
            /* RES 1,L */
            disassembleCB__RES_1_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x8e => {
            /* RES 1,(HL) */
            disassembleCB__RES_1_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x8f => {
            /* RES 1,A */
            disassembleCB__RES_1_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x90 => {
            /* RES 2,B */
            disassembleCB__RES_2_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x91 => {
            /* RES 2,C */
            disassembleCB__RES_2_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x92 => {
            /* RES 2,D */
            disassembleCB__RES_2_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x93 => {
            /* RES 2,E */
            disassembleCB__RES_2_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x94 => {
            /* RES 2,H */
            disassembleCB__RES_2_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x95 => {
            /* RES 2,L */
            disassembleCB__RES_2_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x96 => {
            /* RES 2,(HL) */
            disassembleCB__RES_2_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x97 => {
            /* RES 2,A */
            disassembleCB__RES_2_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x98 => {
            /* RES 3,B */
            disassembleCB__RES_3_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x99 => {
            /* RES 3,C */
            disassembleCB__RES_3_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x9a => {
            /* RES 3,D */
            disassembleCB__RES_3_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x9b => {
            /* RES 3,E */
            disassembleCB__RES_3_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x9c => {
            /* RES 3,H */
            disassembleCB__RES_3_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x9d => {
            /* RES 3,L */
            disassembleCB__RES_3_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x9e => {
            /* RES 3,(HL) */
            disassembleCB__RES_3_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0x9f => {
            /* RES 3,A */
            disassembleCB__RES_3_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xa0 => {
            /* RES 4,B */
            disassembleCB__RES_4_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xa1 => {
            /* RES 4,C */
            disassembleCB__RES_4_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xa2 => {
            /* RES 4,D */
            disassembleCB__RES_4_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xa3 => {
            /* RES 4,E */
            disassembleCB__RES_4_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xa4 => {
            /* RES 4,H */
            disassembleCB__RES_4_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xa5 => {
            /* RES 4,L */
            disassembleCB__RES_4_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xa6 => {
            /* RES 4,(HL) */
            disassembleCB__RES_4_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xa7 => {
            /* RES 4,A */
            disassembleCB__RES_4_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xa8 => {
            /* RES 5,B */
            disassembleCB__RES_5_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xa9 => {
            /* RES 5,C */
            disassembleCB__RES_5_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xaa => {
            /* RES 5,D */
            disassembleCB__RES_5_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xab => {
            /* RES 5,E */
            disassembleCB__RES_5_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xac => {
            /* RES 5,H */
            disassembleCB__RES_5_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xad => {
            /* RES 5,L */
            disassembleCB__RES_5_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xae => {
            /* RES 5,(HL) */
            disassembleCB__RES_5_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xaf => {
            /* RES 5,A */
            disassembleCB__RES_5_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xb0 => {
            /* RES 6,B */
            disassembleCB__RES_6_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xb1 => {
            /* RES 6,C */
            disassembleCB__RES_6_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xb2 => {
            /* RES 6,D */
            disassembleCB__RES_6_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xb3 => {
            /* RES 6,E */
            disassembleCB__RES_6_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xb4 => {
            /* RES 6,H */
            disassembleCB__RES_6_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xb5 => {
            /* RES 6,L */
            disassembleCB__RES_6_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xb6 => {
            /* RES 6,(HL) */
            disassembleCB__RES_6_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xb7 => {
            /* RES 6,A */
            disassembleCB__RES_6_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xb8 => {
            /* RES 7,B */
            disassembleCB__RES_7_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xb9 => {
            /* RES 7,C */
            disassembleCB__RES_7_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xba => {
            /* RES 7,D */
            disassembleCB__RES_7_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xbb => {
            /* RES 7,E */
            disassembleCB__RES_7_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xbc => {
            /* RES 7,H */
            disassembleCB__RES_7_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xbd => {
            /* RES 7,L */
            disassembleCB__RES_7_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xbe => {
            /* RES 7,(HL) */
            disassembleCB__RES_7_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xbf => {
            /* RES 7,A */
            disassembleCB__RES_7_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xc0 => {
            /* SET 0,B */
            disassembleCB__SET_0_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xc1 => {
            /* SET 0,C */
            disassembleCB__SET_0_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xc2 => {
            /* SET 0,D */
            disassembleCB__SET_0_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xc3 => {
            /* SET 0,E */
            disassembleCB__SET_0_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xc4 => {
            /* SET 0,H */
            disassembleCB__SET_0_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xc5 => {
            /* SET 0,L */
            disassembleCB__SET_0_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xc6 => {
            /* SET 0,(HL) */
            disassembleCB__SET_0_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xc7 => {
            /* SET 0,A */
            disassembleCB__SET_0_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xc8 => {
            /* SET 1,B */
            disassembleCB__SET_1_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xc9 => {
            /* SET 1,C */
            disassembleCB__SET_1_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xca => {
            /* SET 1,D */
            disassembleCB__SET_1_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xcb => {
            /* SET 1,E */
            disassembleCB__SET_1_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xcc => {
            /* SET 1,H */
            disassembleCB__SET_1_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xcd => {
            /* SET 1,L */
            disassembleCB__SET_1_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xce => {
            /* SET 1,(HL) */
            disassembleCB__SET_1_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xcf => {
            /* SET 1,A */
            disassembleCB__SET_1_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xd0 => {
            /* SET 2,B */
            disassembleCB__SET_2_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xd1 => {
            /* SET 2,C */
            disassembleCB__SET_2_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xd2 => {
            /* SET 2,D */
            disassembleCB__SET_2_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xd3 => {
            /* SET 2,E */
            disassembleCB__SET_2_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xd4 => {
            /* SET 2,H */
            disassembleCB__SET_2_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xd5 => {
            /* SET 2,L */
            disassembleCB__SET_2_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xd6 => {
            /* SET 2,(HL) */
            disassembleCB__SET_2_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xd7 => {
            /* SET 2,A */
            disassembleCB__SET_2_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xd8 => {
            /* SET 3,B */
            disassembleCB__SET_3_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xd9 => {
            /* SET 3,C */
            disassembleCB__SET_3_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xda => {
            /* SET 3,D */
            disassembleCB__SET_3_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xdb => {
            /* SET 3,E */
            disassembleCB__SET_3_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xdc => {
            /* SET 3,H */
            disassembleCB__SET_3_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xdd => {
            /* SET 3,L */
            disassembleCB__SET_3_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xde => {
            /* SET 3,(HL) */
            disassembleCB__SET_3_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xdf => {
            /* SET 3,A */
            disassembleCB__SET_3_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xe0 => {
            /* SET 4,B */
            disassembleCB__SET_4_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xe1 => {
            /* SET 4,C */
            disassembleCB__SET_4_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xe2 => {
            /* SET 4,D */
            disassembleCB__SET_4_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xe3 => {
            /* SET 4,E */
            disassembleCB__SET_4_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xe4 => {
            /* SET 4,H */
            disassembleCB__SET_4_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xe5 => {
            /* SET 4,L */
            disassembleCB__SET_4_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xe6 => {
            /* SET 4,(HL) */
            disassembleCB__SET_4_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xe7 => {
            /* SET 4,A */
            disassembleCB__SET_4_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xe8 => {
            /* SET 5,B */
            disassembleCB__SET_5_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xe9 => {
            /* SET 5,C */
            disassembleCB__SET_5_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xea => {
            /* SET 5,D */
            disassembleCB__SET_5_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xeb => {
            /* SET 5,E */
            disassembleCB__SET_5_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xec => {
            /* SET 5,H */
            disassembleCB__SET_5_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xed => {
            /* SET 5,L */
            disassembleCB__SET_5_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xee => {
            /* SET 5,(HL) */
            disassembleCB__SET_5_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xef => {
            /* SET 5,A */
            disassembleCB__SET_5_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xf0 => {
            /* SET 6,B */
            disassembleCB__SET_6_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xf1 => {
            /* SET 6,C */
            disassembleCB__SET_6_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xf2 => {
            /* SET 6,D */
            disassembleCB__SET_6_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xf3 => {
            /* SET 6,E */
            disassembleCB__SET_6_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xf4 => {
            /* SET 6,H */
            disassembleCB__SET_6_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xf5 => {
            /* SET 6,L */
            disassembleCB__SET_6_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xf6 => {
            /* SET 6,(HL) */
            disassembleCB__SET_6_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xf7 => {
            /* SET 6,A */
            disassembleCB__SET_6_A(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xf8 => {
            /* SET 7,B */
            disassembleCB__SET_7_B(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xf9 => {
            /* SET 7,C */
            disassembleCB__SET_7_C(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xfa => {
            /* SET 7,D */
            disassembleCB__SET_7_D(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xfb => {
            /* SET 7,E */
            disassembleCB__SET_7_E(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xfc => {
            /* SET 7,H */
            disassembleCB__SET_7_H(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xfd => {
            /* SET 7,L */
            disassembleCB__SET_7_L(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xfe => {
            /* SET 7,(HL) */
            disassembleCB__SET_7_iHL(data, memory);
        }

        val if val == SHIFT_0X_CB + 0xff => {
            /* SET 7,A */
            disassembleCB__SET_7_A(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x40 => {
            /* IN B,(C) */
            disassembleED__IN_B_iC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x41 => {
            /* OUT (C),B */
            disassembleED__OUT_iC_B(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x42 => {
            /* SBC HL,BC */
            disassembleED__SBC_HL_BC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x43 => {
            /* LD (nnnn),BC */
            disassembleED__LD_iNNNN_BC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x7c => {
            /* NEG */
            disassembleED__NEG(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x44 => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c](data, memory);
            disassembleED__NEG(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x4c => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c](data, memory);
            disassembleED__NEG(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x54 => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c](data, memory);
            disassembleED__NEG(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x5c => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c](data, memory);
            disassembleED__NEG(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x64 => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c](data, memory);
            disassembleED__NEG(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x6c => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c](data, memory);
            disassembleED__NEG(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x74 => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c](data, memory);
            disassembleED__NEG(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x7d => {
            /* RETN */
            disassembleED__RETN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x45 => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d](data, memory);
            disassembleED__RETN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x4d => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d](data, memory);
            disassembleED__RETN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x55 => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d](data, memory);
            disassembleED__RETN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x5d => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d](data, memory);
            disassembleED__RETN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x65 => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d](data, memory);
            disassembleED__RETN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x6d => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d](data, memory);
            disassembleED__RETN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x75 => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d](data, memory);
            disassembleED__RETN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x6e => {
            /* IM 0 */
            disassembleED__IM_0(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x46 => {
            /* IM 0 */
            // self.OpcodesMap[SHIFT_0xED + 0x6e](data, memory);
            disassembleED__IM_0(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x4e => {
            /* IM 0 */
            // self.OpcodesMap[SHIFT_0xED + 0x6e](data, memory);
            disassembleED__IM_0(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x66 => {
            /* IM 0 */
            // self.OpcodesMap[SHIFT_0xED + 0x6e](data, memory);
            disassembleED__IM_0(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x47 => {
            /* LD I,A */
            disassembleED__LD_I_A(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x48 => {
            /* IN C,(C) */
            disassembleED__IN_C_iC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x49 => {
            /* OUT (C),C */
            disassembleED__OUT_iC_C(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x4a => {
            /* ADC HL,BC */
            disassembleED__ADC_HL_BC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x4b => {
            /* LD BC,(nnnn) */
            disassembleED__LD_BC_iNNNN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x4f => {
            /* LD R,A */
            disassembleED__LD_R_A(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x50 => {
            /* IN D,(C) */
            disassembleED__IN_D_iC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x51 => {
            /* OUT (C),D */
            disassembleED__OUT_iC_D(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x52 => {
            /* SBC HL,DE */
            disassembleED__SBC_HL_DE(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x53 => {
            /* LD (nnnn),DE */
            disassembleED__LD_iNNNN_DE(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x76 => {
            /* IM 1 */
            disassembleED__IM_1(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x56 => {
            /* IM 1 */
            // self.OpcodesMap[SHIFT_0xED + 0x76](data, memory);
            disassembleED__IM_1(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x57 => {
            /* LD A,I */
            disassembleED__LD_A_I(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x58 => {
            /* IN E,(C) */
            disassembleED__IN_E_iC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x59 => {
            /* OUT (C),E */
            disassembleED__OUT_iC_E(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x5a => {
            /* ADC HL,DE */
            disassembleED__ADC_HL_DE(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x5b => {
            /* LD DE,(nnnn) */
            disassembleED__LD_DE_iNNNN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x7e => {
            /* IM 2 */
            disassembleED__IM_2(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x5e => {
            /* IM 2 */
            // self.OpcodesMap[SHIFT_0xED + 0x7e](data, memory);
            disassembleED__IM_2(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x5f => {
            /* LD A,R */
            disassembleED__LD_A_R(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x60 => {
            /* IN H,(C) */
            disassembleED__IN_H_iC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x61 => {
            /* OUT (C),H */
            disassembleED__OUT_iC_H(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x62 => {
            /* SBC HL,HL */
            disassembleED__SBC_HL_HL(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x63 => {
            /* LD (nnnn),HL */
            disassembleED__LD_iNNNN_HL(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x67 => {
            /* RRD */
            disassembleED__RRD(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x68 => {
            /* IN L,(C) */
            disassembleED__IN_L_iC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x69 => {
            /* OUT (C),L */
            disassembleED__OUT_iC_L(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x6a => {
            /* ADC HL,HL */
            disassembleED__ADC_HL_HL(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x6b => {
            /* LD HL,(nnnn) */
            disassembleED__LD_HL_iNNNN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x6f => {
            /* RLD */
            disassembleED__RLD(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x70 => {
            /* IN F,(C) */
            disassembleED__IN_F_iC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x71 => {
            /* OUT (C),0 */
            disassembleED__OUT_iC_0(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x72 => {
            /* SBC HL,SP */
            disassembleED__SBC_HL_SP(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x73 => {
            /* LD (nnnn),SP */
            disassembleED__LD_iNNNN_SP(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x78 => {
            /* IN A,(C) */
            disassembleED__IN_A_iC(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x79 => {
            /* OUT (C),A */
            disassembleED__OUT_iC_A(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x7a => {
            /* ADC HL,SP */
            disassembleED__ADC_HL_SP(data, memory);
        }

        val if val == SHIFT_0X_ED + 0x7b => {
            /* LD SP,(nnnn) */
            disassembleED__LD_SP_iNNNN(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xa0 => {
            /* LDI */
            disassembleED__LDI(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xa1 => {
            /* CPI */
            disassembleED__CPI(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xa2 => {
            /* INI */
            disassembleED__INI(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xa3 => {
            /* OUTI */
            disassembleED__OUTI(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xa8 => {
            /* LDD */
            disassembleED__LDD(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xa9 => {
            /* CPD */
            disassembleED__CPD(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xaa => {
            /* IND */
            disassembleED__IND(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xab => {
            /* OUTD */
            disassembleED__OUTD(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xb0 => {
            /* LDIR */
            disassembleED__LDIR(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xb1 => {
            /* CPIR */
            disassembleED__CPIR(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xb2 => {
            /* INIR */
            disassembleED__INIR(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xb3 => {
            /* OTIR */
            disassembleED__OTIR(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xb8 => {
            /* LDDR */
            disassembleED__LDDR(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xb9 => {
            /* CPDR */
            disassembleED__CPDR(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xba => {
            /* INDR */
            disassembleED__INDR(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xbb => {
            /* OTDR */
            disassembleED__OTDR(data, memory);
        }

        val if val == SHIFT_0X_ED + 0xfb => {
            /* slttrap */
            disassembleED__SLTTRAP(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x09 => {
            /* ADD REGISTER,BC */
            disassembleDD__ADD_REG_BC(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x19 => {
            /* ADD REGISTER,DE */
            disassembleDD__ADD_REG_DE(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x21 => {
            /* LD REGISTER,nnnn */
            disassembleDD__LD_REG_NNNN(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x22 => {
            /* LD (nnnn),REGISTER */
            disassembleDD__LD_iNNNN_REG(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x23 => {
            /* INC REGISTER */
            disassembleDD__INC_REG(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x24 => {
            /* INC REGISTERH */
            disassembleDD__INC_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x25 => {
            /* DEC REGISTERH */
            disassembleDD__DEC_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x26 => {
            /* LD REGISTERH,nn */
            disassembleDD__LD_REGH_NN(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x29 => {
            /* ADD REGISTER,REGISTER */
            disassembleDD__ADD_REG_REG(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x2a => {
            /* LD REGISTER,(nnnn) */
            disassembleDD__LD_REG_iNNNN(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x2b => {
            /* DEC REGISTER */
            disassembleDD__DEC_REG(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x2c => {
            /* INC REGISTERL */
            disassembleDD__INC_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x2d => {
            /* DEC REGISTERL */
            disassembleDD__DEC_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x2e => {
            /* LD REGISTERL,nn */
            disassembleDD__LD_REGL_NN(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x34 => {
            /* INC (REGISTER+dd) */
            disassembleDD__INC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x35 => {
            /* DEC (REGISTER+dd) */
            disassembleDD__DEC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x36 => {
            /* LD (REGISTER+dd),nn */
            disassembleDD__LD_iREGpDD_NN(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x39 => {
            /* ADD REGISTER,SP */
            disassembleDD__ADD_REG_SP(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x44 => {
            /* LD B,REGISTERH */
            disassembleDD__LD_B_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x45 => {
            /* LD B,REGISTERL */
            disassembleDD__LD_B_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x46 => {
            /* LD B,(REGISTER+dd) */
            disassembleDD__LD_B_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x4c => {
            /* LD C,REGISTERH */
            disassembleDD__LD_C_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x4d => {
            /* LD C,REGISTERL */
            disassembleDD__LD_C_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x4e => {
            /* LD C,(REGISTER+dd) */
            disassembleDD__LD_C_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x54 => {
            /* LD D,REGISTERH */
            disassembleDD__LD_D_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x55 => {
            /* LD D,REGISTERL */
            disassembleDD__LD_D_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x56 => {
            /* LD D,(REGISTER+dd) */
            disassembleDD__LD_D_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x5c => {
            /* LD E,REGISTERH */
            disassembleDD__LD_E_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x5d => {
            /* LD E,REGISTERL */
            disassembleDD__LD_E_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x5e => {
            /* LD E,(REGISTER+dd) */
            disassembleDD__LD_E_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x60 => {
            /* LD REGISTERH,B */
            disassembleDD__LD_REGH_B(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x61 => {
            /* LD REGISTERH,C */
            disassembleDD__LD_REGH_C(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x62 => {
            /* LD REGISTERH,D */
            disassembleDD__LD_REGH_D(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x63 => {
            /* LD REGISTERH,E */
            disassembleDD__LD_REGH_E(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x64 => {
            /* LD REGISTERH,REGISTERH */
            disassembleDD__LD_REGH_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x65 => {
            /* LD REGISTERH,REGISTERL */
            disassembleDD__LD_REGH_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x66 => {
            /* LD H,(REGISTER+dd) */
            disassembleDD__LD_H_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x67 => {
            /* LD REGISTERH,A */
            disassembleDD__LD_REGH_A(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x68 => {
            /* LD REGISTERL,B */
            disassembleDD__LD_REGL_B(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x69 => {
            /* LD REGISTERL,C */
            disassembleDD__LD_REGL_C(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x6a => {
            /* LD REGISTERL,D */
            disassembleDD__LD_REGL_D(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x6b => {
            /* LD REGISTERL,E */
            disassembleDD__LD_REGL_E(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x6c => {
            /* LD REGISTERL,REGISTERH */
            disassembleDD__LD_REGL_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x6d => {
            /* LD REGISTERL,REGISTERL */
            disassembleDD__LD_REGL_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x6e => {
            /* LD L,(REGISTER+dd) */
            disassembleDD__LD_L_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x6f => {
            /* LD REGISTERL,A */
            disassembleDD__LD_REGL_A(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x70 => {
            /* LD (REGISTER+dd),B */
            disassembleDD__LD_iREGpDD_B(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x71 => {
            /* LD (REGISTER+dd),C */
            disassembleDD__LD_iREGpDD_C(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x72 => {
            /* LD (REGISTER+dd),D */
            disassembleDD__LD_iREGpDD_D(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x73 => {
            /* LD (REGISTER+dd),E */
            disassembleDD__LD_iREGpDD_E(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x74 => {
            /* LD (REGISTER+dd),H */
            disassembleDD__LD_iREGpDD_H(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x75 => {
            /* LD (REGISTER+dd),L */
            disassembleDD__LD_iREGpDD_L(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x77 => {
            /* LD (REGISTER+dd),A */
            disassembleDD__LD_iREGpDD_A(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x7c => {
            /* LD A,REGISTERH */
            disassembleDD__LD_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x7d => {
            /* LD A,REGISTERL */
            disassembleDD__LD_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x7e => {
            /* LD A,(REGISTER+dd) */
            disassembleDD__LD_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x84 => {
            /* ADD A,REGISTERH */
            disassembleDD__ADD_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x85 => {
            /* ADD A,REGISTERL */
            disassembleDD__ADD_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x86 => {
            /* ADD A,(REGISTER+dd) */
            disassembleDD__ADD_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x8c => {
            /* ADC A,REGISTERH */
            disassembleDD__ADC_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x8d => {
            /* ADC A,REGISTERL */
            disassembleDD__ADC_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x8e => {
            /* ADC A,(REGISTER+dd) */
            disassembleDD__ADC_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x94 => {
            /* SUB A,REGISTERH */
            disassembleDD__SUB_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x95 => {
            /* SUB A,REGISTERL */
            disassembleDD__SUB_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x96 => {
            /* SUB A,(REGISTER+dd) */
            disassembleDD__SUB_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x9c => {
            /* SBC A,REGISTERH */
            disassembleDD__SBC_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x9d => {
            /* SBC A,REGISTERL */
            disassembleDD__SBC_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0x9e => {
            /* SBC A,(REGISTER+dd) */
            disassembleDD__SBC_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xa4 => {
            /* AND A,REGISTERH */
            disassembleDD__AND_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xa5 => {
            /* AND A,REGISTERL */
            disassembleDD__AND_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xa6 => {
            /* AND A,(REGISTER+dd) */
            disassembleDD__AND_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xac => {
            /* XOR A,REGISTERH */
            disassembleDD__XOR_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xad => {
            /* XOR A,REGISTERL */
            disassembleDD__XOR_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xae => {
            /* XOR A,(REGISTER+dd) */
            disassembleDD__XOR_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xb4 => {
            /* OR A,REGISTERH */
            disassembleDD__OR_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xb5 => {
            /* OR A,REGISTERL */
            disassembleDD__OR_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xb6 => {
            /* OR A,(REGISTER+dd) */
            disassembleDD__OR_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xbc => {
            /* CP A,REGISTERH */
            disassembleDD__CP_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xbd => {
            /* CP A,REGISTERL */
            disassembleDD__CP_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xbe => {
            /* CP A,(REGISTER+dd) */
            disassembleDD__CP_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xcb => {
            /* shift DDFDCB */
            disassembleDD__SHIFT_DDFDCB(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xe1 => {
            /* POP REGISTER */
            disassembleDD__POP_REG(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xe3 => {
            /* EX (SP),REGISTER */
            disassembleDD__EX_iSP_REG(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xe5 => {
            /* PUSH REGISTER */
            disassembleDD__PUSH_REG(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xe9 => {
            /* JP REGISTER */
            disassembleDD__JP_REG(data, memory);
        }

        val if val == SHIFT_0X_DD + 0xf9 => {
            /* LD SP,REGISTER */
            disassembleDD__LD_SP_REG(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x09 => {
            /* ADD REGISTER,BC */
            disassembleFD__ADD_REG_BC(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x19 => {
            /* ADD REGISTER,DE */
            disassembleFD__ADD_REG_DE(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x21 => {
            /* LD REGISTER,nnnn */
            disassembleFD__LD_REG_NNNN(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x22 => {
            /* LD (nnnn),REGISTER */
            disassembleFD__LD_iNNNN_REG(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x23 => {
            /* INC REGISTER */
            disassembleFD__INC_REG(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x24 => {
            /* INC REGISTERH */
            disassembleFD__INC_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x25 => {
            /* DEC REGISTERH */
            disassembleFD__DEC_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x26 => {
            /* LD REGISTERH,nn */
            disassembleFD__LD_REGH_NN(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x29 => {
            /* ADD REGISTER,REGISTER */
            disassembleFD__ADD_REG_REG(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x2a => {
            /* LD REGISTER,(nnnn) */
            disassembleFD__LD_REG_iNNNN(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x2b => {
            /* DEC REGISTER */
            disassembleFD__DEC_REG(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x2c => {
            /* INC REGISTERL */
            disassembleFD__INC_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x2d => {
            /* DEC REGISTERL */
            disassembleFD__DEC_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x2e => {
            /* LD REGISTERL,nn */
            disassembleFD__LD_REGL_NN(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x34 => {
            /* INC (REGISTER+dd) */
            disassembleFD__INC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x35 => {
            /* DEC (REGISTER+dd) */
            disassembleFD__DEC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x36 => {
            /* LD (REGISTER+dd),nn */
            disassembleFD__LD_iREGpDD_NN(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x39 => {
            /* ADD REGISTER,SP */
            disassembleFD__ADD_REG_SP(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x44 => {
            /* LD B,REGISTERH */
            disassembleFD__LD_B_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x45 => {
            /* LD B,REGISTERL */
            disassembleFD__LD_B_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x46 => {
            /* LD B,(REGISTER+dd) */
            disassembleFD__LD_B_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x4c => {
            /* LD C,REGISTERH */
            disassembleFD__LD_C_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x4d => {
            /* LD C,REGISTERL */
            disassembleFD__LD_C_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x4e => {
            /* LD C,(REGISTER+dd) */
            disassembleFD__LD_C_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x54 => {
            /* LD D,REGISTERH */
            disassembleFD__LD_D_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x55 => {
            /* LD D,REGISTERL */
            disassembleFD__LD_D_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x56 => {
            /* LD D,(REGISTER+dd) */
            disassembleFD__LD_D_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x5c => {
            /* LD E,REGISTERH */
            disassembleFD__LD_E_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x5d => {
            /* LD E,REGISTERL */
            disassembleFD__LD_E_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x5e => {
            /* LD E,(REGISTER+dd) */
            disassembleFD__LD_E_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x60 => {
            /* LD REGISTERH,B */
            disassembleFD__LD_REGH_B(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x61 => {
            /* LD REGISTERH,C */
            disassembleFD__LD_REGH_C(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x62 => {
            /* LD REGISTERH,D */
            disassembleFD__LD_REGH_D(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x63 => {
            /* LD REGISTERH,E */
            disassembleFD__LD_REGH_E(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x64 => {
            /* LD REGISTERH,REGISTERH */
            disassembleFD__LD_REGH_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x65 => {
            /* LD REGISTERH,REGISTERL */
            disassembleFD__LD_REGH_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x66 => {
            /* LD H,(REGISTER+dd) */
            disassembleFD__LD_H_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x67 => {
            /* LD REGISTERH,A */
            disassembleFD__LD_REGH_A(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x68 => {
            /* LD REGISTERL,B */
            disassembleFD__LD_REGL_B(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x69 => {
            /* LD REGISTERL,C */
            disassembleFD__LD_REGL_C(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x6a => {
            /* LD REGISTERL,D */
            disassembleFD__LD_REGL_D(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x6b => {
            /* LD REGISTERL,E */
            disassembleFD__LD_REGL_E(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x6c => {
            /* LD REGISTERL,REGISTERH */
            disassembleFD__LD_REGL_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x6d => {
            /* LD REGISTERL,REGISTERL */
            disassembleFD__LD_REGL_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x6e => {
            /* LD L,(REGISTER+dd) */
            disassembleFD__LD_L_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x6f => {
            /* LD REGISTERL,A */
            disassembleFD__LD_REGL_A(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x70 => {
            /* LD (REGISTER+dd),B */
            disassembleFD__LD_iREGpDD_B(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x71 => {
            /* LD (REGISTER+dd),C */
            disassembleFD__LD_iREGpDD_C(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x72 => {
            /* LD (REGISTER+dd),D */
            disassembleFD__LD_iREGpDD_D(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x73 => {
            /* LD (REGISTER+dd),E */
            disassembleFD__LD_iREGpDD_E(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x74 => {
            /* LD (REGISTER+dd),H */
            disassembleFD__LD_iREGpDD_H(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x75 => {
            /* LD (REGISTER+dd),L */
            disassembleFD__LD_iREGpDD_L(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x77 => {
            /* LD (REGISTER+dd),A */
            disassembleFD__LD_iREGpDD_A(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x7c => {
            /* LD A,REGISTERH */
            disassembleFD__LD_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x7d => {
            /* LD A,REGISTERL */
            disassembleFD__LD_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x7e => {
            /* LD A,(REGISTER+dd) */
            disassembleFD__LD_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x84 => {
            /* ADD A,REGISTERH */
            disassembleFD__ADD_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x85 => {
            /* ADD A,REGISTERL */
            disassembleFD__ADD_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x86 => {
            /* ADD A,(REGISTER+dd) */
            disassembleFD__ADD_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x8c => {
            /* ADC A,REGISTERH */
            disassembleFD__ADC_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x8d => {
            /* ADC A,REGISTERL */
            disassembleFD__ADC_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x8e => {
            /* ADC A,(REGISTER+dd) */
            disassembleFD__ADC_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x94 => {
            /* SUB A,REGISTERH */
            disassembleFD__SUB_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x95 => {
            /* SUB A,REGISTERL */
            disassembleFD__SUB_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x96 => {
            /* SUB A,(REGISTER+dd) */
            disassembleFD__SUB_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x9c => {
            /* SBC A,REGISTERH */
            disassembleFD__SBC_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x9d => {
            /* SBC A,REGISTERL */
            disassembleFD__SBC_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0x9e => {
            /* SBC A,(REGISTER+dd) */
            disassembleFD__SBC_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xa4 => {
            /* AND A,REGISTERH */
            disassembleFD__AND_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xa5 => {
            /* AND A,REGISTERL */
            disassembleFD__AND_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xa6 => {
            /* AND A,(REGISTER+dd) */
            disassembleFD__AND_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xac => {
            /* XOR A,REGISTERH */
            disassembleFD__XOR_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xad => {
            /* XOR A,REGISTERL */
            disassembleFD__XOR_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xae => {
            /* XOR A,(REGISTER+dd) */
            disassembleFD__XOR_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xb4 => {
            /* OR A,REGISTERH */
            disassembleFD__OR_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xb5 => {
            /* OR A,REGISTERL */
            disassembleFD__OR_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xb6 => {
            /* OR A,(REGISTER+dd) */
            disassembleFD__OR_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xbc => {
            /* CP A,REGISTERH */
            disassembleFD__CP_A_REGH(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xbd => {
            /* CP A,REGISTERL */
            disassembleFD__CP_A_REGL(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xbe => {
            /* CP A,(REGISTER+dd) */
            disassembleFD__CP_A_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xcb => {
            /* shift DDFDCB */
            disassembleFD__SHIFT_DDFDCB(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xe1 => {
            /* POP REGISTER */
            disassembleFD__POP_REG(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xe3 => {
            /* EX (SP),REGISTER */
            disassembleFD__EX_iSP_REG(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xe5 => {
            /* PUSH REGISTER */
            disassembleFD__PUSH_REG(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xe9 => {
            /* JP REGISTER */
            disassembleFD__JP_REG(data, memory);
        }

        val if val == SHIFT_0X_FD + 0xf9 => {
            /* LD SP,REGISTER */
            disassembleFD__LD_SP_REG(data, memory);
        }

        val if val == SHIFT_0X_DDCB => {
            /* LD B,RLC (REGISTER+dd) */
            disassembleDDCB__LD_B_RLC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x01 => {
            /* LD C,RLC (REGISTER+dd) */
            disassembleDDCB__LD_C_RLC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x02 => {
            /* LD D,RLC (REGISTER+dd) */
            disassembleDDCB__LD_D_RLC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x03 => {
            /* LD E,RLC (REGISTER+dd) */
            disassembleDDCB__LD_E_RLC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x04 => {
            /* LD H,RLC (REGISTER+dd) */
            disassembleDDCB__LD_H_RLC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x05 => {
            /* LD L,RLC (REGISTER+dd) */
            disassembleDDCB__LD_L_RLC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x06 => {
            /* RLC (REGISTER+dd) */
            disassembleDDCB__RLC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x07 => {
            /* LD A,RLC (REGISTER+dd) */
            disassembleDDCB__LD_A_RLC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x08 => {
            /* LD B,RRC (REGISTER+dd) */
            disassembleDDCB__LD_B_RRC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x09 => {
            /* LD C,RRC (REGISTER+dd) */
            disassembleDDCB__LD_C_RRC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x0a => {
            /* LD D,RRC (REGISTER+dd) */
            disassembleDDCB__LD_D_RRC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x0b => {
            /* LD E,RRC (REGISTER+dd) */
            disassembleDDCB__LD_E_RRC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x0c => {
            /* LD H,RRC (REGISTER+dd) */
            disassembleDDCB__LD_H_RRC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x0d => {
            /* LD L,RRC (REGISTER+dd) */
            disassembleDDCB__LD_L_RRC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x0e => {
            /* RRC (REGISTER+dd) */
            disassembleDDCB__RRC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x0f => {
            /* LD A,RRC (REGISTER+dd) */
            disassembleDDCB__LD_A_RRC_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x10 => {
            /* LD B,RL (REGISTER+dd) */
            disassembleDDCB__LD_B_RL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x11 => {
            /* LD C,RL (REGISTER+dd) */
            disassembleDDCB__LD_C_RL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x12 => {
            /* LD D,RL (REGISTER+dd) */
            disassembleDDCB__LD_D_RL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x13 => {
            /* LD E,RL (REGISTER+dd) */
            disassembleDDCB__LD_E_RL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x14 => {
            /* LD H,RL (REGISTER+dd) */
            disassembleDDCB__LD_H_RL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x15 => {
            /* LD L,RL (REGISTER+dd) */
            disassembleDDCB__LD_L_RL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x16 => {
            /* RL (REGISTER+dd) */
            disassembleDDCB__RL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x17 => {
            /* LD A,RL (REGISTER+dd) */
            disassembleDDCB__LD_A_RL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x18 => {
            /* LD B,RR (REGISTER+dd) */
            disassembleDDCB__LD_B_RR_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x19 => {
            /* LD C,RR (REGISTER+dd) */
            disassembleDDCB__LD_C_RR_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x1a => {
            /* LD D,RR (REGISTER+dd) */
            disassembleDDCB__LD_D_RR_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x1b => {
            /* LD E,RR (REGISTER+dd) */
            disassembleDDCB__LD_E_RR_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x1c => {
            /* LD H,RR (REGISTER+dd) */
            disassembleDDCB__LD_H_RR_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x1d => {
            /* LD L,RR (REGISTER+dd) */
            disassembleDDCB__LD_L_RR_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x1e => {
            /* RR (REGISTER+dd) */
            disassembleDDCB__RR_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x1f => {
            /* LD A,RR (REGISTER+dd) */
            disassembleDDCB__LD_A_RR_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x20 => {
            /* LD B,SLA (REGISTER+dd) */
            disassembleDDCB__LD_B_SLA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x21 => {
            /* LD C,SLA (REGISTER+dd) */
            disassembleDDCB__LD_C_SLA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x22 => {
            /* LD D,SLA (REGISTER+dd) */
            disassembleDDCB__LD_D_SLA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x23 => {
            /* LD E,SLA (REGISTER+dd) */
            disassembleDDCB__LD_E_SLA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x24 => {
            /* LD H,SLA (REGISTER+dd) */
            disassembleDDCB__LD_H_SLA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x25 => {
            /* LD L,SLA (REGISTER+dd) */
            disassembleDDCB__LD_L_SLA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x26 => {
            /* SLA (REGISTER+dd) */
            disassembleDDCB__SLA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x27 => {
            /* LD A,SLA (REGISTER+dd) */
            disassembleDDCB__LD_A_SLA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x28 => {
            /* LD B,SRA (REGISTER+dd) */
            disassembleDDCB__LD_B_SRA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x29 => {
            /* LD C,SRA (REGISTER+dd) */
            disassembleDDCB__LD_C_SRA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x2a => {
            /* LD D,SRA (REGISTER+dd) */
            disassembleDDCB__LD_D_SRA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x2b => {
            /* LD E,SRA (REGISTER+dd) */
            disassembleDDCB__LD_E_SRA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x2c => {
            /* LD H,SRA (REGISTER+dd) */
            disassembleDDCB__LD_H_SRA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x2d => {
            /* LD L,SRA (REGISTER+dd) */
            disassembleDDCB__LD_L_SRA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x2e => {
            /* SRA (REGISTER+dd) */
            disassembleDDCB__SRA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x2f => {
            /* LD A,SRA (REGISTER+dd) */
            disassembleDDCB__LD_A_SRA_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x30 => {
            /* LD B,SLL (REGISTER+dd) */
            disassembleDDCB__LD_B_SLL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x31 => {
            /* LD C,SLL (REGISTER+dd) */
            disassembleDDCB__LD_C_SLL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x32 => {
            /* LD D,SLL (REGISTER+dd) */
            disassembleDDCB__LD_D_SLL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x33 => {
            /* LD E,SLL (REGISTER+dd) */
            disassembleDDCB__LD_E_SLL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x34 => {
            /* LD H,SLL (REGISTER+dd) */
            disassembleDDCB__LD_H_SLL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x35 => {
            /* LD L,SLL (REGISTER+dd) */
            disassembleDDCB__LD_L_SLL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x36 => {
            /* SLL (REGISTER+dd) */
            disassembleDDCB__SLL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x37 => {
            /* LD A,SLL (REGISTER+dd) */
            disassembleDDCB__LD_A_SLL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x38 => {
            /* LD B,SRL (REGISTER+dd) */
            disassembleDDCB__LD_B_SRL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x39 => {
            /* LD C,SRL (REGISTER+dd) */
            disassembleDDCB__LD_C_SRL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x3a => {
            /* LD D,SRL (REGISTER+dd) */
            disassembleDDCB__LD_D_SRL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x3b => {
            /* LD E,SRL (REGISTER+dd) */
            disassembleDDCB__LD_E_SRL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x3c => {
            /* LD H,SRL (REGISTER+dd) */
            disassembleDDCB__LD_H_SRL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x3d => {
            /* LD L,SRL (REGISTER+dd) */
            disassembleDDCB__LD_L_SRL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x3e => {
            /* SRL (REGISTER+dd) */
            disassembleDDCB__SRL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x3f => {
            /* LD A,SRL (REGISTER+dd) */
            disassembleDDCB__LD_A_SRL_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x47 => {
            /* BIT 0,(REGISTER+dd) */
            disassembleDDCB__BIT_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x40 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47](data, memory);
            disassembleDDCB__BIT_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x41 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47](data, memory);
            disassembleDDCB__BIT_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x42 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47](data, memory);
            disassembleDDCB__BIT_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x43 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47](data, memory);
            disassembleDDCB__BIT_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x44 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47](data, memory);
            disassembleDDCB__BIT_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x45 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47](data, memory);
            disassembleDDCB__BIT_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x46 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47](data, memory);
            disassembleDDCB__BIT_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x4f => {
            /* BIT 1,(REGISTER+dd) */
            disassembleDDCB__BIT_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x48 => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f](data, memory);
            disassembleDDCB__BIT_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x49 => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f](data, memory);
            disassembleDDCB__BIT_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x4a => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f](data, memory);
            disassembleDDCB__BIT_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x4b => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f](data, memory);
            disassembleDDCB__BIT_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x4c => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f](data, memory);
            disassembleDDCB__BIT_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x4d => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f](data, memory);
            disassembleDDCB__BIT_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x4e => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f](data, memory);
            disassembleDDCB__BIT_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x57 => {
            /* BIT 2,(REGISTER+dd) */
            disassembleDDCB__BIT_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x50 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57](data, memory);
            disassembleDDCB__BIT_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x51 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57](data, memory);
            disassembleDDCB__BIT_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x52 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57](data, memory);
            disassembleDDCB__BIT_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x53 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57](data, memory);
            disassembleDDCB__BIT_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x54 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57](data, memory);
            disassembleDDCB__BIT_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x55 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57](data, memory);
            disassembleDDCB__BIT_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x56 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57](data, memory);
            disassembleDDCB__BIT_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x5f => {
            /* BIT 3,(REGISTER+dd) */
            disassembleDDCB__BIT_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x58 => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f](data, memory);
            disassembleDDCB__BIT_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x59 => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f](data, memory);
            disassembleDDCB__BIT_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x5a => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f](data, memory);
            disassembleDDCB__BIT_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x5b => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f](data, memory);
            disassembleDDCB__BIT_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x5c => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f](data, memory);
            disassembleDDCB__BIT_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x5d => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f](data, memory);
            disassembleDDCB__BIT_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x5e => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f](data, memory);
            disassembleDDCB__BIT_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x67 => {
            /* BIT 4,(REGISTER+dd) */
            disassembleDDCB__BIT_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x60 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67](data, memory);
            disassembleDDCB__BIT_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x61 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67](data, memory);
            disassembleDDCB__BIT_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x62 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67](data, memory);
            disassembleDDCB__BIT_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x63 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67](data, memory);
            disassembleDDCB__BIT_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x64 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67](data, memory);
            disassembleDDCB__BIT_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x65 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67](data, memory);
            disassembleDDCB__BIT_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x66 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67](data, memory);
            disassembleDDCB__BIT_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x6f => {
            /* BIT 5,(REGISTER+dd) */
            disassembleDDCB__BIT_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x68 => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f](data, memory);
            disassembleDDCB__BIT_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x69 => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f](data, memory);
            disassembleDDCB__BIT_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x6a => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f](data, memory);
            disassembleDDCB__BIT_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x6b => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f](data, memory);
            disassembleDDCB__BIT_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x6c => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f](data, memory);
            disassembleDDCB__BIT_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x6d => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f](data, memory);
            disassembleDDCB__BIT_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x6e => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f](data, memory);
            disassembleDDCB__BIT_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x77 => {
            /* BIT 6,(REGISTER+dd) */
            disassembleDDCB__BIT_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x70 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77](data, memory);
            disassembleDDCB__BIT_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x71 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77](data, memory);
            disassembleDDCB__BIT_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x72 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77](data, memory);
            disassembleDDCB__BIT_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x73 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77](data, memory);
            disassembleDDCB__BIT_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x74 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77](data, memory);
            disassembleDDCB__BIT_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x75 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77](data, memory);
            disassembleDDCB__BIT_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x76 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77](data, memory);
            disassembleDDCB__BIT_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x7f => {
            /* BIT 7,(REGISTER+dd) */
            disassembleDDCB__BIT_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x78 => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f](data, memory);
            disassembleDDCB__BIT_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x79 => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f](data, memory);
            disassembleDDCB__BIT_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x7a => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f](data, memory);
            disassembleDDCB__BIT_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x7b => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f](data, memory);
            disassembleDDCB__BIT_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x7c => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f](data, memory);
            disassembleDDCB__BIT_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x7d => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f](data, memory);
            disassembleDDCB__BIT_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x7e => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f](data, memory);
            disassembleDDCB__BIT_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x80 => {
            /* LD B,RES 0,(REGISTER+dd) */
            disassembleDDCB__LD_B_RES_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x81 => {
            /* LD C,RES 0,(REGISTER+dd) */
            disassembleDDCB__LD_C_RES_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x82 => {
            /* LD D,RES 0,(REGISTER+dd) */
            disassembleDDCB__LD_D_RES_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x83 => {
            /* LD E,RES 0,(REGISTER+dd) */
            disassembleDDCB__LD_E_RES_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x84 => {
            /* LD H,RES 0,(REGISTER+dd) */
            disassembleDDCB__LD_H_RES_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x85 => {
            /* LD L,RES 0,(REGISTER+dd) */
            disassembleDDCB__LD_L_RES_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x86 => {
            /* RES 0,(REGISTER+dd) */
            disassembleDDCB__RES_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x87 => {
            /* LD A,RES 0,(REGISTER+dd) */
            disassembleDDCB__LD_A_RES_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x88 => {
            /* LD B,RES 1,(REGISTER+dd) */
            disassembleDDCB__LD_B_RES_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x89 => {
            /* LD C,RES 1,(REGISTER+dd) */
            disassembleDDCB__LD_C_RES_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x8a => {
            /* LD D,RES 1,(REGISTER+dd) */
            disassembleDDCB__LD_D_RES_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x8b => {
            /* LD E,RES 1,(REGISTER+dd) */
            disassembleDDCB__LD_E_RES_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x8c => {
            /* LD H,RES 1,(REGISTER+dd) */
            disassembleDDCB__LD_H_RES_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x8d => {
            /* LD L,RES 1,(REGISTER+dd) */
            disassembleDDCB__LD_L_RES_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x8e => {
            /* RES 1,(REGISTER+dd) */
            disassembleDDCB__RES_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x8f => {
            /* LD A,RES 1,(REGISTER+dd) */
            disassembleDDCB__LD_A_RES_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x90 => {
            /* LD B,RES 2,(REGISTER+dd) */
            disassembleDDCB__LD_B_RES_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x91 => {
            /* LD C,RES 2,(REGISTER+dd) */
            disassembleDDCB__LD_C_RES_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x92 => {
            /* LD D,RES 2,(REGISTER+dd) */
            disassembleDDCB__LD_D_RES_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x93 => {
            /* LD E,RES 2,(REGISTER+dd) */
            disassembleDDCB__LD_E_RES_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x94 => {
            /* LD H,RES 2,(REGISTER+dd) */
            disassembleDDCB__LD_H_RES_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x95 => {
            /* LD L,RES 2,(REGISTER+dd) */
            disassembleDDCB__LD_L_RES_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x96 => {
            /* RES 2,(REGISTER+dd) */
            disassembleDDCB__RES_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x97 => {
            /* LD A,RES 2,(REGISTER+dd) */
            disassembleDDCB__LD_A_RES_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x98 => {
            /* LD B,RES 3,(REGISTER+dd) */
            disassembleDDCB__LD_B_RES_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x99 => {
            /* LD C,RES 3,(REGISTER+dd) */
            disassembleDDCB__LD_C_RES_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x9a => {
            /* LD D,RES 3,(REGISTER+dd) */
            disassembleDDCB__LD_D_RES_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x9b => {
            /* LD E,RES 3,(REGISTER+dd) */
            disassembleDDCB__LD_E_RES_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x9c => {
            /* LD H,RES 3,(REGISTER+dd) */
            disassembleDDCB__LD_H_RES_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x9d => {
            /* LD L,RES 3,(REGISTER+dd) */
            disassembleDDCB__LD_L_RES_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x9e => {
            /* RES 3,(REGISTER+dd) */
            disassembleDDCB__RES_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0x9f => {
            /* LD A,RES 3,(REGISTER+dd) */
            disassembleDDCB__LD_A_RES_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xa0 => {
            /* LD B,RES 4,(REGISTER+dd) */
            disassembleDDCB__LD_B_RES_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xa1 => {
            /* LD C,RES 4,(REGISTER+dd) */
            disassembleDDCB__LD_C_RES_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xa2 => {
            /* LD D,RES 4,(REGISTER+dd) */
            disassembleDDCB__LD_D_RES_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xa3 => {
            /* LD E,RES 4,(REGISTER+dd) */
            disassembleDDCB__LD_E_RES_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xa4 => {
            /* LD H,RES 4,(REGISTER+dd) */
            disassembleDDCB__LD_H_RES_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xa5 => {
            /* LD L,RES 4,(REGISTER+dd) */
            disassembleDDCB__LD_L_RES_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xa6 => {
            /* RES 4,(REGISTER+dd) */
            disassembleDDCB__RES_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xa7 => {
            /* LD A,RES 4,(REGISTER+dd) */
            disassembleDDCB__LD_A_RES_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xa8 => {
            /* LD B,RES 5,(REGISTER+dd) */
            disassembleDDCB__LD_B_RES_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xa9 => {
            /* LD C,RES 5,(REGISTER+dd) */
            disassembleDDCB__LD_C_RES_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xaa => {
            /* LD D,RES 5,(REGISTER+dd) */
            disassembleDDCB__LD_D_RES_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xab => {
            /* LD E,RES 5,(REGISTER+dd) */
            disassembleDDCB__LD_E_RES_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xac => {
            /* LD H,RES 5,(REGISTER+dd) */
            disassembleDDCB__LD_H_RES_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xad => {
            /* LD L,RES 5,(REGISTER+dd) */
            disassembleDDCB__LD_L_RES_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xae => {
            /* RES 5,(REGISTER+dd) */
            disassembleDDCB__RES_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xaf => {
            /* LD A,RES 5,(REGISTER+dd) */
            disassembleDDCB__LD_A_RES_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xb0 => {
            /* LD B,RES 6,(REGISTER+dd) */
            disassembleDDCB__LD_B_RES_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xb1 => {
            /* LD C,RES 6,(REGISTER+dd) */
            disassembleDDCB__LD_C_RES_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xb2 => {
            /* LD D,RES 6,(REGISTER+dd) */
            disassembleDDCB__LD_D_RES_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xb3 => {
            /* LD E,RES 6,(REGISTER+dd) */
            disassembleDDCB__LD_E_RES_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xb4 => {
            /* LD H,RES 6,(REGISTER+dd) */
            disassembleDDCB__LD_H_RES_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xb5 => {
            /* LD L,RES 6,(REGISTER+dd) */
            disassembleDDCB__LD_L_RES_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xb6 => {
            /* RES 6,(REGISTER+dd) */
            disassembleDDCB__RES_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xb7 => {
            /* LD A,RES 6,(REGISTER+dd) */
            disassembleDDCB__LD_A_RES_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xb8 => {
            /* LD B,RES 7,(REGISTER+dd) */
            disassembleDDCB__LD_B_RES_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xb9 => {
            /* LD C,RES 7,(REGISTER+dd) */
            disassembleDDCB__LD_C_RES_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xba => {
            /* LD D,RES 7,(REGISTER+dd) */
            disassembleDDCB__LD_D_RES_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xbb => {
            /* LD E,RES 7,(REGISTER+dd) */
            disassembleDDCB__LD_E_RES_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xbc => {
            /* LD H,RES 7,(REGISTER+dd) */
            disassembleDDCB__LD_H_RES_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xbd => {
            /* LD L,RES 7,(REGISTER+dd) */
            disassembleDDCB__LD_L_RES_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xbe => {
            /* RES 7,(REGISTER+dd) */
            disassembleDDCB__RES_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xbf => {
            /* LD A,RES 7,(REGISTER+dd) */
            disassembleDDCB__LD_A_RES_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xc0 => {
            /* LD B,SET 0,(REGISTER+dd) */
            disassembleDDCB__LD_B_SET_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xc1 => {
            /* LD C,SET 0,(REGISTER+dd) */
            disassembleDDCB__LD_C_SET_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xc2 => {
            /* LD D,SET 0,(REGISTER+dd) */
            disassembleDDCB__LD_D_SET_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xc3 => {
            /* LD E,SET 0,(REGISTER+dd) */
            disassembleDDCB__LD_E_SET_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xc4 => {
            /* LD H,SET 0,(REGISTER+dd) */
            disassembleDDCB__LD_H_SET_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xc5 => {
            /* LD L,SET 0,(REGISTER+dd) */
            disassembleDDCB__LD_L_SET_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xc6 => {
            /* SET 0,(REGISTER+dd) */
            disassembleDDCB__SET_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xc7 => {
            /* LD A,SET 0,(REGISTER+dd) */
            disassembleDDCB__LD_A_SET_0_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xc8 => {
            /* LD B,SET 1,(REGISTER+dd) */
            disassembleDDCB__LD_B_SET_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xc9 => {
            /* LD C,SET 1,(REGISTER+dd) */
            disassembleDDCB__LD_C_SET_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xca => {
            /* LD D,SET 1,(REGISTER+dd) */
            disassembleDDCB__LD_D_SET_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xcb => {
            /* LD E,SET 1,(REGISTER+dd) */
            disassembleDDCB__LD_E_SET_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xcc => {
            /* LD H,SET 1,(REGISTER+dd) */
            disassembleDDCB__LD_H_SET_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xcd => {
            /* LD L,SET 1,(REGISTER+dd) */
            disassembleDDCB__LD_L_SET_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xce => {
            /* SET 1,(REGISTER+dd) */
            disassembleDDCB__SET_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xcf => {
            /* LD A,SET 1,(REGISTER+dd) */
            disassembleDDCB__LD_A_SET_1_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xd0 => {
            /* LD B,SET 2,(REGISTER+dd) */
            disassembleDDCB__LD_B_SET_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xd1 => {
            /* LD C,SET 2,(REGISTER+dd) */
            disassembleDDCB__LD_C_SET_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xd2 => {
            /* LD D,SET 2,(REGISTER+dd) */
            disassembleDDCB__LD_D_SET_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xd3 => {
            /* LD E,SET 2,(REGISTER+dd) */
            disassembleDDCB__LD_E_SET_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xd4 => {
            /* LD H,SET 2,(REGISTER+dd) */
            disassembleDDCB__LD_H_SET_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xd5 => {
            /* LD L,SET 2,(REGISTER+dd) */
            disassembleDDCB__LD_L_SET_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xd6 => {
            /* SET 2,(REGISTER+dd) */
            disassembleDDCB__SET_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xd7 => {
            /* LD A,SET 2,(REGISTER+dd) */
            disassembleDDCB__LD_A_SET_2_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xd8 => {
            /* LD B,SET 3,(REGISTER+dd) */
            disassembleDDCB__LD_B_SET_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xd9 => {
            /* LD C,SET 3,(REGISTER+dd) */
            disassembleDDCB__LD_C_SET_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xda => {
            /* LD D,SET 3,(REGISTER+dd) */
            disassembleDDCB__LD_D_SET_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xdb => {
            /* LD E,SET 3,(REGISTER+dd) */
            disassembleDDCB__LD_E_SET_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xdc => {
            /* LD H,SET 3,(REGISTER+dd) */
            disassembleDDCB__LD_H_SET_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xdd => {
            /* LD L,SET 3,(REGISTER+dd) */
            disassembleDDCB__LD_L_SET_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xde => {
            /* SET 3,(REGISTER+dd) */
            disassembleDDCB__SET_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xdf => {
            /* LD A,SET 3,(REGISTER+dd) */
            disassembleDDCB__LD_A_SET_3_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xe0 => {
            /* LD B,SET 4,(REGISTER+dd) */
            disassembleDDCB__LD_B_SET_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xe1 => {
            /* LD C,SET 4,(REGISTER+dd) */
            disassembleDDCB__LD_C_SET_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xe2 => {
            /* LD D,SET 4,(REGISTER+dd) */
            disassembleDDCB__LD_D_SET_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xe3 => {
            /* LD E,SET 4,(REGISTER+dd) */
            disassembleDDCB__LD_E_SET_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xe4 => {
            /* LD H,SET 4,(REGISTER+dd) */
            disassembleDDCB__LD_H_SET_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xe5 => {
            /* LD L,SET 4,(REGISTER+dd) */
            disassembleDDCB__LD_L_SET_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xe6 => {
            /* SET 4,(REGISTER+dd) */
            disassembleDDCB__SET_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xe7 => {
            /* LD A,SET 4,(REGISTER+dd) */
            disassembleDDCB__LD_A_SET_4_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xe8 => {
            /* LD B,SET 5,(REGISTER+dd) */
            disassembleDDCB__LD_B_SET_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xe9 => {
            /* LD C,SET 5,(REGISTER+dd) */
            disassembleDDCB__LD_C_SET_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xea => {
            /* LD D,SET 5,(REGISTER+dd) */
            disassembleDDCB__LD_D_SET_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xeb => {
            /* LD E,SET 5,(REGISTER+dd) */
            disassembleDDCB__LD_E_SET_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xec => {
            /* LD H,SET 5,(REGISTER+dd) */
            disassembleDDCB__LD_H_SET_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xed => {
            /* LD L,SET 5,(REGISTER+dd) */
            disassembleDDCB__LD_L_SET_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xee => {
            /* SET 5,(REGISTER+dd) */
            disassembleDDCB__SET_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xef => {
            /* LD A,SET 5,(REGISTER+dd) */
            disassembleDDCB__LD_A_SET_5_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xf0 => {
            /* LD B,SET 6,(REGISTER+dd) */
            disassembleDDCB__LD_B_SET_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xf1 => {
            /* LD C,SET 6,(REGISTER+dd) */
            disassembleDDCB__LD_C_SET_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xf2 => {
            /* LD D,SET 6,(REGISTER+dd) */
            disassembleDDCB__LD_D_SET_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xf3 => {
            /* LD E,SET 6,(REGISTER+dd) */
            disassembleDDCB__LD_E_SET_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xf4 => {
            /* LD H,SET 6,(REGISTER+dd) */
            disassembleDDCB__LD_H_SET_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xf5 => {
            /* LD L,SET 6,(REGISTER+dd) */
            disassembleDDCB__LD_L_SET_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xf6 => {
            /* SET 6,(REGISTER+dd) */
            disassembleDDCB__SET_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xf7 => {
            /* LD A,SET 6,(REGISTER+dd) */
            disassembleDDCB__LD_A_SET_6_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xf8 => {
            /* LD B,SET 7,(REGISTER+dd) */
            disassembleDDCB__LD_B_SET_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xf9 => {
            /* LD C,SET 7,(REGISTER+dd) */
            disassembleDDCB__LD_C_SET_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xfa => {
            /* LD D,SET 7,(REGISTER+dd) */
            disassembleDDCB__LD_D_SET_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xfb => {
            /* LD E,SET 7,(REGISTER+dd) */
            disassembleDDCB__LD_E_SET_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xfc => {
            /* LD H,SET 7,(REGISTER+dd) */
            disassembleDDCB__LD_H_SET_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xfd => {
            /* LD L,SET 7,(REGISTER+dd) */
            disassembleDDCB__LD_L_SET_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xfe => {
            /* SET 7,(REGISTER+dd) */
            disassembleDDCB__SET_7_iREGpDD(data, memory);
        }

        val if val == SHIFT_0X_DDCB + 0xff => {
            /* LD A,SET 7,(REGISTER+dd) */
            disassembleDDCB__LD_A_SET_7_iREGpDD(data, memory);
        }

        _ => {
            unimplemented!();
        }
    }
}
/* NOP */
fn disassemble__NOP(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) NOP", address);
}
/* LD BC,nnnn */
fn disassemble__LD_BC_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD BC,0x{:04x}", address, nnnn);
}

/* LD (BC),A */
fn disassemble__LD_iBC_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (BC),A", address);
}

/* INC BC */
fn disassemble__INC_BC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC BC", address);
}

/* INC B */
fn disassemble__INC_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC B", address);
}

/* DEC B */
fn disassemble__DEC_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC B", address);
}

/* LD B,nn */
fn disassemble__LD_B_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,nn", address);
}

/* RLCA */
fn disassemble__RLCA(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLCA", address);
}

/* EX AF,AF' */
fn disassemble__EX_AF_AF(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) EX AF,AF'", address);
}

/* ADD HL,BC */
fn disassemble__ADD_HL_BC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD HL,BC", address);
}

/* LD A,(BC) */
fn disassemble__LD_A_iBC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,(BC)", address);
}

/* DEC BC */
fn disassemble__DEC_BC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC BC", address);
}

/* INC C */
fn disassemble__INC_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC C", address);
}

/* DEC C */
fn disassemble__DEC_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC C", address);
}

/* LD C,nn */
fn disassemble__LD_C_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,nn", address);
}

/* RRCA */
fn disassemble__RRCA(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRCA", address);
}

/* DJNZ offset */
fn disassemble__DJNZ_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DJNZ offset", address);
}

/* LD DE,nnnn */
fn disassemble__LD_DE_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD DE,0x{:04x}", address, nnnn);
}

/* LD (DE),A */
fn disassemble__LD_iDE_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (DE),A", address);
}

/* INC DE */
fn disassemble__INC_DE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC DE", address);
}

/* INC D */
fn disassemble__INC_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC D", address);
}

/* DEC D */
fn disassemble__DEC_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC D", address);
}

/* LD D,nn */
fn disassemble__LD_D_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,nn", address);
}

/* RLA */
fn disassemble__RLA(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLA", address);
}

/* JR offset */
fn disassemble__JR_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let offset = memory.read_byte(address + 1);
    println!("({:04x}) JR 0x{:02x}", address, offset);
}

/* ADD HL,DE */
fn disassemble__ADD_HL_DE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD HL,DE", address);
}

/* LD A,(DE) */
fn disassemble__LD_A_iDE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,(DE)", address);
}

/* DEC DE */
fn disassemble__DEC_DE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC DE", address);
}

/* INC E */
fn disassemble__INC_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC E", address);
}

/* DEC E */
fn disassemble__DEC_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC E", address);
}

/* LD E,nn */
fn disassemble__LD_E_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,nn", address);
}

/* RRA */
fn disassemble__RRA(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRA", address);
}

/* JR NZ,offset */
fn disassemble__JR_NZ_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let offset = memory.read_byte(address + 1);
    println!("({:04x}) JR NZ,0x{:02x}", address, offset);
}

/* LD HL,nnnn */
fn disassemble__LD_HL_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD HL,0x{:04x}", address, nnnn);
}

/* LD (nnnn),HL */
fn disassemble__LD_iNNNN_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD (0x{:04x}),HL", address, nnnn);
}

/* INC HL */
fn disassemble__INC_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC HL", address);
}

/* INC H */
fn disassemble__INC_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC H", address);
}

/* DEC H */
fn disassemble__DEC_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC H", address);
}

/* LD H,nn */
fn disassemble__LD_H_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,nn", address);
}

/* DAA */
fn disassemble__DAA(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DAA", address);
}

/* JR Z,offset */
fn disassemble__JR_Z_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let offset = memory.read_byte(address + 1);
    println!("({:04x}) JR Z,0x{:02x}", address, offset);
}

/* ADD HL,HL */
fn disassemble__ADD_HL_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD HL,HL", address);
}

/* LD HL,(nnnn) */
fn disassemble__LD_HL_iNNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD HL,(0x{:04x})", address, nnnn);
}

/* DEC HL */
fn disassemble__DEC_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC HL", address);
}

/* INC L */
fn disassemble__INC_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC L", address);
}

/* DEC L */
fn disassemble__DEC_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC L", address);
}

/* LD L,nn */
fn disassemble__LD_L_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,nn", address);
}

/* CPL */
fn disassemble__CPL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CPL", address);
}

/* JR NC,offset */
fn disassemble__JR_NC_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let offset = memory.read_byte(address + 1);
    println!("({:04x}) JR NC,0x{:02x}", address, offset);
}

/* LD SP,nnnn */
fn disassemble__LD_SP_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD SP,0x{:04x}", address, nnnn);
}

/* LD (nnnn),A */
fn disassemble__LD_iNNNN_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD (0x{:04x}),A", address, nnnn);
}

/* INC SP */
fn disassemble__INC_SP(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC SP", address);
}

/* INC (HL) */
fn disassemble__INC_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC (HL)", address);
}

/* DEC (HL) */
fn disassemble__DEC_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC (HL)", address);
}

/* LD (HL),nn */
fn disassemble__LD_iHL_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (HL),nn", address);
}

/* SCF */
fn disassemble__SCF(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SCF", address);
}

/* JR C,offset */
fn disassemble__JR_C_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let offset = memory.read_byte(address + 1);
    println!("({:04x}) JR C,0x{:02x}", address, offset);
}

/* ADD HL,SP */
fn disassemble__ADD_HL_SP(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD HL,SP", address);
}

/* LD A,(nnnn) */
fn disassemble__LD_A_iNNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD A,(0x{:04x})", address, nnnn);
}

/* DEC SP */
fn disassemble__DEC_SP(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC SP", address);
}

/* INC A */
fn disassemble__INC_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC A", address);
}

/* DEC A */
fn disassemble__DEC_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC A", address);
}

/* LD A,nn */
fn disassemble__LD_A_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) LD A,0x{:02x}", address, nn);
}

/* CCF */
fn disassemble__CCF(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CCF", address);
}

/* LD B,B */
fn disassemble__LD_B_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,B", address);
}

/* LD B,C */
fn disassemble__LD_B_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,C", address);
}

/* LD B,D */
fn disassemble__LD_B_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,D", address);
}

/* LD B,E */
fn disassemble__LD_B_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,E", address);
}

/* LD B,H */
fn disassemble__LD_B_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,H", address);
}

/* LD B,L */
fn disassemble__LD_B_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,L", address);
}

/* LD B,(HL) */
fn disassemble__LD_B_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,(HL)", address);
}

/* LD B,A */
fn disassemble__LD_B_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,A", address);
}

/* LD C,B */
fn disassemble__LD_C_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,B", address);
}

/* LD C,C */
fn disassemble__LD_C_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,C", address);
}

/* LD C,D */
fn disassemble__LD_C_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,D", address);
}

/* LD C,E */
fn disassemble__LD_C_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,E", address);
}

/* LD C,H */
fn disassemble__LD_C_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,H", address);
}

/* LD C,L */
fn disassemble__LD_C_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,L", address);
}

/* LD C,(HL) */
fn disassemble__LD_C_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,(HL)", address);
}

/* LD C,A */
fn disassemble__LD_C_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,A", address);
}

/* LD D,B */
fn disassemble__LD_D_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,B", address);
}

/* LD D,C */
fn disassemble__LD_D_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,C", address);
}

/* LD D,D */
fn disassemble__LD_D_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,D", address);
}

/* LD D,E */
fn disassemble__LD_D_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,E", address);
}

/* LD D,H */
fn disassemble__LD_D_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,H", address);
}

/* LD D,L */
fn disassemble__LD_D_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,L", address);
}

/* LD D,(HL) */
fn disassemble__LD_D_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,(HL)", address);
}

/* LD D,A */
fn disassemble__LD_D_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,A", address);
}

/* LD E,B */
fn disassemble__LD_E_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,B", address);
}

/* LD E,C */
fn disassemble__LD_E_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,C", address);
}

/* LD E,D */
fn disassemble__LD_E_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,D", address);
}

/* LD E,E */
fn disassemble__LD_E_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,E", address);
}

/* LD E,H */
fn disassemble__LD_E_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,H", address);
}

/* LD E,L */
fn disassemble__LD_E_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,L", address);
}

/* LD E,(HL) */
fn disassemble__LD_E_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,(HL)", address);
}

/* LD E,A */
fn disassemble__LD_E_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,A", address);
}

/* LD H,B */
fn disassemble__LD_H_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,B", address);
}

/* LD H,C */
fn disassemble__LD_H_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,C", address);
}

/* LD H,D */
fn disassemble__LD_H_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,D", address);
}

/* LD H,E */
fn disassemble__LD_H_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,E", address);
}

/* LD H,H */
fn disassemble__LD_H_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,H", address);
}

/* LD H,L */
fn disassemble__LD_H_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,L", address);
}

/* LD H,(HL) */
fn disassemble__LD_H_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,(HL)", address);
}

/* LD H,A */
fn disassemble__LD_H_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,A", address);
}

/* LD L,B */
fn disassemble__LD_L_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,B", address);
}

/* LD L,C */
fn disassemble__LD_L_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,C", address);
}

/* LD L,D */
fn disassemble__LD_L_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,D", address);
}

/* LD L,E */
fn disassemble__LD_L_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,E", address);
}

/* LD L,H */
fn disassemble__LD_L_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,H", address);
}

/* LD L,L */
fn disassemble__LD_L_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,L", address);
}

/* LD L,(HL) */
fn disassemble__LD_L_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,(HL)", address);
}

/* LD L,A */
fn disassemble__LD_L_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,A", address);
}

/* LD (HL),B */
fn disassemble__LD_iHL_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (HL),B", address);
}

/* LD (HL),C */
fn disassemble__LD_iHL_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (HL),C", address);
}

/* LD (HL),D */
fn disassemble__LD_iHL_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (HL),D", address);
}

/* LD (HL),E */
fn disassemble__LD_iHL_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (HL),E", address);
}

/* LD (HL),H */
fn disassemble__LD_iHL_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (HL),H", address);
}

/* LD (HL),L */
fn disassemble__LD_iHL_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (HL),L", address);
}

/* HALT */
fn disassemble__HALT(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) HALT", address);
}

/* LD (HL),A */
fn disassemble__LD_iHL_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (HL),A", address);
}

/* LD A,B */
fn disassemble__LD_A_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,B", address);
}

/* LD A,C */
fn disassemble__LD_A_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,C", address);
}

/* LD A,D */
fn disassemble__LD_A_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,D", address);
}

/* LD A,E */
fn disassemble__LD_A_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,E", address);
}

/* LD A,H */
fn disassemble__LD_A_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,H", address);
}

/* LD A,L */
fn disassemble__LD_A_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,L", address);
}

/* LD A,(HL) */
fn disassemble__LD_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,(HL)", address);
}

/* LD A,A */
fn disassemble__LD_A_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,A", address);
}

/* ADD A,B */
fn disassemble__ADD_A_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,B", address);
}

/* ADD A,C */
fn disassemble__ADD_A_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,C", address);
}

/* ADD A,D */
fn disassemble__ADD_A_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,D", address);
}

/* ADD A,E */
fn disassemble__ADD_A_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,E", address);
}

/* ADD A,H */
fn disassemble__ADD_A_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,H", address);
}

/* ADD A,L */
fn disassemble__ADD_A_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,L", address);
}

/* ADD A,(HL) */
fn disassemble__ADD_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,(HL)", address);
}

/* ADD A,A */
fn disassemble__ADD_A_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,A", address);
}

/* ADC A,B */
fn disassemble__ADC_A_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,B", address);
}

/* ADC A,C */
fn disassemble__ADC_A_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,C", address);
}

/* ADC A,D */
fn disassemble__ADC_A_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,D", address);
}

/* ADC A,E */
fn disassemble__ADC_A_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,E", address);
}

/* ADC A,H */
fn disassemble__ADC_A_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,H", address);
}

/* ADC A,L */
fn disassemble__ADC_A_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,L", address);
}

/* ADC A,(HL) */
fn disassemble__ADC_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,(HL)", address);
}

/* ADC A,A */
fn disassemble__ADC_A_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,A", address);
}

/* SUB A,B */
fn disassemble__SUB_A_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,B", address);
}

/* SUB A,C */
fn disassemble__SUB_A_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,C", address);
}

/* SUB A,D */
fn disassemble__SUB_A_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,D", address);
}

/* SUB A,E */
fn disassemble__SUB_A_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,E", address);
}

/* SUB A,H */
fn disassemble__SUB_A_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,H", address);
}

/* SUB A,L */
fn disassemble__SUB_A_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,L", address);
}

/* SUB A,(HL) */
fn disassemble__SUB_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,(HL)", address);
}

/* SUB A,A */
fn disassemble__SUB_A_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,A", address);
}

/* SBC A,B */
fn disassemble__SBC_A_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,B", address);
}

/* SBC A,C */
fn disassemble__SBC_A_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,C", address);
}

/* SBC A,D */
fn disassemble__SBC_A_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,D", address);
}

/* SBC A,E */
fn disassemble__SBC_A_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,E", address);
}

/* SBC A,H */
fn disassemble__SBC_A_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,H", address);
}

/* SBC A,L */
fn disassemble__SBC_A_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,L", address);
}

/* SBC A,(HL) */
fn disassemble__SBC_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,(HL)", address);
}

/* SBC A,A */
fn disassemble__SBC_A_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,A", address);
}

/* AND A,B */
fn disassemble__AND_A_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,B", address);
}

/* AND A,C */
fn disassemble__AND_A_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,C", address);
}

/* AND A,D */
fn disassemble__AND_A_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,D", address);
}

/* AND A,E */
fn disassemble__AND_A_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,E", address);
}

/* AND A,H */
fn disassemble__AND_A_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,H", address);
}

/* AND A,L */
fn disassemble__AND_A_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,L", address);
}

/* AND A,(HL) */
fn disassemble__AND_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,(HL)", address);
}

/* AND A,A */
fn disassemble__AND_A_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,A", address);
}

/* XOR A,B */
fn disassemble__XOR_A_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,B", address);
}

/* XOR A,C */
fn disassemble__XOR_A_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,C", address);
}

/* XOR A,D */
fn disassemble__XOR_A_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,D", address);
}

/* XOR A,E */
fn disassemble__XOR_A_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,E", address);
}

/* XOR A,H */
fn disassemble__XOR_A_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,H", address);
}

/* XOR A,L */
fn disassemble__XOR_A_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,L", address);
}

/* XOR A,(HL) */
fn disassemble__XOR_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,(HL)", address);
}

/* XOR A,A */
fn disassemble__XOR_A_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,A", address);
}

/* OR A,B */
fn disassemble__OR_A_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,B", address);
}

/* OR A,C */
fn disassemble__OR_A_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,C", address);
}

/* OR A,D */
fn disassemble__OR_A_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,D", address);
}

/* OR A,E */
fn disassemble__OR_A_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,E", address);
}

/* OR A,H */
fn disassemble__OR_A_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,H", address);
}

/* OR A,L */
fn disassemble__OR_A_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,L", address);
}

/* OR A,(HL) */
fn disassemble__OR_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,(HL)", address);
}

/* OR A,A */
fn disassemble__OR_A_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,A", address);
}

/* CP B */
fn disassemble__CP_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP B", address);
}

/* CP C */
fn disassemble__CP_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP C", address);
}

/* CP D */
fn disassemble__CP_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP D", address);
}

/* CP E */
fn disassemble__CP_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP E", address);
}

/* CP H */
fn disassemble__CP_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP H", address);
}

/* CP L */
fn disassemble__CP_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP L", address);
}

/* CP (HL) */
fn disassemble__CP_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP (HL)", address);
}

/* CP A */
fn disassemble__CP_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP A", address);
}

/* RET NZ */
fn disassemble__RET_NZ(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RET NZ", address);
}

/* POP BC */
fn disassemble__POP_BC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) POP BC", address);
}

/* JP NZ,nnnn */
fn disassemble__JP_NZ_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) JP NZ,0x{:04x}", address, nnnn);
}

/* JP nnnn */
fn disassemble__JP_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) JP 0x{:04x}", address, nnnn);
}

/* CALL NZ,nnnn */
fn disassemble__CALL_NZ_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) CALL NZ,0x{:04x}", address, nnnn);
}

/* PUSH BC */
fn disassemble__PUSH_BC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) PUSH BC", address);
}

/* ADD A,nn */
fn disassemble__ADD_A_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) ADD A,0x{:02x}", address, nn);
}

/* RST 00 */
fn disassemble__RST_00(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RST 00", address);
}

/* RET Z */
fn disassemble__RET_Z(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RET Z", address);
}

/* RET */
fn disassemble__RET(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RET", address);
}

/* JP Z,nnnn */
fn disassemble__JP_Z_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) JP Z,0x{:04x}", address, nnnn);
}

/* shift CB */
fn disassemble__SHIFT_CB(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) shift CB", address);
}

/* CALL Z,nnnn */
fn disassemble__CALL_Z_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) CALL Z,0x{:04x}", address, nnnn);
}

/* CALL nnnn */
fn disassemble__CALL_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) CALL 0x{:04x}", address, nnnn);
}

/* ADC A,nn */
fn disassemble__ADC_A_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) ADC A,0x{:02x}", address, nn);
}

/* RST 8 */
fn disassemble__RST_8(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RST 8", address);
}

/* RET NC */
fn disassemble__RET_NC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RET NC", address);
}

/* POP DE */
fn disassemble__POP_DE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) POP DE", address);
}

/* JP NC,nnnn */
fn disassemble__JP_NC_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) JP NC,0x{:04x}", address, nnnn);
}

/* OUT (nn),A */
fn disassemble__OUT_iNN_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) OUT (0x{:02x}),A", address, nn);
}

/* CALL NC,nnnn */
fn disassemble__CALL_NC_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) CALL NC,0x{:04x}", address, nnnn);
}

/* PUSH DE */
fn disassemble__PUSH_DE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) PUSH DE", address);
}

/* SUB nn */
fn disassemble__SUB_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) SUB 0x{:02x}", address, nn);
}

/* RST 10 */
fn disassemble__RST_10(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RST 10", address);
}

/* RET C */
fn disassemble__RET_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RET C", address);
}

/* EXX */
fn disassemble__EXX(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) EXX", address);
}

/* JP C,nnnn */
fn disassemble__JP_C_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) JP C,0x{:04x}", address, nnnn);
}

/* IN A,(nn) */
fn disassemble__IN_A_iNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) IN A,(0x{:02x})", address, nn);
}

/* CALL C,nnnn */
fn disassemble__CALL_C_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) CALL C,0x{:04x}", address, nnnn);
}

/* shift DD */
fn disassemble__SHIFT_DD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) shift DD", address);
}

/* SBC A,nn */
fn disassemble__SBC_A_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) SBC A,0x{:02x}", address, nn);
}

/* RST 18 */
fn disassemble__RST_18(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RST 18", address);
}

/* RET PO */
fn disassemble__RET_PO(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RET PO", address);
}

/* POP HL */
fn disassemble__POP_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) POP HL", address);
}

/* JP PO,nnnn */
fn disassemble__JP_PO_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) JP PO,0x{:04x}", address, nnnn);
}

/* EX (SP),HL */
fn disassemble__EX_iSP_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) EX (SP),HL", address);
}

/* CALL PO,nnnn */
fn disassemble__CALL_PO_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) CALL PO,0x{:04x}", address, nnnn);
}

/* PUSH HL */
fn disassemble__PUSH_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) PUSH HL", address);
}

/* AND nn */
fn disassemble__AND_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) AND 0x{:02x}", address, nn);
}

/* RST 20 */
fn disassemble__RST_20(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RST 20", address);
}

/* RET PE */
fn disassemble__RET_PE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RET PE", address);
}

/* JP HL */
fn disassemble__JP_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) JP HL", address);
}

/* JP PE,nnnn */
fn disassemble__JP_PE_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) JP PE,0x{:04x}", address, nnnn);
}

/* EX DE,HL */
fn disassemble__EX_DE_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) EX DE,HL", address);
}

/* CALL PE,nnnn */
fn disassemble__CALL_PE_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) CALL PE,0x{:04x}", address, nnnn);
}

/* shift ED */
fn disassemble__SHIFT_ED(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) shift ED", address);
}

/* XOR A,nn */
fn disassemble__XOR_A_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) XOR A,0x{:02x}", address, nn);
}

/* RST 28 */
fn disassemble__RST_28(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RST 28", address);
}

/* RET P */
fn disassemble__RET_P(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RET P", address);
}

/* POP AF */
fn disassemble__POP_AF(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) POP AF", address);
}

/* JP P,nnnn */
fn disassemble__JP_P_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) JP P,0x{:04x}", address, nnnn);
}

/* DI */
fn disassemble__DI(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DI", address);
}

/* CALL P,nnnn */
fn disassemble__CALL_P_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) CALL P,0x{:04x}", address, nnnn);
}

/* PUSH AF */
fn disassemble__PUSH_AF(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) PUSH AF", address);
}

/* OR nn */
fn disassemble__OR_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) OR 0x{:02x}", address, nn);
}

/* RST 30 */
fn disassemble__RST_30(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RST 30", address);
}

/* RET M */
fn disassemble__RET_M(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RET M", address);
}

/* LD SP,HL */
fn disassemble__LD_SP_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD SP,HL", address);
}

/* JP M,nnnn */
fn disassemble__JP_M_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) JP M,0x{:04x}", address, nnnn);
}

/* EI */
fn disassemble__EI(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) EI", address);
}

/* CALL M,nnnn */
fn disassemble__CALL_M_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) CALL M,0x{:04x}", address, nnnn);
}

/* shift FD */
fn disassemble__SHIFT_FD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) shift FD", address);
}

/* CP nn */
fn disassemble__CP_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) CP 0x{:02x}", address, nn);
}

/* RST 38 */
fn disassemble__RST_38(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RST 38", address);
}

/* RLC B */
fn disassembleCB__RLC_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLC B", address);
}

/* RLC C */
fn disassembleCB__RLC_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLC C", address);
}

/* RLC D */
fn disassembleCB__RLC_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLC D", address);
}

/* RLC E */
fn disassembleCB__RLC_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLC E", address);
}

/* RLC H */
fn disassembleCB__RLC_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLC H", address);
}

/* RLC L */
fn disassembleCB__RLC_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLC L", address);
}

/* RLC (HL) */
fn disassembleCB__RLC_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLC (HL)", address);
}

/* RLC A */
fn disassembleCB__RLC_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLC A", address);
}

/* RRC B */
fn disassembleCB__RRC_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRC B", address);
}

/* RRC C */
fn disassembleCB__RRC_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRC C", address);
}

/* RRC D */
fn disassembleCB__RRC_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRC D", address);
}

/* RRC E */
fn disassembleCB__RRC_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRC E", address);
}

/* RRC H */
fn disassembleCB__RRC_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRC H", address);
}

/* RRC L */
fn disassembleCB__RRC_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRC L", address);
}

/* RRC (HL) */
fn disassembleCB__RRC_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRC (HL)", address);
}

/* RRC A */
fn disassembleCB__RRC_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRC A", address);
}

/* RL B */
fn disassembleCB__RL_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RL B", address);
}

/* RL C */
fn disassembleCB__RL_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RL C", address);
}

/* RL D */
fn disassembleCB__RL_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RL D", address);
}

/* RL E */
fn disassembleCB__RL_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RL E", address);
}

/* RL H */
fn disassembleCB__RL_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RL H", address);
}

/* RL L */
fn disassembleCB__RL_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RL L", address);
}

/* RL (HL) */
fn disassembleCB__RL_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RL (HL)", address);
}

/* RL A */
fn disassembleCB__RL_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RL A", address);
}

/* RR B */
fn disassembleCB__RR_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RR B", address);
}

/* RR C */
fn disassembleCB__RR_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RR C", address);
}

/* RR D */
fn disassembleCB__RR_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RR D", address);
}

/* RR E */
fn disassembleCB__RR_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RR E", address);
}

/* RR H */
fn disassembleCB__RR_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RR H", address);
}

/* RR L */
fn disassembleCB__RR_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RR L", address);
}

/* RR (HL) */
fn disassembleCB__RR_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RR (HL)", address);
}

/* RR A */
fn disassembleCB__RR_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RR A", address);
}

/* SLA B */
fn disassembleCB__SLA_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLA B", address);
}

/* SLA C */
fn disassembleCB__SLA_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLA C", address);
}

/* SLA D */
fn disassembleCB__SLA_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLA D", address);
}

/* SLA E */
fn disassembleCB__SLA_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLA E", address);
}

/* SLA H */
fn disassembleCB__SLA_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLA H", address);
}

/* SLA L */
fn disassembleCB__SLA_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLA L", address);
}

/* SLA (HL) */
fn disassembleCB__SLA_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLA (HL)", address);
}

/* SLA A */
fn disassembleCB__SLA_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLA A", address);
}

/* SRA B */
fn disassembleCB__SRA_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRA B", address);
}

/* SRA C */
fn disassembleCB__SRA_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRA C", address);
}

/* SRA D */
fn disassembleCB__SRA_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRA D", address);
}

/* SRA E */
fn disassembleCB__SRA_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRA E", address);
}

/* SRA H */
fn disassembleCB__SRA_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRA H", address);
}

/* SRA L */
fn disassembleCB__SRA_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRA L", address);
}

/* SRA (HL) */
fn disassembleCB__SRA_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRA (HL)", address);
}

/* SRA A */
fn disassembleCB__SRA_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRA A", address);
}

/* SLL B */
fn disassembleCB__SLL_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLL B", address);
}

/* SLL C */
fn disassembleCB__SLL_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLL C", address);
}

/* SLL D */
fn disassembleCB__SLL_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLL D", address);
}

/* SLL E */
fn disassembleCB__SLL_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLL E", address);
}

/* SLL H */
fn disassembleCB__SLL_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLL H", address);
}

/* SLL L */
fn disassembleCB__SLL_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLL L", address);
}

/* SLL (HL) */
fn disassembleCB__SLL_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLL (HL)", address);
}

/* SLL A */
fn disassembleCB__SLL_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLL A", address);
}

/* SRL B */
fn disassembleCB__SRL_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRL B", address);
}

/* SRL C */
fn disassembleCB__SRL_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRL C", address);
}

/* SRL D */
fn disassembleCB__SRL_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRL D", address);
}

/* SRL E */
fn disassembleCB__SRL_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRL E", address);
}

/* SRL H */
fn disassembleCB__SRL_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRL H", address);
}

/* SRL L */
fn disassembleCB__SRL_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRL L", address);
}

/* SRL (HL) */
fn disassembleCB__SRL_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRL (HL)", address);
}

/* SRL A */
fn disassembleCB__SRL_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRL A", address);
}

/* BIT 0,B */
fn disassembleCB__BIT_0_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 0,B", address);
}

/* BIT 0,C */
fn disassembleCB__BIT_0_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 0,C", address);
}

/* BIT 0,D */
fn disassembleCB__BIT_0_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 0,D", address);
}

/* BIT 0,E */
fn disassembleCB__BIT_0_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 0,E", address);
}

/* BIT 0,H */
fn disassembleCB__BIT_0_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 0,H", address);
}

/* BIT 0,L */
fn disassembleCB__BIT_0_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 0,L", address);
}

/* BIT 0,(HL) */
fn disassembleCB__BIT_0_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 0,(HL)", address);
}

/* BIT 0,A */
fn disassembleCB__BIT_0_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 0,A", address);
}

/* BIT 1,B */
fn disassembleCB__BIT_1_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 1,B", address);
}

/* BIT 1,C */
fn disassembleCB__BIT_1_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 1,C", address);
}

/* BIT 1,D */
fn disassembleCB__BIT_1_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 1,D", address);
}

/* BIT 1,E */
fn disassembleCB__BIT_1_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 1,E", address);
}

/* BIT 1,H */
fn disassembleCB__BIT_1_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 1,H", address);
}

/* BIT 1,L */
fn disassembleCB__BIT_1_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 1,L", address);
}

/* BIT 1,(HL) */
fn disassembleCB__BIT_1_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 1,(HL)", address);
}

/* BIT 1,A */
fn disassembleCB__BIT_1_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 1,A", address);
}

/* BIT 2,B */
fn disassembleCB__BIT_2_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 2,B", address);
}

/* BIT 2,C */
fn disassembleCB__BIT_2_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 2,C", address);
}

/* BIT 2,D */
fn disassembleCB__BIT_2_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 2,D", address);
}

/* BIT 2,E */
fn disassembleCB__BIT_2_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 2,E", address);
}

/* BIT 2,H */
fn disassembleCB__BIT_2_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 2,H", address);
}

/* BIT 2,L */
fn disassembleCB__BIT_2_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 2,L", address);
}

/* BIT 2,(HL) */
fn disassembleCB__BIT_2_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 2,(HL)", address);
}

/* BIT 2,A */
fn disassembleCB__BIT_2_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 2,A", address);
}

/* BIT 3,B */
fn disassembleCB__BIT_3_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 3,B", address);
}

/* BIT 3,C */
fn disassembleCB__BIT_3_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 3,C", address);
}

/* BIT 3,D */
fn disassembleCB__BIT_3_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 3,D", address);
}

/* BIT 3,E */
fn disassembleCB__BIT_3_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 3,E", address);
}

/* BIT 3,H */
fn disassembleCB__BIT_3_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 3,H", address);
}

/* BIT 3,L */
fn disassembleCB__BIT_3_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 3,L", address);
}

/* BIT 3,(HL) */
fn disassembleCB__BIT_3_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 3,(HL)", address);
}

/* BIT 3,A */
fn disassembleCB__BIT_3_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 3,A", address);
}

/* BIT 4,B */
fn disassembleCB__BIT_4_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 4,B", address);
}

/* BIT 4,C */
fn disassembleCB__BIT_4_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 4,C", address);
}

/* BIT 4,D */
fn disassembleCB__BIT_4_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 4,D", address);
}

/* BIT 4,E */
fn disassembleCB__BIT_4_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 4,E", address);
}

/* BIT 4,H */
fn disassembleCB__BIT_4_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 4,H", address);
}

/* BIT 4,L */
fn disassembleCB__BIT_4_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 4,L", address);
}

/* BIT 4,(HL) */
fn disassembleCB__BIT_4_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 4,(HL)", address);
}

/* BIT 4,A */
fn disassembleCB__BIT_4_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 4,A", address);
}

/* BIT 5,B */
fn disassembleCB__BIT_5_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 5,B", address);
}

/* BIT 5,C */
fn disassembleCB__BIT_5_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 5,C", address);
}

/* BIT 5,D */
fn disassembleCB__BIT_5_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 5,D", address);
}

/* BIT 5,E */
fn disassembleCB__BIT_5_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 5,E", address);
}

/* BIT 5,H */
fn disassembleCB__BIT_5_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 5,H", address);
}

/* BIT 5,L */
fn disassembleCB__BIT_5_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 5,L", address);
}

/* BIT 5,(HL) */
fn disassembleCB__BIT_5_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 5,(HL)", address);
}

/* BIT 5,A */
fn disassembleCB__BIT_5_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 5,A", address);
}

/* BIT 6,B */
fn disassembleCB__BIT_6_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 6,B", address);
}

/* BIT 6,C */
fn disassembleCB__BIT_6_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 6,C", address);
}

/* BIT 6,D */
fn disassembleCB__BIT_6_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 6,D", address);
}

/* BIT 6,E */
fn disassembleCB__BIT_6_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 6,E", address);
}

/* BIT 6,H */
fn disassembleCB__BIT_6_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 6,H", address);
}

/* BIT 6,L */
fn disassembleCB__BIT_6_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 6,L", address);
}

/* BIT 6,(HL) */
fn disassembleCB__BIT_6_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 6,(HL)", address);
}

/* BIT 6,A */
fn disassembleCB__BIT_6_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 6,A", address);
}

/* BIT 7,B */
fn disassembleCB__BIT_7_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 7,B", address);
}

/* BIT 7,C */
fn disassembleCB__BIT_7_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 7,C", address);
}

/* BIT 7,D */
fn disassembleCB__BIT_7_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 7,D", address);
}

/* BIT 7,E */
fn disassembleCB__BIT_7_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 7,E", address);
}

/* BIT 7,H */
fn disassembleCB__BIT_7_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 7,H", address);
}

/* BIT 7,L */
fn disassembleCB__BIT_7_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 7,L", address);
}

/* BIT 7,(HL) */
fn disassembleCB__BIT_7_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 7,(HL)", address);
}

/* BIT 7,A */
fn disassembleCB__BIT_7_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 7,A", address);
}

/* RES 0,B */
fn disassembleCB__RES_0_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 0,B", address);
}

/* RES 0,C */
fn disassembleCB__RES_0_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 0,C", address);
}

/* RES 0,D */
fn disassembleCB__RES_0_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 0,D", address);
}

/* RES 0,E */
fn disassembleCB__RES_0_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 0,E", address);
}

/* RES 0,H */
fn disassembleCB__RES_0_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 0,H", address);
}

/* RES 0,L */
fn disassembleCB__RES_0_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 0,L", address);
}

/* RES 0,(HL) */
fn disassembleCB__RES_0_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 0,(HL)", address);
}

/* RES 0,A */
fn disassembleCB__RES_0_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 0,A", address);
}

/* RES 1,B */
fn disassembleCB__RES_1_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 1,B", address);
}

/* RES 1,C */
fn disassembleCB__RES_1_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 1,C", address);
}

/* RES 1,D */
fn disassembleCB__RES_1_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 1,D", address);
}

/* RES 1,E */
fn disassembleCB__RES_1_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 1,E", address);
}

/* RES 1,H */
fn disassembleCB__RES_1_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 1,H", address);
}

/* RES 1,L */
fn disassembleCB__RES_1_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 1,L", address);
}

/* RES 1,(HL) */
fn disassembleCB__RES_1_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 1,(HL)", address);
}

/* RES 1,A */
fn disassembleCB__RES_1_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 1,A", address);
}

/* RES 2,B */
fn disassembleCB__RES_2_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 2,B", address);
}

/* RES 2,C */
fn disassembleCB__RES_2_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 2,C", address);
}

/* RES 2,D */
fn disassembleCB__RES_2_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 2,D", address);
}

/* RES 2,E */
fn disassembleCB__RES_2_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 2,E", address);
}

/* RES 2,H */
fn disassembleCB__RES_2_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 2,H", address);
}

/* RES 2,L */
fn disassembleCB__RES_2_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 2,L", address);
}

/* RES 2,(HL) */
fn disassembleCB__RES_2_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 2,(HL)", address);
}

/* RES 2,A */
fn disassembleCB__RES_2_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 2,A", address);
}

/* RES 3,B */
fn disassembleCB__RES_3_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 3,B", address);
}

/* RES 3,C */
fn disassembleCB__RES_3_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 3,C", address);
}

/* RES 3,D */
fn disassembleCB__RES_3_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 3,D", address);
}

/* RES 3,E */
fn disassembleCB__RES_3_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 3,E", address);
}

/* RES 3,H */
fn disassembleCB__RES_3_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 3,H", address);
}

/* RES 3,L */
fn disassembleCB__RES_3_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 3,L", address);
}

/* RES 3,(HL) */
fn disassembleCB__RES_3_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 3,(HL)", address);
}

/* RES 3,A */
fn disassembleCB__RES_3_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 3,A", address);
}

/* RES 4,B */
fn disassembleCB__RES_4_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 4,B", address);
}

/* RES 4,C */
fn disassembleCB__RES_4_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 4,C", address);
}

/* RES 4,D */
fn disassembleCB__RES_4_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 4,D", address);
}

/* RES 4,E */
fn disassembleCB__RES_4_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 4,E", address);
}

/* RES 4,H */
fn disassembleCB__RES_4_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 4,H", address);
}

/* RES 4,L */
fn disassembleCB__RES_4_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 4,L", address);
}

/* RES 4,(HL) */
fn disassembleCB__RES_4_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 4,(HL)", address);
}

/* RES 4,A */
fn disassembleCB__RES_4_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 4,A", address);
}

/* RES 5,B */
fn disassembleCB__RES_5_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 5,B", address);
}

/* RES 5,C */
fn disassembleCB__RES_5_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 5,C", address);
}

/* RES 5,D */
fn disassembleCB__RES_5_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 5,D", address);
}

/* RES 5,E */
fn disassembleCB__RES_5_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 5,E", address);
}

/* RES 5,H */
fn disassembleCB__RES_5_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 5,H", address);
}

/* RES 5,L */
fn disassembleCB__RES_5_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 5,L", address);
}

/* RES 5,(HL) */
fn disassembleCB__RES_5_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 5,(HL)", address);
}

/* RES 5,A */
fn disassembleCB__RES_5_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 5,A", address);
}

/* RES 6,B */
fn disassembleCB__RES_6_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 6,B", address);
}

/* RES 6,C */
fn disassembleCB__RES_6_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 6,C", address);
}

/* RES 6,D */
fn disassembleCB__RES_6_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 6,D", address);
}

/* RES 6,E */
fn disassembleCB__RES_6_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 6,E", address);
}

/* RES 6,H */
fn disassembleCB__RES_6_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 6,H", address);
}

/* RES 6,L */
fn disassembleCB__RES_6_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 6,L", address);
}

/* RES 6,(HL) */
fn disassembleCB__RES_6_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 6,(HL)", address);
}

/* RES 6,A */
fn disassembleCB__RES_6_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 6,A", address);
}

/* RES 7,B */
fn disassembleCB__RES_7_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 7,B", address);
}

/* RES 7,C */
fn disassembleCB__RES_7_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 7,C", address);
}

/* RES 7,D */
fn disassembleCB__RES_7_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 7,D", address);
}

/* RES 7,E */
fn disassembleCB__RES_7_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 7,E", address);
}

/* RES 7,H */
fn disassembleCB__RES_7_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 7,H", address);
}

/* RES 7,L */
fn disassembleCB__RES_7_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 7,L", address);
}

/* RES 7,(HL) */
fn disassembleCB__RES_7_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 7,(HL)", address);
}

/* RES 7,A */
fn disassembleCB__RES_7_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 7,A", address);
}

/* SET 0,B */
fn disassembleCB__SET_0_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 0,B", address);
}

/* SET 0,C */
fn disassembleCB__SET_0_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 0,C", address);
}

/* SET 0,D */
fn disassembleCB__SET_0_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 0,D", address);
}

/* SET 0,E */
fn disassembleCB__SET_0_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 0,E", address);
}

/* SET 0,H */
fn disassembleCB__SET_0_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 0,H", address);
}

/* SET 0,L */
fn disassembleCB__SET_0_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 0,L", address);
}

/* SET 0,(HL) */
fn disassembleCB__SET_0_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 0,(HL)", address);
}

/* SET 0,A */
fn disassembleCB__SET_0_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 0,A", address);
}

/* SET 1,B */
fn disassembleCB__SET_1_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 1,B", address);
}

/* SET 1,C */
fn disassembleCB__SET_1_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 1,C", address);
}

/* SET 1,D */
fn disassembleCB__SET_1_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 1,D", address);
}

/* SET 1,E */
fn disassembleCB__SET_1_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 1,E", address);
}

/* SET 1,H */
fn disassembleCB__SET_1_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 1,H", address);
}

/* SET 1,L */
fn disassembleCB__SET_1_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 1,L", address);
}

/* SET 1,(HL) */
fn disassembleCB__SET_1_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 1,(HL)", address);
}

/* SET 1,A */
fn disassembleCB__SET_1_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 1,A", address);
}

/* SET 2,B */
fn disassembleCB__SET_2_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 2,B", address);
}

/* SET 2,C */
fn disassembleCB__SET_2_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 2,C", address);
}

/* SET 2,D */
fn disassembleCB__SET_2_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 2,D", address);
}

/* SET 2,E */
fn disassembleCB__SET_2_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 2,E", address);
}

/* SET 2,H */
fn disassembleCB__SET_2_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 2,H", address);
}

/* SET 2,L */
fn disassembleCB__SET_2_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 2,L", address);
}

/* SET 2,(HL) */
fn disassembleCB__SET_2_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 2,(HL)", address);
}

/* SET 2,A */
fn disassembleCB__SET_2_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 2,A", address);
}

/* SET 3,B */
fn disassembleCB__SET_3_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 3,B", address);
}

/* SET 3,C */
fn disassembleCB__SET_3_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 3,C", address);
}

/* SET 3,D */
fn disassembleCB__SET_3_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 3,D", address);
}

/* SET 3,E */
fn disassembleCB__SET_3_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 3,E", address);
}

/* SET 3,H */
fn disassembleCB__SET_3_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 3,H", address);
}

/* SET 3,L */
fn disassembleCB__SET_3_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 3,L", address);
}

/* SET 3,(HL) */
fn disassembleCB__SET_3_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 3,(HL)", address);
}

/* SET 3,A */
fn disassembleCB__SET_3_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 3,A", address);
}

/* SET 4,B */
fn disassembleCB__SET_4_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 4,B", address);
}

/* SET 4,C */
fn disassembleCB__SET_4_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 4,C", address);
}

/* SET 4,D */
fn disassembleCB__SET_4_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 4,D", address);
}

/* SET 4,E */
fn disassembleCB__SET_4_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 4,E", address);
}

/* SET 4,H */
fn disassembleCB__SET_4_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 4,H", address);
}

/* SET 4,L */
fn disassembleCB__SET_4_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 4,L", address);
}

/* SET 4,(HL) */
fn disassembleCB__SET_4_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 4,(HL)", address);
}

/* SET 4,A */
fn disassembleCB__SET_4_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 4,A", address);
}

/* SET 5,B */
fn disassembleCB__SET_5_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 5,B", address);
}

/* SET 5,C */
fn disassembleCB__SET_5_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 5,C", address);
}

/* SET 5,D */
fn disassembleCB__SET_5_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 5,D", address);
}

/* SET 5,E */
fn disassembleCB__SET_5_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 5,E", address);
}

/* SET 5,H */
fn disassembleCB__SET_5_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 5,H", address);
}

/* SET 5,L */
fn disassembleCB__SET_5_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 5,L", address);
}

/* SET 5,(HL) */
fn disassembleCB__SET_5_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 5,(HL)", address);
}

/* SET 5,A */
fn disassembleCB__SET_5_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 5,A", address);
}

/* SET 6,B */
fn disassembleCB__SET_6_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 6,B", address);
}

/* SET 6,C */
fn disassembleCB__SET_6_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 6,C", address);
}

/* SET 6,D */
fn disassembleCB__SET_6_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 6,D", address);
}

/* SET 6,E */
fn disassembleCB__SET_6_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 6,E", address);
}

/* SET 6,H */
fn disassembleCB__SET_6_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 6,H", address);
}

/* SET 6,L */
fn disassembleCB__SET_6_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 6,L", address);
}

/* SET 6,(HL) */
fn disassembleCB__SET_6_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 6,(HL)", address);
}

/* SET 6,A */
fn disassembleCB__SET_6_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 6,A", address);
}

/* SET 7,B */
fn disassembleCB__SET_7_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 7,B", address);
}

/* SET 7,C */
fn disassembleCB__SET_7_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 7,C", address);
}

/* SET 7,D */
fn disassembleCB__SET_7_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 7,D", address);
}

/* SET 7,E */
fn disassembleCB__SET_7_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 7,E", address);
}

/* SET 7,H */
fn disassembleCB__SET_7_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 7,H", address);
}

/* SET 7,L */
fn disassembleCB__SET_7_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 7,L", address);
}

/* SET 7,(HL) */
fn disassembleCB__SET_7_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 7,(HL)", address);
}

/* SET 7,A */
fn disassembleCB__SET_7_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 7,A", address);
}

/* IN B,(C) */
fn disassembleED__IN_B_iC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IN B,(C)", address);
}

/* OUT (C),B */
fn disassembleED__OUT_iC_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OUT (C),B", address);
}

/* SBC HL,BC */
fn disassembleED__SBC_HL_BC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC HL,BC", address);
}

/* LD (nnnn),BC */
fn disassembleED__LD_iNNNN_BC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD (0x{:04x}),BC", address, nnnn);
}

/* NEG */
fn disassembleED__NEG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) NEG", address);
}

/* RETN */
fn disassembleED__RETN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RETN", address);
}

/* IM 0 */
fn disassembleED__IM_0(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IM 0", address);
}

/* LD I,A */
fn disassembleED__LD_I_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD I,A", address);
}

/* IN C,(C) */
fn disassembleED__IN_C_iC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IN C,(C)", address);
}

/* OUT (C),C */
fn disassembleED__OUT_iC_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OUT (C),C", address);
}

/* ADC HL,BC */
fn disassembleED__ADC_HL_BC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC HL,BC", address);
}

/* LD BC,(nnnn) */
fn disassembleED__LD_BC_iNNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD BC,(0x{:04x})", address, nnnn);
}

/* LD R,A */
fn disassembleED__LD_R_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD R,A", address);
}

/* IN D,(C) */
fn disassembleED__IN_D_iC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IN D,(C)", address);
}

/* OUT (C),D */
fn disassembleED__OUT_iC_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OUT (C),D", address);
}

/* SBC HL,DE */
fn disassembleED__SBC_HL_DE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC HL,DE", address);
}

/* LD (nnnn),DE */
fn disassembleED__LD_iNNNN_DE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD (0x{:04x}),DE", address, nnnn);
}

/* IM 1 */
fn disassembleED__IM_1(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IM 1", address);
}

/* LD A,I */
fn disassembleED__LD_A_I(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,I", address);
}

/* IN E,(C) */
fn disassembleED__IN_E_iC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IN E,(C)", address);
}

/* OUT (C),E */
fn disassembleED__OUT_iC_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OUT (C),E", address);
}

/* ADC HL,DE */
fn disassembleED__ADC_HL_DE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC HL,DE", address);
}

/* LD DE,(nnnn) */
fn disassembleED__LD_DE_iNNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD DE,(0x{:04x})", address, nnnn);
}

/* IM 2 */
fn disassembleED__IM_2(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IM 2", address);
}

/* LD A,R */
fn disassembleED__LD_A_R(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,R", address);
}

/* IN H,(C) */
fn disassembleED__IN_H_iC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IN H,(C)", address);
}

/* OUT (C),H */
fn disassembleED__OUT_iC_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OUT (C),H", address);
}

/* SBC HL,HL */
fn disassembleED__SBC_HL_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC HL,HL", address);
}

/* LD (nnnn),HL */
fn disassembleED__LD_iNNNN_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD (0x{:04x}),HL", address, nnnn);
}

/* RRD */
fn disassembleED__RRD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRD", address);
}

/* IN L,(C) */
fn disassembleED__IN_L_iC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IN L,(C)", address);
}

/* OUT (C),L */
fn disassembleED__OUT_iC_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OUT (C),L", address);
}

/* ADC HL,HL */
fn disassembleED__ADC_HL_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC HL,HL", address);
}

/* LD HL,(nnnn) */
fn disassembleED__LD_HL_iNNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD HL,(0x{:04x})", address, nnnn);
}

/* RLD */
fn disassembleED__RLD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLD", address);
}

/* IN F,(C) */
fn disassembleED__IN_F_iC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IN F,(C)", address);
}

/* OUT (C),0 */
fn disassembleED__OUT_iC_0(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OUT (C),0", address);
}

/* SBC HL,SP */
fn disassembleED__SBC_HL_SP(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC HL,SP", address);
}

/* LD (nnnn),SP */
fn disassembleED__LD_iNNNN_SP(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD (0x{:04x}),SP", address, nnnn);
}

/* IN A,(C) */
fn disassembleED__IN_A_iC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IN A,(C)", address);
}

/* OUT (C),A */
fn disassembleED__OUT_iC_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OUT (C),A", address);
}

/* ADC HL,SP */
fn disassembleED__ADC_HL_SP(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC HL,SP", address);
}

/* LD SP,(nnnn) */
fn disassembleED__LD_SP_iNNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD SP,(0x{:04x})", address, nnnn);
}

/* LDI */
fn disassembleED__LDI(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LDI", address);
}

/* CPI */
fn disassembleED__CPI(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CPI", address);
}

/* INI */
fn disassembleED__INI(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INI", address);
}

/* OUTI */
fn disassembleED__OUTI(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OUTI", address);
}

/* LDD */
fn disassembleED__LDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LDD", address);
}

/* CPD */
fn disassembleED__CPD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CPD", address);
}

/* IND */
fn disassembleED__IND(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) IND", address);
}

/* OUTD */
fn disassembleED__OUTD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OUTD", address);
}

/* LDIR */
fn disassembleED__LDIR(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LDIR", address);
}

/* CPIR */
fn disassembleED__CPIR(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CPIR", address);
}

/* INIR */
fn disassembleED__INIR(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INIR", address);
}

/* OTIR */
fn disassembleED__OTIR(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OTIR", address);
}

/* LDDR */
fn disassembleED__LDDR(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LDDR", address);
}

/* CPDR */
fn disassembleED__CPDR(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CPDR", address);
}

/* INDR */
fn disassembleED__INDR(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INDR", address);
}

/* OTDR */
fn disassembleED__OTDR(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OTDR", address);
}

/* slttrap */
fn disassembleED__SLTTRAP(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) slttrap", address);
}

/* ADD REGISTER,BC */
fn disassembleDD__ADD_REG_BC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD ix,BC", address);
}

/* ADD REGISTER,DE */
fn disassembleDD__ADD_REG_DE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD ix,DE", address);
}

/* LD REGISTER,nnnn */
fn disassembleDD__LD_REG_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD ix,0x{:04x}", address, nnnn);
}

/* LD (nnnn),REGISTER */
fn disassembleDD__LD_iNNNN_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD (0x{:04x}),ix", address, nnnn);
}

/* INC REGISTER */
fn disassembleDD__INC_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC ix", address);
}

/* INC REGISTERH */
fn disassembleDD__INC_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC IXH", address);
}

/* DEC REGISTERH */
fn disassembleDD__DEC_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC IXH", address);
}

/* LD REGISTERH,nn */
fn disassembleDD__LD_REGH_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) LD IXH,0x{:04x}", address, nn);
}

/* ADD REGISTER,REGISTER */
fn disassembleDD__ADD_REG_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD REGISTER,REGISTER", address);
}

/* LD REGISTER,(nnnn) */
fn disassembleDD__LD_REG_iNNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD ix,(0x{:04x})", address, nnnn);
}

/* DEC REGISTER */
fn disassembleDD__DEC_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC REGISTER", address);
}

/* INC REGISTERL */
fn disassembleDD__INC_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC REGISTERL", address);
}

/* DEC REGISTERL */
fn disassembleDD__DEC_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC REGISTERL", address);
}

/* LD REGISTERL,nn */
fn disassembleDD__LD_REGL_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) LD IXL,0x{:02x}", address, nn);
}

/* INC (REGISTER+dd) */
fn disassembleDD__INC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC (REGISTER+dd)", address);
}

/* DEC (REGISTER+dd) */
fn disassembleDD__DEC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC (REGISTER+dd)", address);
}

/* LD (REGISTER+dd),nn */
fn disassembleDD__LD_iREGpDD_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let ix_dd = memory.read_byte(address + 1);
    let nn = memory.read_byte(address + 2);
    println!("({:04x}) LD (ix+0x{:02x}),0x{:02x}", address, ix_dd, nn);
}

/* ADD REGISTER,SP */
fn disassembleDD__ADD_REG_SP(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD REGISTER,SP", address);
}

/* LD B,REGISTERH */
fn disassembleDD__LD_B_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,REGISTERH", address);
}

/* LD B,REGISTERL */
fn disassembleDD__LD_B_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,REGISTERL", address);
}

/* LD B,(REGISTER+dd) */
fn disassembleDD__LD_B_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,(REGISTER+dd)", address);
}

/* LD C,REGISTERH */
fn disassembleDD__LD_C_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,REGISTERH", address);
}

/* LD C,REGISTERL */
fn disassembleDD__LD_C_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,REGISTERL", address);
}

/* LD C,(REGISTER+dd) */
fn disassembleDD__LD_C_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,(REGISTER+dd)", address);
}

/* LD D,REGISTERH */
fn disassembleDD__LD_D_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,REGISTERH", address);
}

/* LD D,REGISTERL */
fn disassembleDD__LD_D_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,REGISTERL", address);
}

/* LD D,(REGISTER+dd) */
fn disassembleDD__LD_D_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,(REGISTER+dd)", address);
}

/* LD E,REGISTERH */
fn disassembleDD__LD_E_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,REGISTERH", address);
}

/* LD E,REGISTERL */
fn disassembleDD__LD_E_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,REGISTERL", address);
}

/* LD E,(REGISTER+dd) */
fn disassembleDD__LD_E_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,(REGISTER+dd)", address);
}

/* LD REGISTERH,B */
fn disassembleDD__LD_REGH_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,B", address);
}

/* LD REGISTERH,C */
fn disassembleDD__LD_REGH_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,C", address);
}

/* LD REGISTERH,D */
fn disassembleDD__LD_REGH_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,D", address);
}

/* LD REGISTERH,E */
fn disassembleDD__LD_REGH_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,E", address);
}

/* LD REGISTERH,REGISTERH */
fn disassembleDD__LD_REGH_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,REGISTERH", address);
}

/* LD REGISTERH,REGISTERL */
fn disassembleDD__LD_REGH_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,REGISTERL", address);
}

/* LD H,(REGISTER+dd) */
fn disassembleDD__LD_H_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,(REGISTER+dd)", address);
}

/* LD REGISTERH,A */
fn disassembleDD__LD_REGH_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,A", address);
}

/* LD REGISTERL,B */
fn disassembleDD__LD_REGL_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,B", address);
}

/* LD REGISTERL,C */
fn disassembleDD__LD_REGL_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,C", address);
}

/* LD REGISTERL,D */
fn disassembleDD__LD_REGL_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,D", address);
}

/* LD REGISTERL,E */
fn disassembleDD__LD_REGL_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,E", address);
}

/* LD REGISTERL,REGISTERH */
fn disassembleDD__LD_REGL_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,REGISTERH", address);
}

/* LD REGISTERL,REGISTERL */
fn disassembleDD__LD_REGL_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,REGISTERL", address);
}

/* LD L,(REGISTER+dd) */
fn disassembleDD__LD_L_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,(REGISTER+dd)", address);
}

/* LD REGISTERL,A */
fn disassembleDD__LD_REGL_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,A", address);
}

/* LD (REGISTER+dd),B */
fn disassembleDD__LD_iREGpDD_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),B", address);
}

/* LD (REGISTER+dd),C */
fn disassembleDD__LD_iREGpDD_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),C", address);
}

/* LD (REGISTER+dd),D */
fn disassembleDD__LD_iREGpDD_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),D", address);
}

/* LD (REGISTER+dd),E */
fn disassembleDD__LD_iREGpDD_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),E", address);
}

/* LD (REGISTER+dd),H */
fn disassembleDD__LD_iREGpDD_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),H", address);
}

/* LD (REGISTER+dd),L */
fn disassembleDD__LD_iREGpDD_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),L", address);
}

/* LD (REGISTER+dd),A */
fn disassembleDD__LD_iREGpDD_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),A", address);
}

/* LD A,REGISTERH */
fn disassembleDD__LD_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,REGISTERH", address);
}

/* LD A,REGISTERL */
fn disassembleDD__LD_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,REGISTERL", address);
}

/* LD A,(REGISTER+dd) */
fn disassembleDD__LD_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,(REGISTER+dd)", address);
}

/* ADD A,REGISTERH */
fn disassembleDD__ADD_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,REGISTERH", address);
}

/* ADD A,REGISTERL */
fn disassembleDD__ADD_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,REGISTERL", address);
}

/* ADD A,(REGISTER+dd) */
fn disassembleDD__ADD_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,(REGISTER+dd)", address);
}

/* ADC A,REGISTERH */
fn disassembleDD__ADC_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,REGISTERH", address);
}

/* ADC A,REGISTERL */
fn disassembleDD__ADC_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,REGISTERL", address);
}

/* ADC A,(REGISTER+dd) */
fn disassembleDD__ADC_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,(REGISTER+dd)", address);
}

/* SUB A,REGISTERH */
fn disassembleDD__SUB_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,REGISTERH", address);
}

/* SUB A,REGISTERL */
fn disassembleDD__SUB_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,REGISTERL", address);
}

/* SUB A,(REGISTER+dd) */
fn disassembleDD__SUB_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,(REGISTER+dd)", address);
}

/* SBC A,REGISTERH */
fn disassembleDD__SBC_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,REGISTERH", address);
}

/* SBC A,REGISTERL */
fn disassembleDD__SBC_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,REGISTERL", address);
}

/* SBC A,(REGISTER+dd) */
fn disassembleDD__SBC_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,(REGISTER+dd)", address);
}

/* AND A,REGISTERH */
fn disassembleDD__AND_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,REGISTERH", address);
}

/* AND A,REGISTERL */
fn disassembleDD__AND_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,REGISTERL", address);
}

/* AND A,(REGISTER+dd) */
fn disassembleDD__AND_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,(REGISTER+dd)", address);
}

/* XOR A,REGISTERH */
fn disassembleDD__XOR_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,REGISTERH", address);
}

/* XOR A,REGISTERL */
fn disassembleDD__XOR_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,REGISTERL", address);
}

/* XOR A,(REGISTER+dd) */
fn disassembleDD__XOR_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,(REGISTER+dd)", address);
}

/* OR A,REGISTERH */
fn disassembleDD__OR_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,REGISTERH", address);
}

/* OR A,REGISTERL */
fn disassembleDD__OR_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,REGISTERL", address);
}

/* OR A,(REGISTER+dd) */
fn disassembleDD__OR_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,(REGISTER+dd)", address);
}

/* CP A,REGISTERH */
fn disassembleDD__CP_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP A,REGISTERH", address);
}

/* CP A,REGISTERL */
fn disassembleDD__CP_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP A,REGISTERL", address);
}

/* CP A,(REGISTER+dd) */
fn disassembleDD__CP_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP A,(REGISTER+dd)", address);
}

/* shift DDFDCB */
fn disassembleDD__SHIFT_DDFDCB(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) shift DDFDCB", address);
}

/* POP REGISTER */
fn disassembleDD__POP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) POP REGISTER", address);
}

/* EX (SP),REGISTER */
fn disassembleDD__EX_iSP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) EX (SP),REGISTER", address);
}

/* PUSH REGISTER */
fn disassembleDD__PUSH_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) PUSH REGISTER", address);
}

/* JP REGISTER */
fn disassembleDD__JP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) JP REGISTER", address);
}

/* LD SP,REGISTER */
fn disassembleDD__LD_SP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD SP,REGISTER", address);
}

/* ADD REGISTER,BC */
fn disassembleFD__ADD_REG_BC(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD REGISTER,BC", address);
}

/* ADD REGISTER,DE */
fn disassembleFD__ADD_REG_DE(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD REGISTER,DE", address);
}

/* LD REGISTER,nnnn */
fn disassembleFD__LD_REG_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTER,nnnn", address);
}

/* LD (nnnn),REGISTER */
fn disassembleFD__LD_iNNNN_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD (0x{:04x}),iy", address, nnnn);
}

/* INC REGISTER */
fn disassembleFD__INC_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC REGISTER", address);
}

/* INC REGISTERH */
fn disassembleFD__INC_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC REGISTERH", address);
}

/* DEC REGISTERH */
fn disassembleFD__DEC_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC REGISTERH", address);
}

/* LD REGISTERH,nn */
fn disassembleFD__LD_REGH_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) LD IYH,0x{:02x}", address, nn);
}

/* ADD REGISTER,REGISTER */
fn disassembleFD__ADD_REG_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD REGISTER,REGISTER", address);
}

/* LD REGISTER,(nnnn) */
fn disassembleFD__LD_REG_iNNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let b1 = memory.read_byte(address + 1);
    let b2 = memory.read_byte(address + 2);
    let nnnn = join_bytes(b2, b1);
    println!("({:04x}) LD iy,(0x{:04x})", address, nnnn);
}

/* DEC REGISTER */
fn disassembleFD__DEC_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC REGISTER", address);
}

/* INC REGISTERL */
fn disassembleFD__INC_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC REGISTERL", address);
}

/* DEC REGISTERL */
fn disassembleFD__DEC_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC REGISTERL", address);
}

/* LD REGISTERL,nn */
fn disassembleFD__LD_REGL_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let nn = memory.read_byte(address + 1);
    println!("({:04x}) LD IYL,0x{:02x}", address, nn);
}

/* INC (REGISTER+dd) */
fn disassembleFD__INC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) INC (REGISTER+dd)", address);
}

/* DEC (REGISTER+dd) */
fn disassembleFD__DEC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) DEC (REGISTER+dd)", address);
}

/* LD (REGISTER+dd),nn */
fn disassembleFD__LD_iREGpDD_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    let iy_dd = memory.read_byte(address + 1);
    let nn = memory.read_byte(address + 2);
    println!("({:04x}) LD (iy+0x{:02x}),0x{:02x}", address, iy_dd, nn);
}

/* ADD REGISTER,SP */
fn disassembleFD__ADD_REG_SP(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD REGISTER,SP", address);
}

/* LD B,REGISTERH */
fn disassembleFD__LD_B_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,REGISTERH", address);
}

/* LD B,REGISTERL */
fn disassembleFD__LD_B_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,REGISTERL", address);
}

/* LD B,(REGISTER+dd) */
fn disassembleFD__LD_B_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,(REGISTER+dd)", address);
}

/* LD C,REGISTERH */
fn disassembleFD__LD_C_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,REGISTERH", address);
}

/* LD C,REGISTERL */
fn disassembleFD__LD_C_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,REGISTERL", address);
}

/* LD C,(REGISTER+dd) */
fn disassembleFD__LD_C_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,(REGISTER+dd)", address);
}

/* LD D,REGISTERH */
fn disassembleFD__LD_D_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,REGISTERH", address);
}

/* LD D,REGISTERL */
fn disassembleFD__LD_D_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,REGISTERL", address);
}

/* LD D,(REGISTER+dd) */
fn disassembleFD__LD_D_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,(REGISTER+dd)", address);
}

/* LD E,REGISTERH */
fn disassembleFD__LD_E_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,REGISTERH", address);
}

/* LD E,REGISTERL */
fn disassembleFD__LD_E_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,REGISTERL", address);
}

/* LD E,(REGISTER+dd) */
fn disassembleFD__LD_E_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,(REGISTER+dd)", address);
}

/* LD REGISTERH,B */
fn disassembleFD__LD_REGH_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,B", address);
}

/* LD REGISTERH,C */
fn disassembleFD__LD_REGH_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,C", address);
}

/* LD REGISTERH,D */
fn disassembleFD__LD_REGH_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,D", address);
}

/* LD REGISTERH,E */
fn disassembleFD__LD_REGH_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,E", address);
}

/* LD REGISTERH,REGISTERH */
fn disassembleFD__LD_REGH_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,REGISTERH", address);
}

/* LD REGISTERH,REGISTERL */
fn disassembleFD__LD_REGH_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,REGISTERL", address);
}

/* LD H,(REGISTER+dd) */
fn disassembleFD__LD_H_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,(REGISTER+dd)", address);
}

/* LD REGISTERH,A */
fn disassembleFD__LD_REGH_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERH,A", address);
}

/* LD REGISTERL,B */
fn disassembleFD__LD_REGL_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,B", address);
}

/* LD REGISTERL,C */
fn disassembleFD__LD_REGL_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,C", address);
}

/* LD REGISTERL,D */
fn disassembleFD__LD_REGL_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,D", address);
}

/* LD REGISTERL,E */
fn disassembleFD__LD_REGL_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,E", address);
}

/* LD REGISTERL,REGISTERH */
fn disassembleFD__LD_REGL_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,REGISTERH", address);
}

/* LD REGISTERL,REGISTERL */
fn disassembleFD__LD_REGL_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,REGISTERL", address);
}

/* LD L,(REGISTER+dd) */
fn disassembleFD__LD_L_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,(REGISTER+dd)", address);
}

/* LD REGISTERL,A */
fn disassembleFD__LD_REGL_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD REGISTERL,A", address);
}

/* LD (REGISTER+dd),B */
fn disassembleFD__LD_iREGpDD_B(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),B", address);
}

/* LD (REGISTER+dd),C */
fn disassembleFD__LD_iREGpDD_C(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),C", address);
}

/* LD (REGISTER+dd),D */
fn disassembleFD__LD_iREGpDD_D(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),D", address);
}

/* LD (REGISTER+dd),E */
fn disassembleFD__LD_iREGpDD_E(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),E", address);
}

/* LD (REGISTER+dd),H */
fn disassembleFD__LD_iREGpDD_H(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),H", address);
}

/* LD (REGISTER+dd),L */
fn disassembleFD__LD_iREGpDD_L(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),L", address);
}

/* LD (REGISTER+dd),A */
fn disassembleFD__LD_iREGpDD_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD (REGISTER+dd),A", address);
}

/* LD A,REGISTERH */
fn disassembleFD__LD_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,REGISTERH", address);
}

/* LD A,REGISTERL */
fn disassembleFD__LD_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,REGISTERL", address);
}

/* LD A,(REGISTER+dd) */
fn disassembleFD__LD_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,(REGISTER+dd)", address);
}

/* ADD A,REGISTERH */
fn disassembleFD__ADD_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,REGISTERH", address);
}

/* ADD A,REGISTERL */
fn disassembleFD__ADD_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,REGISTERL", address);
}

/* ADD A,(REGISTER+dd) */
fn disassembleFD__ADD_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADD A,(REGISTER+dd)", address);
}

/* ADC A,REGISTERH */
fn disassembleFD__ADC_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,REGISTERH", address);
}

/* ADC A,REGISTERL */
fn disassembleFD__ADC_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,REGISTERL", address);
}

/* ADC A,(REGISTER+dd) */
fn disassembleFD__ADC_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) ADC A,(REGISTER+dd)", address);
}

/* SUB A,REGISTERH */
fn disassembleFD__SUB_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,REGISTERH", address);
}

/* SUB A,REGISTERL */
fn disassembleFD__SUB_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,REGISTERL", address);
}

/* SUB A,(REGISTER+dd) */
fn disassembleFD__SUB_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SUB A,(REGISTER+dd)", address);
}

/* SBC A,REGISTERH */
fn disassembleFD__SBC_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,REGISTERH", address);
}

/* SBC A,REGISTERL */
fn disassembleFD__SBC_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,REGISTERL", address);
}

/* SBC A,(REGISTER+dd) */
fn disassembleFD__SBC_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SBC A,(REGISTER+dd)", address);
}

/* AND A,REGISTERH */
fn disassembleFD__AND_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,REGISTERH", address);
}

/* AND A,REGISTERL */
fn disassembleFD__AND_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,REGISTERL", address);
}

/* AND A,(REGISTER+dd) */
fn disassembleFD__AND_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) AND A,(REGISTER+dd)", address);
}

/* XOR A,REGISTERH */
fn disassembleFD__XOR_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,REGISTERH", address);
}

/* XOR A,REGISTERL */
fn disassembleFD__XOR_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,REGISTERL", address);
}

/* XOR A,(REGISTER+dd) */
fn disassembleFD__XOR_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) XOR A,(REGISTER+dd)", address);
}

/* OR A,REGISTERH */
fn disassembleFD__OR_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,REGISTERH", address);
}

/* OR A,REGISTERL */
fn disassembleFD__OR_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,REGISTERL", address);
}

/* OR A,(REGISTER+dd) */
fn disassembleFD__OR_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) OR A,(REGISTER+dd)", address);
}

/* CP A,REGISTERH */
fn disassembleFD__CP_A_REGH(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP A,REGISTERH", address);
}

/* CP A,REGISTERL */
fn disassembleFD__CP_A_REGL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP A,REGISTERL", address);
}

/* CP A,(REGISTER+dd) */
fn disassembleFD__CP_A_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) CP A,(REGISTER+dd)", address);
}

/* shift DDFDCB */
fn disassembleFD__SHIFT_DDFDCB(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) shift DDFDCB", address);
}

/* POP REGISTER */
fn disassembleFD__POP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) POP REGISTER", address);
}

/* EX (SP),REGISTER */
fn disassembleFD__EX_iSP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) EX (SP),REGISTER", address);
}

/* PUSH REGISTER */
fn disassembleFD__PUSH_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) PUSH REGISTER", address);
}

/* JP REGISTER */
fn disassembleFD__JP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) JP REGISTER", address);
}

/* LD SP,REGISTER */
fn disassembleFD__LD_SP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD SP,REGISTER", address);
}

/* LD B,RLC (REGISTER+dd) */
fn disassembleDDCB__LD_B_RLC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RLC (REGISTER+dd)", address);
}

/* LD C,RLC (REGISTER+dd) */
fn disassembleDDCB__LD_C_RLC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RLC (REGISTER+dd)", address);
}

/* LD D,RLC (REGISTER+dd) */
fn disassembleDDCB__LD_D_RLC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RLC (REGISTER+dd)", address);
}

/* LD E,RLC (REGISTER+dd) */
fn disassembleDDCB__LD_E_RLC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RLC (REGISTER+dd)", address);
}

/* LD H,RLC (REGISTER+dd) */
fn disassembleDDCB__LD_H_RLC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RLC (REGISTER+dd)", address);
}

/* LD L,RLC (REGISTER+dd) */
fn disassembleDDCB__LD_L_RLC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RLC (REGISTER+dd)", address);
}

/* RLC (REGISTER+dd) */
fn disassembleDDCB__RLC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RLC (REGISTER+dd)", address);
}

/* LD A,RLC (REGISTER+dd) */
fn disassembleDDCB__LD_A_RLC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RLC (REGISTER+dd)", address);
}

/* LD B,RRC (REGISTER+dd) */
fn disassembleDDCB__LD_B_RRC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RRC (REGISTER+dd)", address);
}

/* LD C,RRC (REGISTER+dd) */
fn disassembleDDCB__LD_C_RRC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RRC (REGISTER+dd)", address);
}

/* LD D,RRC (REGISTER+dd) */
fn disassembleDDCB__LD_D_RRC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RRC (REGISTER+dd)", address);
}

/* LD E,RRC (REGISTER+dd) */
fn disassembleDDCB__LD_E_RRC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RRC (REGISTER+dd)", address);
}

/* LD H,RRC (REGISTER+dd) */
fn disassembleDDCB__LD_H_RRC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RRC (REGISTER+dd)", address);
}

/* LD L,RRC (REGISTER+dd) */
fn disassembleDDCB__LD_L_RRC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RRC (REGISTER+dd)", address);
}

/* RRC (REGISTER+dd) */
fn disassembleDDCB__RRC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RRC (REGISTER+dd)", address);
}

/* LD A,RRC (REGISTER+dd) */
fn disassembleDDCB__LD_A_RRC_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RRC (REGISTER+dd)", address);
}

/* LD B,RL (REGISTER+dd) */
fn disassembleDDCB__LD_B_RL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RL (REGISTER+dd)", address);
}

/* LD C,RL (REGISTER+dd) */
fn disassembleDDCB__LD_C_RL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RL (REGISTER+dd)", address);
}

/* LD D,RL (REGISTER+dd) */
fn disassembleDDCB__LD_D_RL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RL (REGISTER+dd)", address);
}

/* LD E,RL (REGISTER+dd) */
fn disassembleDDCB__LD_E_RL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RL (REGISTER+dd)", address);
}

/* LD H,RL (REGISTER+dd) */
fn disassembleDDCB__LD_H_RL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RL (REGISTER+dd)", address);
}

/* LD L,RL (REGISTER+dd) */
fn disassembleDDCB__LD_L_RL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RL (REGISTER+dd)", address);
}

/* RL (REGISTER+dd) */
fn disassembleDDCB__RL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RL (REGISTER+dd)", address);
}

/* LD A,RL (REGISTER+dd) */
fn disassembleDDCB__LD_A_RL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RL (REGISTER+dd)", address);
}

/* LD B,RR (REGISTER+dd) */
fn disassembleDDCB__LD_B_RR_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RR (REGISTER+dd)", address);
}

/* LD C,RR (REGISTER+dd) */
fn disassembleDDCB__LD_C_RR_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RR (REGISTER+dd)", address);
}

/* LD D,RR (REGISTER+dd) */
fn disassembleDDCB__LD_D_RR_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RR (REGISTER+dd)", address);
}

/* LD E,RR (REGISTER+dd) */
fn disassembleDDCB__LD_E_RR_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RR (REGISTER+dd)", address);
}

/* LD H,RR (REGISTER+dd) */
fn disassembleDDCB__LD_H_RR_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RR (REGISTER+dd)", address);
}

/* LD L,RR (REGISTER+dd) */
fn disassembleDDCB__LD_L_RR_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RR (REGISTER+dd)", address);
}

/* RR (REGISTER+dd) */
fn disassembleDDCB__RR_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RR (REGISTER+dd)", address);
}

/* LD A,RR (REGISTER+dd) */
fn disassembleDDCB__LD_A_RR_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RR (REGISTER+dd)", address);
}

/* LD B,SLA (REGISTER+dd) */
fn disassembleDDCB__LD_B_SLA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SLA (REGISTER+dd)", address);
}

/* LD C,SLA (REGISTER+dd) */
fn disassembleDDCB__LD_C_SLA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SLA (REGISTER+dd)", address);
}

/* LD D,SLA (REGISTER+dd) */
fn disassembleDDCB__LD_D_SLA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SLA (REGISTER+dd)", address);
}

/* LD E,SLA (REGISTER+dd) */
fn disassembleDDCB__LD_E_SLA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SLA (REGISTER+dd)", address);
}

/* LD H,SLA (REGISTER+dd) */
fn disassembleDDCB__LD_H_SLA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SLA (REGISTER+dd)", address);
}

/* LD L,SLA (REGISTER+dd) */
fn disassembleDDCB__LD_L_SLA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SLA (REGISTER+dd)", address);
}

/* SLA (REGISTER+dd) */
fn disassembleDDCB__SLA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLA (REGISTER+dd)", address);
}

/* LD A,SLA (REGISTER+dd) */
fn disassembleDDCB__LD_A_SLA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SLA (REGISTER+dd)", address);
}

/* LD B,SRA (REGISTER+dd) */
fn disassembleDDCB__LD_B_SRA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SRA (REGISTER+dd)", address);
}

/* LD C,SRA (REGISTER+dd) */
fn disassembleDDCB__LD_C_SRA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SRA (REGISTER+dd)", address);
}

/* LD D,SRA (REGISTER+dd) */
fn disassembleDDCB__LD_D_SRA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SRA (REGISTER+dd)", address);
}

/* LD E,SRA (REGISTER+dd) */
fn disassembleDDCB__LD_E_SRA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SRA (REGISTER+dd)", address);
}

/* LD H,SRA (REGISTER+dd) */
fn disassembleDDCB__LD_H_SRA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SRA (REGISTER+dd)", address);
}

/* LD L,SRA (REGISTER+dd) */
fn disassembleDDCB__LD_L_SRA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SRA (REGISTER+dd)", address);
}

/* SRA (REGISTER+dd) */
fn disassembleDDCB__SRA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRA (REGISTER+dd)", address);
}

/* LD A,SRA (REGISTER+dd) */
fn disassembleDDCB__LD_A_SRA_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SRA (REGISTER+dd)", address);
}

/* LD B,SLL (REGISTER+dd) */
fn disassembleDDCB__LD_B_SLL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SLL (REGISTER+dd)", address);
}

/* LD C,SLL (REGISTER+dd) */
fn disassembleDDCB__LD_C_SLL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SLL (REGISTER+dd)", address);
}

/* LD D,SLL (REGISTER+dd) */
fn disassembleDDCB__LD_D_SLL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SLL (REGISTER+dd)", address);
}

/* LD E,SLL (REGISTER+dd) */
fn disassembleDDCB__LD_E_SLL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SLL (REGISTER+dd)", address);
}

/* LD H,SLL (REGISTER+dd) */
fn disassembleDDCB__LD_H_SLL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SLL (REGISTER+dd)", address);
}

/* LD L,SLL (REGISTER+dd) */
fn disassembleDDCB__LD_L_SLL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SLL (REGISTER+dd)", address);
}

/* SLL (REGISTER+dd) */
fn disassembleDDCB__SLL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SLL (REGISTER+dd)", address);
}

/* LD A,SLL (REGISTER+dd) */
fn disassembleDDCB__LD_A_SLL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SLL (REGISTER+dd)", address);
}

/* LD B,SRL (REGISTER+dd) */
fn disassembleDDCB__LD_B_SRL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SRL (REGISTER+dd)", address);
}

/* LD C,SRL (REGISTER+dd) */
fn disassembleDDCB__LD_C_SRL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SRL (REGISTER+dd)", address);
}

/* LD D,SRL (REGISTER+dd) */
fn disassembleDDCB__LD_D_SRL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SRL (REGISTER+dd)", address);
}

/* LD E,SRL (REGISTER+dd) */
fn disassembleDDCB__LD_E_SRL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SRL (REGISTER+dd)", address);
}

/* LD H,SRL (REGISTER+dd) */
fn disassembleDDCB__LD_H_SRL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SRL (REGISTER+dd)", address);
}

/* LD L,SRL (REGISTER+dd) */
fn disassembleDDCB__LD_L_SRL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SRL (REGISTER+dd)", address);
}

/* SRL (REGISTER+dd) */
fn disassembleDDCB__SRL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SRL (REGISTER+dd)", address);
}

/* LD A,SRL (REGISTER+dd) */
fn disassembleDDCB__LD_A_SRL_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SRL (REGISTER+dd)", address);
}

/* BIT 0,(REGISTER+dd) */
fn disassembleDDCB__BIT_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 0,(REGISTER+dd)", address);
}

/* BIT 1,(REGISTER+dd) */
fn disassembleDDCB__BIT_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 1,(REGISTER+dd)", address);
}

/* BIT 2,(REGISTER+dd) */
fn disassembleDDCB__BIT_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 2,(REGISTER+dd)", address);
}

/* BIT 3,(REGISTER+dd) */
fn disassembleDDCB__BIT_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 3,(REGISTER+dd)", address);
}

/* BIT 4,(REGISTER+dd) */
fn disassembleDDCB__BIT_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 4,(REGISTER+dd)", address);
}

/* BIT 5,(REGISTER+dd) */
fn disassembleDDCB__BIT_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 5,(REGISTER+dd)", address);
}

/* BIT 6,(REGISTER+dd) */
fn disassembleDDCB__BIT_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 6,(REGISTER+dd)", address);
}

/* BIT 7,(REGISTER+dd) */
fn disassembleDDCB__BIT_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) BIT 7,(REGISTER+dd)", address);
}

/* LD B,RES 0,(REGISTER+dd) */
fn disassembleDDCB__LD_B_RES_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RES 0,(REGISTER+dd)", address);
}

/* LD C,RES 0,(REGISTER+dd) */
fn disassembleDDCB__LD_C_RES_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RES 0,(REGISTER+dd)", address);
}

/* LD D,RES 0,(REGISTER+dd) */
fn disassembleDDCB__LD_D_RES_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RES 0,(REGISTER+dd)", address);
}

/* LD E,RES 0,(REGISTER+dd) */
fn disassembleDDCB__LD_E_RES_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RES 0,(REGISTER+dd)", address);
}

/* LD H,RES 0,(REGISTER+dd) */
fn disassembleDDCB__LD_H_RES_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RES 0,(REGISTER+dd)", address);
}

/* LD L,RES 0,(REGISTER+dd) */
fn disassembleDDCB__LD_L_RES_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RES 0,(REGISTER+dd)", address);
}

/* RES 0,(REGISTER+dd) */
fn disassembleDDCB__RES_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 0,(REGISTER+dd)", address);
}

/* LD A,RES 0,(REGISTER+dd) */
fn disassembleDDCB__LD_A_RES_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RES 0,(REGISTER+dd)", address);
}

/* LD B,RES 1,(REGISTER+dd) */
fn disassembleDDCB__LD_B_RES_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RES 1,(REGISTER+dd)", address);
}

/* LD C,RES 1,(REGISTER+dd) */
fn disassembleDDCB__LD_C_RES_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RES 1,(REGISTER+dd)", address);
}

/* LD D,RES 1,(REGISTER+dd) */
fn disassembleDDCB__LD_D_RES_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RES 1,(REGISTER+dd)", address);
}

/* LD E,RES 1,(REGISTER+dd) */
fn disassembleDDCB__LD_E_RES_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RES 1,(REGISTER+dd)", address);
}

/* LD H,RES 1,(REGISTER+dd) */
fn disassembleDDCB__LD_H_RES_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RES 1,(REGISTER+dd)", address);
}

/* LD L,RES 1,(REGISTER+dd) */
fn disassembleDDCB__LD_L_RES_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RES 1,(REGISTER+dd)", address);
}

/* RES 1,(REGISTER+dd) */
fn disassembleDDCB__RES_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 1,(REGISTER+dd)", address);
}

/* LD A,RES 1,(REGISTER+dd) */
fn disassembleDDCB__LD_A_RES_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RES 1,(REGISTER+dd)", address);
}

/* LD B,RES 2,(REGISTER+dd) */
fn disassembleDDCB__LD_B_RES_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RES 2,(REGISTER+dd)", address);
}

/* LD C,RES 2,(REGISTER+dd) */
fn disassembleDDCB__LD_C_RES_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RES 2,(REGISTER+dd)", address);
}

/* LD D,RES 2,(REGISTER+dd) */
fn disassembleDDCB__LD_D_RES_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RES 2,(REGISTER+dd)", address);
}

/* LD E,RES 2,(REGISTER+dd) */
fn disassembleDDCB__LD_E_RES_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RES 2,(REGISTER+dd)", address);
}

/* LD H,RES 2,(REGISTER+dd) */
fn disassembleDDCB__LD_H_RES_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RES 2,(REGISTER+dd)", address);
}

/* LD L,RES 2,(REGISTER+dd) */
fn disassembleDDCB__LD_L_RES_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RES 2,(REGISTER+dd)", address);
}

/* RES 2,(REGISTER+dd) */
fn disassembleDDCB__RES_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 2,(REGISTER+dd)", address);
}

/* LD A,RES 2,(REGISTER+dd) */
fn disassembleDDCB__LD_A_RES_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RES 2,(REGISTER+dd)", address);
}

/* LD B,RES 3,(REGISTER+dd) */
fn disassembleDDCB__LD_B_RES_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RES 3,(REGISTER+dd)", address);
}

/* LD C,RES 3,(REGISTER+dd) */
fn disassembleDDCB__LD_C_RES_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RES 3,(REGISTER+dd)", address);
}

/* LD D,RES 3,(REGISTER+dd) */
fn disassembleDDCB__LD_D_RES_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RES 3,(REGISTER+dd)", address);
}

/* LD E,RES 3,(REGISTER+dd) */
fn disassembleDDCB__LD_E_RES_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RES 3,(REGISTER+dd)", address);
}

/* LD H,RES 3,(REGISTER+dd) */
fn disassembleDDCB__LD_H_RES_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RES 3,(REGISTER+dd)", address);
}

/* LD L,RES 3,(REGISTER+dd) */
fn disassembleDDCB__LD_L_RES_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RES 3,(REGISTER+dd)", address);
}

/* RES 3,(REGISTER+dd) */
fn disassembleDDCB__RES_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 3,(REGISTER+dd)", address);
}

/* LD A,RES 3,(REGISTER+dd) */
fn disassembleDDCB__LD_A_RES_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RES 3,(REGISTER+dd)", address);
}

/* LD B,RES 4,(REGISTER+dd) */
fn disassembleDDCB__LD_B_RES_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RES 4,(REGISTER+dd)", address);
}

/* LD C,RES 4,(REGISTER+dd) */
fn disassembleDDCB__LD_C_RES_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RES 4,(REGISTER+dd)", address);
}

/* LD D,RES 4,(REGISTER+dd) */
fn disassembleDDCB__LD_D_RES_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RES 4,(REGISTER+dd)", address);
}

/* LD E,RES 4,(REGISTER+dd) */
fn disassembleDDCB__LD_E_RES_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RES 4,(REGISTER+dd)", address);
}

/* LD H,RES 4,(REGISTER+dd) */
fn disassembleDDCB__LD_H_RES_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RES 4,(REGISTER+dd)", address);
}

/* LD L,RES 4,(REGISTER+dd) */
fn disassembleDDCB__LD_L_RES_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RES 4,(REGISTER+dd)", address);
}

/* RES 4,(REGISTER+dd) */
fn disassembleDDCB__RES_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 4,(REGISTER+dd)", address);
}

/* LD A,RES 4,(REGISTER+dd) */
fn disassembleDDCB__LD_A_RES_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RES 4,(REGISTER+dd)", address);
}

/* LD B,RES 5,(REGISTER+dd) */
fn disassembleDDCB__LD_B_RES_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RES 5,(REGISTER+dd)", address);
}

/* LD C,RES 5,(REGISTER+dd) */
fn disassembleDDCB__LD_C_RES_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RES 5,(REGISTER+dd)", address);
}

/* LD D,RES 5,(REGISTER+dd) */
fn disassembleDDCB__LD_D_RES_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RES 5,(REGISTER+dd)", address);
}

/* LD E,RES 5,(REGISTER+dd) */
fn disassembleDDCB__LD_E_RES_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RES 5,(REGISTER+dd)", address);
}

/* LD H,RES 5,(REGISTER+dd) */
fn disassembleDDCB__LD_H_RES_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RES 5,(REGISTER+dd)", address);
}

/* LD L,RES 5,(REGISTER+dd) */
fn disassembleDDCB__LD_L_RES_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RES 5,(REGISTER+dd)", address);
}

/* RES 5,(REGISTER+dd) */
fn disassembleDDCB__RES_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 5,(REGISTER+dd)", address);
}

/* LD A,RES 5,(REGISTER+dd) */
fn disassembleDDCB__LD_A_RES_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RES 5,(REGISTER+dd)", address);
}

/* LD B,RES 6,(REGISTER+dd) */
fn disassembleDDCB__LD_B_RES_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RES 6,(REGISTER+dd)", address);
}

/* LD C,RES 6,(REGISTER+dd) */
fn disassembleDDCB__LD_C_RES_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RES 6,(REGISTER+dd)", address);
}

/* LD D,RES 6,(REGISTER+dd) */
fn disassembleDDCB__LD_D_RES_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RES 6,(REGISTER+dd)", address);
}

/* LD E,RES 6,(REGISTER+dd) */
fn disassembleDDCB__LD_E_RES_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RES 6,(REGISTER+dd)", address);
}

/* LD H,RES 6,(REGISTER+dd) */
fn disassembleDDCB__LD_H_RES_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RES 6,(REGISTER+dd)", address);
}

/* LD L,RES 6,(REGISTER+dd) */
fn disassembleDDCB__LD_L_RES_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RES 6,(REGISTER+dd)", address);
}

/* RES 6,(REGISTER+dd) */
fn disassembleDDCB__RES_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 6,(REGISTER+dd)", address);
}

/* LD A,RES 6,(REGISTER+dd) */
fn disassembleDDCB__LD_A_RES_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RES 6,(REGISTER+dd)", address);
}

/* LD B,RES 7,(REGISTER+dd) */
fn disassembleDDCB__LD_B_RES_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,RES 7,(REGISTER+dd)", address);
}

/* LD C,RES 7,(REGISTER+dd) */
fn disassembleDDCB__LD_C_RES_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,RES 7,(REGISTER+dd)", address);
}

/* LD D,RES 7,(REGISTER+dd) */
fn disassembleDDCB__LD_D_RES_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,RES 7,(REGISTER+dd)", address);
}

/* LD E,RES 7,(REGISTER+dd) */
fn disassembleDDCB__LD_E_RES_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,RES 7,(REGISTER+dd)", address);
}

/* LD H,RES 7,(REGISTER+dd) */
fn disassembleDDCB__LD_H_RES_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,RES 7,(REGISTER+dd)", address);
}

/* LD L,RES 7,(REGISTER+dd) */
fn disassembleDDCB__LD_L_RES_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,RES 7,(REGISTER+dd)", address);
}

/* RES 7,(REGISTER+dd) */
fn disassembleDDCB__RES_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) RES 7,(REGISTER+dd)", address);
}

/* LD A,RES 7,(REGISTER+dd) */
fn disassembleDDCB__LD_A_RES_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,RES 7,(REGISTER+dd)", address);
}

/* LD B,SET 0,(REGISTER+dd) */
fn disassembleDDCB__LD_B_SET_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SET 0,(REGISTER+dd)", address);
}

/* LD C,SET 0,(REGISTER+dd) */
fn disassembleDDCB__LD_C_SET_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SET 0,(REGISTER+dd)", address);
}

/* LD D,SET 0,(REGISTER+dd) */
fn disassembleDDCB__LD_D_SET_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SET 0,(REGISTER+dd)", address);
}

/* LD E,SET 0,(REGISTER+dd) */
fn disassembleDDCB__LD_E_SET_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SET 0,(REGISTER+dd)", address);
}

/* LD H,SET 0,(REGISTER+dd) */
fn disassembleDDCB__LD_H_SET_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SET 0,(REGISTER+dd)", address);
}

/* LD L,SET 0,(REGISTER+dd) */
fn disassembleDDCB__LD_L_SET_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SET 0,(REGISTER+dd)", address);
}

/* SET 0,(REGISTER+dd) */
fn disassembleDDCB__SET_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 0,(REGISTER+dd)", address);
}

/* LD A,SET 0,(REGISTER+dd) */
fn disassembleDDCB__LD_A_SET_0_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SET 0,(REGISTER+dd)", address);
}

/* LD B,SET 1,(REGISTER+dd) */
fn disassembleDDCB__LD_B_SET_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SET 1,(REGISTER+dd)", address);
}

/* LD C,SET 1,(REGISTER+dd) */
fn disassembleDDCB__LD_C_SET_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SET 1,(REGISTER+dd)", address);
}

/* LD D,SET 1,(REGISTER+dd) */
fn disassembleDDCB__LD_D_SET_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SET 1,(REGISTER+dd)", address);
}

/* LD E,SET 1,(REGISTER+dd) */
fn disassembleDDCB__LD_E_SET_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SET 1,(REGISTER+dd)", address);
}

/* LD H,SET 1,(REGISTER+dd) */
fn disassembleDDCB__LD_H_SET_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SET 1,(REGISTER+dd)", address);
}

/* LD L,SET 1,(REGISTER+dd) */
fn disassembleDDCB__LD_L_SET_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SET 1,(REGISTER+dd)", address);
}

/* SET 1,(REGISTER+dd) */
fn disassembleDDCB__SET_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 1,(REGISTER+dd)", address);
}

/* LD A,SET 1,(REGISTER+dd) */
fn disassembleDDCB__LD_A_SET_1_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SET 1,(REGISTER+dd)", address);
}

/* LD B,SET 2,(REGISTER+dd) */
fn disassembleDDCB__LD_B_SET_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SET 2,(REGISTER+dd)", address);
}

/* LD C,SET 2,(REGISTER+dd) */
fn disassembleDDCB__LD_C_SET_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SET 2,(REGISTER+dd)", address);
}

/* LD D,SET 2,(REGISTER+dd) */
fn disassembleDDCB__LD_D_SET_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SET 2,(REGISTER+dd)", address);
}

/* LD E,SET 2,(REGISTER+dd) */
fn disassembleDDCB__LD_E_SET_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SET 2,(REGISTER+dd)", address);
}

/* LD H,SET 2,(REGISTER+dd) */
fn disassembleDDCB__LD_H_SET_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SET 2,(REGISTER+dd)", address);
}

/* LD L,SET 2,(REGISTER+dd) */
fn disassembleDDCB__LD_L_SET_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SET 2,(REGISTER+dd)", address);
}

/* SET 2,(REGISTER+dd) */
fn disassembleDDCB__SET_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 2,(REGISTER+dd)", address);
}

/* LD A,SET 2,(REGISTER+dd) */
fn disassembleDDCB__LD_A_SET_2_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SET 2,(REGISTER+dd)", address);
}

/* LD B,SET 3,(REGISTER+dd) */
fn disassembleDDCB__LD_B_SET_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SET 3,(REGISTER+dd)", address);
}

/* LD C,SET 3,(REGISTER+dd) */
fn disassembleDDCB__LD_C_SET_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SET 3,(REGISTER+dd)", address);
}

/* LD D,SET 3,(REGISTER+dd) */
fn disassembleDDCB__LD_D_SET_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SET 3,(REGISTER+dd)", address);
}

/* LD E,SET 3,(REGISTER+dd) */
fn disassembleDDCB__LD_E_SET_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SET 3,(REGISTER+dd)", address);
}

/* LD H,SET 3,(REGISTER+dd) */
fn disassembleDDCB__LD_H_SET_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SET 3,(REGISTER+dd)", address);
}

/* LD L,SET 3,(REGISTER+dd) */
fn disassembleDDCB__LD_L_SET_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SET 3,(REGISTER+dd)", address);
}

/* SET 3,(REGISTER+dd) */
fn disassembleDDCB__SET_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 3,(REGISTER+dd)", address);
}

/* LD A,SET 3,(REGISTER+dd) */
fn disassembleDDCB__LD_A_SET_3_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SET 3,(REGISTER+dd)", address);
}

/* LD B,SET 4,(REGISTER+dd) */
fn disassembleDDCB__LD_B_SET_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SET 4,(REGISTER+dd)", address);
}

/* LD C,SET 4,(REGISTER+dd) */
fn disassembleDDCB__LD_C_SET_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SET 4,(REGISTER+dd)", address);
}

/* LD D,SET 4,(REGISTER+dd) */
fn disassembleDDCB__LD_D_SET_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SET 4,(REGISTER+dd)", address);
}

/* LD E,SET 4,(REGISTER+dd) */
fn disassembleDDCB__LD_E_SET_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SET 4,(REGISTER+dd)", address);
}

/* LD H,SET 4,(REGISTER+dd) */
fn disassembleDDCB__LD_H_SET_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SET 4,(REGISTER+dd)", address);
}

/* LD L,SET 4,(REGISTER+dd) */
fn disassembleDDCB__LD_L_SET_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SET 4,(REGISTER+dd)", address);
}

/* SET 4,(REGISTER+dd) */
fn disassembleDDCB__SET_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 4,(REGISTER+dd)", address);
}

/* LD A,SET 4,(REGISTER+dd) */
fn disassembleDDCB__LD_A_SET_4_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SET 4,(REGISTER+dd)", address);
}

/* LD B,SET 5,(REGISTER+dd) */
fn disassembleDDCB__LD_B_SET_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SET 5,(REGISTER+dd)", address);
}

/* LD C,SET 5,(REGISTER+dd) */
fn disassembleDDCB__LD_C_SET_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SET 5,(REGISTER+dd)", address);
}

/* LD D,SET 5,(REGISTER+dd) */
fn disassembleDDCB__LD_D_SET_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SET 5,(REGISTER+dd)", address);
}

/* LD E,SET 5,(REGISTER+dd) */
fn disassembleDDCB__LD_E_SET_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SET 5,(REGISTER+dd)", address);
}

/* LD H,SET 5,(REGISTER+dd) */
fn disassembleDDCB__LD_H_SET_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SET 5,(REGISTER+dd)", address);
}

/* LD L,SET 5,(REGISTER+dd) */
fn disassembleDDCB__LD_L_SET_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SET 5,(REGISTER+dd)", address);
}

/* SET 5,(REGISTER+dd) */
fn disassembleDDCB__SET_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 5,(REGISTER+dd)", address);
}

/* LD A,SET 5,(REGISTER+dd) */
fn disassembleDDCB__LD_A_SET_5_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SET 5,(REGISTER+dd)", address);
}

/* LD B,SET 6,(REGISTER+dd) */
fn disassembleDDCB__LD_B_SET_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SET 6,(REGISTER+dd)", address);
}

/* LD C,SET 6,(REGISTER+dd) */
fn disassembleDDCB__LD_C_SET_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SET 6,(REGISTER+dd)", address);
}

/* LD D,SET 6,(REGISTER+dd) */
fn disassembleDDCB__LD_D_SET_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SET 6,(REGISTER+dd)", address);
}

/* LD E,SET 6,(REGISTER+dd) */
fn disassembleDDCB__LD_E_SET_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SET 6,(REGISTER+dd)", address);
}

/* LD H,SET 6,(REGISTER+dd) */
fn disassembleDDCB__LD_H_SET_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SET 6,(REGISTER+dd)", address);
}

/* LD L,SET 6,(REGISTER+dd) */
fn disassembleDDCB__LD_L_SET_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SET 6,(REGISTER+dd)", address);
}

/* SET 6,(REGISTER+dd) */
fn disassembleDDCB__SET_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 6,(REGISTER+dd)", address);
}

/* LD A,SET 6,(REGISTER+dd) */
fn disassembleDDCB__LD_A_SET_6_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SET 6,(REGISTER+dd)", address);
}

/* LD B,SET 7,(REGISTER+dd) */
fn disassembleDDCB__LD_B_SET_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD B,SET 7,(REGISTER+dd)", address);
}

/* LD C,SET 7,(REGISTER+dd) */
fn disassembleDDCB__LD_C_SET_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD C,SET 7,(REGISTER+dd)", address);
}

/* LD D,SET 7,(REGISTER+dd) */
fn disassembleDDCB__LD_D_SET_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD D,SET 7,(REGISTER+dd)", address);
}

/* LD E,SET 7,(REGISTER+dd) */
fn disassembleDDCB__LD_E_SET_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD E,SET 7,(REGISTER+dd)", address);
}

/* LD H,SET 7,(REGISTER+dd) */
fn disassembleDDCB__LD_H_SET_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD H,SET 7,(REGISTER+dd)", address);
}

/* LD L,SET 7,(REGISTER+dd) */
fn disassembleDDCB__LD_L_SET_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD L,SET 7,(REGISTER+dd)", address);
}

/* SET 7,(REGISTER+dd) */
fn disassembleDDCB__SET_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) SET 7,(REGISTER+dd)", address);
}

/* LD A,SET 7,(REGISTER+dd) */
fn disassembleDDCB__LD_A_SET_7_iREGpDD(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc() - 1;
    println!("({:04x}) LD A,SET 7,(REGISTER+dd)", address);
}