librsmsx 0.3.13

#![allow(non_snake_case)]
// /*

// Copyright (c) 2010 Andrea Fazzi

// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:

// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// 8
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// */
use std::{cell::RefCell, rc::Rc};

use crate::libs::{memory::Memory, ports::Ports};

use super::{
    api::{
        adc, adc16, add, add16, and, bit, biti, call, cp, dec, in_u8_ex, inc, jp, jp_hl, jr,
        ld16nnrr, ld16rrnn_ex, or, pop16, push16, ret, rl, rlc, rr, rrc, rst, sbc, sbc16, sla, sll,
        slt_trap, sra, srl, sub, xor, FLAG_3, FLAG_5, FLAG_C, FLAG_H, FLAG_N, FLAG_P, FLAG_S,
        FLAG_V, FLAG_Z,
    },
    hook::FuncHook,
    util::{join_bytes, sign_extend, split_word, tern_op_b},
    z80_base::{
        Register16, Z80Data, SHIFT_0X_CB, SHIFT_0X_DD, SHIFT_0X_DDCB, SHIFT_0X_ED, SHIFT_0X_FD,
    },
    z80_tables::{self, HALF_CARRY_SUB_TABLE},
};

macro_rules! fn_instr_ld_r16_nnnn {
    ($fn:tt, $r:ident, $fs:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let address = data.pc();
            let b1 = memory.read_byte(address);
            data.inc_pc(1);
            let address = data.pc();
            let b2 = memory.read_byte(address);
            data.inc_pc(1);
            data.$fs(join_bytes(b2, b1));
        }
    };
}

macro_rules! fn_instr_ld_i_nnnn_r16 {
    ($fn:tt, $rl:ident, $rh:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            ld16nnrr(data, memory, data.$rl, data.$rh);
        }
    };
}

macro_rules! fn_instr_ld_i_r16_r8 {
    ($fn:tt, $r16:ident, $r8:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            memory.write_byte(data.$r16(), data.$r8);
        }
    };
}

macro_rules! fn_instr_add_r8 {
    ($fn:tt, $r8:ident) => {
        pub fn $fn(data: &mut Z80Data) {
            add(data, data.$r8);
        }
    };
}

macro_rules! fn_instr_adc_r8 {
    ($fn:tt, $r8:ident) => {
        pub fn $fn(data: &mut Z80Data) {
            adc(data, data.$r8);
        }
    };
}

macro_rules! fn_instr_sub_r8 {
    ($fn:tt, $r8:ident) => {
        pub fn $fn(data: &mut Z80Data) {
            sub(data, data.$r8);
        }
    };
}

macro_rules! fn_instr_sbc_r8 {
    ($fn:tt, $r8:ident) => {
        pub fn $fn(data: &mut Z80Data) {
            sbc(data, data.$r8);
        }
    };
}

macro_rules! fn_instr_and_r8 {
    ($fn:tt, $r8:ident) => {
        pub fn $fn(data: &mut Z80Data) {
            and(data, data.$r8);
        }
    };
}

macro_rules! fn_instr_xor_r8 {
    ($fn:tt, $r8:ident) => {
        pub fn $fn(data: &mut Z80Data) {
            xor(data, data.$r8);
        }
    };
}

macro_rules! fn_instr_or_r8 {
    ($fn:tt, $r8:ident) => {
        pub fn $fn(data: &mut Z80Data) {
            or(data, data.$r8);
        }
    };
}

macro_rules! fn_instr_cp_r8 {
    ($fn:tt, $r8:ident) => {
        pub fn $fn(data: &mut Z80Data) {
            cp(data, data.$r8);
        }
    };
}

macro_rules! fn_instr_pop_r16 {
    ($fn:tt, $rl:ident, $rh:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            (data.$rl, data.$rh) = pop16(data, memory);
        }
    };
}

macro_rules! fn_instr_push_r16 {
    ($fn:tt, $rl:ident, $rh:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let _address = data.ir();
            memory.contend_read_no_mreq(_address, 1);
            push16(data, memory, data.$rl, data.$rh);
        }
    };
}

macro_rules! fn_instr_ld_a_r16 {
    ($fn:tt, $r16:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let address = data.$r16();
            data.A = memory.read_byte(address);
        }
    };
}

macro_rules! fn_instr_ld_a_r8 {
    ($fn:tt, $r8:ident) => {
        pub fn $fn(data: &mut Z80Data) {
            data.A = data.$r8;
        }
    };
}

macro_rules! fn_instr_op_16 {
    ($fn:tt, $op:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let _address = data.ir();
            memory.contend_read_no_mreq_loop(_address, 1, 2);
            data.$op();
        }
    };
}

macro_rules! fn_instr_op_8 {
    ($fn:tt, $op:ident) => {
        pub fn $fn(data: &mut Z80Data) {
            data.$op();
        }
    };
}

macro_rules! fn_instr_ld_r8_nn {
    ($fn:tt, $r:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let address = data.pc();
            data.$r = memory.read_byte(address);
            data.inc_pc(1);
        }
    };
}

macro_rules! fn_instr_add_hl_r16 {
    ($fn:tt, $r16:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let _address = data.ir();
            memory.contend_read_no_mreq_loop(_address, 1, 7);
            let mut hl = Register16::new(data.H, data.L);
            let value2 = data.$r16();
            add16(data, &mut hl, value2);
            (data.H, data.L) = hl.result();
        }
    };
}

macro_rules! fn_instr_ld_hl_i_nnnn {
    ($fn:tt, $rl:ident, $rh:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            (data.$rl, data.$rh) = ld16rrnn_ex(data, memory);
        }
    };
}

macro_rules! fn_instr_ld_i_reg_p_dd_r8 {
    ($fn:tt, $ri:ident, $r:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let address = data.pc();
            let offset = memory.read_byte(address);
            let _address = data.pc();
            memory.contend_read_no_mreq_loop(_address, 1, 5);
            data.inc_pc(1);
            memory.write_byte(data.$ri() + (sign_extend(offset) as u16), data.$r)
        }
    };
}

macro_rules! fn_instr_op_a_i_reg_p_dd {
    ($fn:tt, $r:ident, $op:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let address = data.pc();
            let offset: u8 = memory.read_byte(address);
            let _address = data.pc();
            memory.contend_read_no_mreq_loop(_address, 1, 5);
            data.inc_pc(1);
            let byte_temp: u8 = memory.read_byte(data.$r() + (sign_extend(offset) as u16));
            $op(data, byte_temp)
        }
    };
}

macro_rules! fn_instr_op_a_i_reg_p_dd_d {
    ($fn:tt, $r:ident, $op:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let address = data.pc();
            let offset: u8 = memory.read_byte(address);
            let _address = data.pc();
            memory.contend_read_no_mreq_loop(_address, 1, 5);
            data.inc_pc(1);
            let byte_temp: u8 = memory.read_byte(data.$r() + (sign_extend(offset) as u16));
            $op(data, byte_temp)
        }
    };
}

macro_rules! fn_instr_dd_op_a_i_reg_p_dd {
    ($fn:tt, $op:ident) => {
        fn_instr_op_a_i_reg_p_dd!($fn, ix, $op);
    };
}

macro_rules! fn_instr_dd_op_a_i_reg_p_dd_d {
    ($fn:tt, $op:ident) => {
        fn_instr_op_a_i_reg_p_dd_d!($fn, ix, $op);
    };
}

macro_rules! fn_instr_fd_op_a_i_reg_p_dd {
    ($fn:tt, $op:ident) => {
        fn_instr_op_a_i_reg_p_dd!($fn, iy, $op);
    };
}

macro_rules! fn_instr_fd_op_a_i_reg_p_dd_d {
    ($fn:tt, $op:ident) => {
        fn_instr_op_a_i_reg_p_dd_d!($fn, iy, $op);
    };
}

macro_rules! fn_instr_op_i_reg_p_dd {
    ($fn:tt, $ri:ident, $op:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let address = data.pc();
            let offset: u8 = memory.read_byte(address);
            let _address = data.pc();
            memory.contend_read_no_mreq_loop(_address, 1, 5);
            data.inc_pc(1);
            let word_temp: u16 = data.$ri() + sign_extend(offset) as u16;
            let mut byte_temp: u8 = memory.read_byte(word_temp);
            memory.contend_read_no_mreq(word_temp, 1);
            $op(data, &mut byte_temp);
            memory.write_byte(word_temp, byte_temp)
        }
    };
}

macro_rules! fn_instr_dd_op_i_reg_p_dd {
    ($fn:tt, $op:ident) => {
        fn_instr_op_i_reg_p_dd!($fn, ix, $op);
    };
}

macro_rules! fn_instr_fd_op_i_reg_p_dd {
    ($fn:tt, $op:ident) => {
        fn_instr_op_i_reg_p_dd!($fn, iy, $op);
    };
}

macro_rules! fn_instr_ld_r_i_reg_p_dd {
    ($fn:tt, $r:ident, $ri:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let address = data.pc();
            let offset: u8 = memory.read_byte(address);
            let _address = data.pc();
            memory.contend_read_no_mreq_loop(_address, 1, 5);
            data.inc_pc(1);
            data.$r = memory.read_byte(data.$ri() + (sign_extend(offset) as u16));
        }
    };
}

macro_rules! fn_instr_dd_ld_r_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ld_r_i_reg_p_dd!($fn, $r, ix);
    };
}

macro_rules! fn_instr_fd_ld_r_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ld_r_i_reg_p_dd!($fn, $r, iy);
    };
}

macro_rules! fn_instr_ddcb_op_i_reg_p_dd {
    ($fn:tt, $op:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let mut byte_temp: u8 = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            byte_temp = $op(data, byte_temp);
            memory.write_byte(data.temp_addr, byte_temp);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_rlc_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            data.$r = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            data.$r = rlc(data, data.$r);
            memory.write_byte(data.temp_addr, data.$r);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_rrc_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            data.$r = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            data.$r = rrc(data, data.$r);
            memory.write_byte(data.temp_addr, data.$r);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_rl_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            data.$r = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            data.$r = rl(data, data.$r);
            memory.write_byte(data.temp_addr, data.$r);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_rr_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            data.$r = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            data.$r = rr(data, data.$r);
            memory.write_byte(data.temp_addr, data.$r);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_sla_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            data.$r = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            data.$r = sla(data, data.$r);
            memory.write_byte(data.temp_addr, data.$r);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_sra_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            data.$r = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            data.$r = sra(data, data.$r);
            memory.write_byte(data.temp_addr, data.$r);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_sll_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            data.$r = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            data.$r = sll(data, data.$r);
            memory.write_byte(data.temp_addr, data.$r);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_srl_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            data.$r = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            data.$r = srl(data, data.$r);
            memory.write_byte(data.temp_addr, data.$r);
        }
    };
}

macro_rules! fn_instr_ddcb_bit_n_i_reg_p_dd {
    ($fn:tt, $r:expr) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let byte_temp = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            biti(data, $r, byte_temp, data.temp_addr);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_res_n_i_reg_p_dd {
    ($fn:tt, $r:ident, $mask:expr) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            data.$r = memory.read_byte(data.temp_addr) & $mask;
            memory.contend_read_no_mreq(data.temp_addr, 1);
            memory.write_byte(data.temp_addr, data.$r);
        }
    };
}

macro_rules! fn_instr_ddcb_res_n_i_reg_p_dd {
    ($fn:tt, $mask:expr) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let byte_temp: u8 = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            memory.write_byte(data.temp_addr, byte_temp & $mask);
        }
    };
}

macro_rules! fn_instr_ddcb_set_n_i_reg_p_dd {
    ($fn:tt, $mask:expr) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            let byte_temp: u8 = memory.read_byte(data.temp_addr);
            memory.contend_read_no_mreq(data.temp_addr, 1);
            memory.write_byte(data.temp_addr, byte_temp | $mask);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_res_0_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_res_n_i_reg_p_dd!($fn, $r, 0xfe);
    };
}

macro_rules! fn_instr_ddcb_ld_r_res_1_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_res_n_i_reg_p_dd!($fn, $r, 0xfd);
    };
}

macro_rules! fn_instr_ddcb_ld_r_res_2_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_res_n_i_reg_p_dd!($fn, $r, 0xfb);
    };
}

macro_rules! fn_instr_ddcb_ld_r_res_3_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_res_n_i_reg_p_dd!($fn, $r, 0xf7);
    };
}

macro_rules! fn_instr_ddcb_ld_r_res_4_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_res_n_i_reg_p_dd!($fn, $r, 0xef);
    };
}

macro_rules! fn_instr_ddcb_ld_r_res_5_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_res_n_i_reg_p_dd!($fn, $r, 0xdf);
    };
}

macro_rules! fn_instr_ddcb_ld_r_res_6_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_res_n_i_reg_p_dd!($fn, $r, 0xbf);
    };
}

macro_rules! fn_instr_ddcb_ld_r_res_7_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_res_n_i_reg_p_dd!($fn, $r, 0x7f);
    };
}

macro_rules! fn_instr_ddcb_ld_r_set_n_i_reg_p_dd {
    ($fn:tt, $r:ident, $mask:expr) => {
        pub fn $fn(data: &mut Z80Data, memory: &mut Memory) {
            data.$r = memory.read_byte(data.temp_addr) | $mask;
            memory.contend_read_no_mreq(data.temp_addr, 1);
            memory.write_byte(data.temp_addr, data.$r);
        }
    };
}

macro_rules! fn_instr_ddcb_ld_r_set_0_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_set_n_i_reg_p_dd!($fn, $r, 0x01);
    };
}

macro_rules! fn_instr_ddcb_ld_r_set_1_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_set_n_i_reg_p_dd!($fn, $r, 0x02);
    };
}

macro_rules! fn_instr_ddcb_ld_r_set_2_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_set_n_i_reg_p_dd!($fn, $r, 0x04);
    };
}

macro_rules! fn_instr_ddcb_ld_r_set_3_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_set_n_i_reg_p_dd!($fn, $r, 0x08);
    };
}

macro_rules! fn_instr_ddcb_ld_r_set_4_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_set_n_i_reg_p_dd!($fn, $r, 0x10);
    };
}

macro_rules! fn_instr_ddcb_ld_r_set_5_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_set_n_i_reg_p_dd!($fn, $r, 0x20);
    };
}

macro_rules! fn_instr_ddcb_ld_r_set_6_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_set_n_i_reg_p_dd!($fn, $r, 0x40);
    };
}

macro_rules! fn_instr_ddcb_ld_r_set_7_i_reg_p_dd {
    ($fn:tt, $r:ident) => {
        fn_instr_ddcb_ld_r_set_n_i_reg_p_dd!($fn, $r, 0x80);
    };
}

// #[allow(non_snake_case)]
pub fn execute_opcode(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
    opcode: u16,
) -> bool {
    match opcode {
        0 => {
            /* NOP */
            instr__NOP();
            true
        }
        1 => {
            /* LD BC,nnnn */
            instr__LD_BC_NNNN(data, memory);
            true
        }
        0x02 => {
            /* LD (BC),A */
            instr__LD_iBC_A(data, memory);
            true
        }

        0x03 => {
            /* INC BC */
            instr__INC_BC(data, memory);
            true
        }

        0x04 => {
            /* INC B */
            instr__INC_B(data);
            true
        }

        0x05 => {
            /* DEC B */
            instr__DEC_B(data);
            true
        }

        0x06 => {
            /* LD B,nn */
            instr__LD_B_NN(data, memory);
            true
        }

        0x07 => {
            /* RLCA */
            instr__RLCA(data);
            true
        }

        0x08 => {
            /* EX AF,AF' */
            instr__EX_AF_AF(data);
            true
        }

        0x09 => {
            /* ADD HL,BC */
            instr__ADD_HL_BC(data, memory);
            true
        }

        0x0a => {
            /* LD A,(BC) */
            instr__LD_A_iBC(data, memory);
            true
        }

        0x0b => {
            /* DEC BC */
            instr__DEC_BC(data, memory);
            true
        }

        0x0c => {
            /* INC C */
            instr__INC_C(data);
            true
        }

        0x0d => {
            /* DEC C */
            instr__DEC_C(data);
            true
        }

        0x0e => {
            /* LD C,nn */
            instr__LD_C_NN(data, memory);
            true
        }

        0x0f => {
            /* RRCA */
            instr__RRCA(data);
            true
        }

        0x10 => {
            /* DJNZ offset */
            instr__DJNZ_OFFSET(data, memory);
            true
        }

        0x11 => {
            /* LD DE,nnnn */
            instr__LD_DE_NNNN(data, memory);
            true
        }

        0x12 => {
            /* LD (DE),A */
            instr__LD_iDE_A(data, memory);
            true
        }

        0x13 => {
            /* INC DE */
            instr__INC_DE(data, memory);
            true
        }

        0x14 => {
            /* INC D */
            instr__INC_D(data);
            true
        }

        0x15 => {
            /* DEC D */
            instr__DEC_D(data);
            true
        }

        0x16 => {
            /* LD D,nn */
            instr__LD_D_NN(data, memory);
            true
        }

        0x17 => {
            /* RLA */
            instr__RLA(data);
            true
        }

        0x18 => {
            /* JR offset */
            instr__JR_OFFSET(data, memory);
            true
        }

        0x19 => {
            /* ADD HL,DE */
            instr__ADD_HL_DE(data, memory);
            true
        }

        0x1a => {
            /* LD A,(DE) */
            instr__LD_A_iDE(data, memory);
            true
        }

        0x1b => {
            /* DEC DE */
            instr__DEC_DE(data, memory);
            true
        }

        0x1c => {
            /* INC E */
            instr__INC_E(data);
            true
        }

        0x1d => {
            /* DEC E */
            instr__DEC_E(data);
            true
        }

        0x1e => {
            /* LD E,nn */
            instr__LD_E_NN(data, memory);
            true
        }

        0x1f => {
            /* RRA */
            instr__RRA(data);
            true
        }

        0x20 => {
            /* JR NZ,offset */
            instr__JR_NZ_OFFSET(data, memory);
            true
        }

        0x21 => {
            /* LD HL,nnnn */
            instr__LD_HL_NNNN(data, memory);
            true
        }

        0x22 => {
            /* LD (nnnn),HL */
            instr__LD_iNNNN_HL(data, memory);
            true
        }

        0x23 => {
            /* INC HL */
            instr__INC_HL(data, memory);
            true
        }

        0x24 => {
            /* INC H */
            instr__INC_H(data);
            true
        }

        0x25 => {
            /* DEC H */
            instr__DEC_H(data);
            true
        }

        0x26 => {
            /* LD H,nn */
            instr__LD_H_NN(data, memory);
            true
        }

        0x27 => {
            /* DAA */
            instr__DAA(data);
            true
        }

        0x28 => {
            /* JR Z,offset */
            instr__JR_Z_OFFSET(data, memory);
            true
        }

        0x29 => {
            /* ADD HL,HL */
            instr__ADD_HL_HL(data, memory);
            true
        }

        0x2a => {
            /* LD HL,(nnnn) */
            instr__LD_HL_iNNNN(data, memory);
            true
        }

        0x2b => {
            /* DEC HL */
            instr__DEC_HL(data, memory);
            true
        }

        0x2c => {
            /* INC L */
            instr__INC_L(data);
            true
        }

        0x2d => {
            /* DEC L */
            instr__DEC_L(data);
            true
        }

        0x2e => {
            /* LD L,nn */
            instr__LD_L_NN(data, memory);
            true
        }

        0x2f => {
            /* CPL */
            instr__CPL(data);
            true
        }

        0x30 => {
            /* JR NC,offset */
            instr__JR_NC_OFFSET(data, memory);
            true
        }

        0x31 => {
            /* LD SP,nnnn */
            instr__LD_SP_NNNN(data, memory);
            true
        }

        0x32 => {
            /* LD (nnnn),A */
            instr__LD_iNNNN_A(data, memory);
            true
        }

        0x33 => {
            /* INC SP */
            instr__INC_SP(data, memory);
            true
        }

        0x34 => {
            /* INC (HL) */
            instr__INC_iHL(data, memory);
            true
        }

        0x35 => {
            /* DEC (HL) */
            instr__DEC_iHL(data, memory);
            true
        }

        0x36 => {
            /* LD (HL),nn */
            instr__LD_iHL_NN(data, memory);
            true
        }

        0x37 => {
            /* SCF */
            instr__SCF(data);
            true
        }

        0x38 => {
            /* JR C,offset */
            instr__JR_C_OFFSET(data, memory);
            true
        }

        0x39 => {
            /* ADD HL,SP */
            instr__ADD_HL_SP(data, memory);
            true
        }

        0x3a => {
            /* LD A,(nnnn) */
            instr__LD_A_iNNNN(data, memory);
            true
        }

        0x3b => {
            /* DEC SP */
            instr__DEC_SP(data, memory);
            true
        }

        0x3c => {
            /* INC A */
            instr__INC_A(data);
            true
        }

        0x3d => {
            /* DEC A */
            instr__DEC_A(data);
            true
        }

        0x3e => {
            /* LD A,nn */
            instr__LD_A_NN(data, memory);
            true
        }

        0x3f => {
            /* CCF */
            instr__CCF(data);
            true
        }

        0x40 => {
            /* LD B,B */
            instr__LD_B_B();
            true
        }

        0x41 => {
            /* LD B,C */
            instr__LD_B_C(data);
            true
        }

        0x42 => {
            /* LD B,D */
            instr__LD_B_D(data);
            true
        }

        0x43 => {
            /* LD B,E */
            instr__LD_B_E(data);
            true
        }

        0x44 => {
            /* LD B,H */
            instr__LD_B_H(data);
            true
        }

        0x45 => {
            /* LD B,L */
            instr__LD_B_L(data);
            true
        }

        0x46 => {
            /* LD B,(HL) */
            instr__LD_B_iHL(data, memory);
            true
        }

        0x47 => {
            /* LD B,A */
            instr__LD_B_A(data);
            true
        }

        0x48 => {
            /* LD C,B */
            instr__LD_C_B(data);
            true
        }

        0x49 => {
            /* LD C,C */
            instr__LD_C_C();
            true
        }

        0x4a => {
            /* LD C,D */
            instr__LD_C_D(data);
            true
        }

        0x4b => {
            /* LD C,E */
            instr__LD_C_E(data);
            true
        }

        0x4c => {
            /* LD C,H */
            instr__LD_C_H(data);
            true
        }

        0x4d => {
            /* LD C,L */
            instr__LD_C_L(data);
            true
        }

        0x4e => {
            /* LD C,(HL) */
            instr__LD_C_iHL(data, memory);
            true
        }

        0x4f => {
            /* LD C,A */
            instr__LD_C_A(data);
            true
        }

        0x50 => {
            /* LD D,B */
            instr__LD_D_B(data);
            true
        }

        0x51 => {
            /* LD D,C */
            instr__LD_D_C(data);
            true
        }

        0x52 => {
            /* LD D,D */
            instr__LD_D_D();
            true
        }

        0x53 => {
            /* LD D,E */
            instr__LD_D_E(data);
            true
        }

        0x54 => {
            /* LD D,H */
            instr__LD_D_H(data);
            true
        }

        0x55 => {
            /* LD D,L */
            instr__LD_D_L(data);
            true
        }

        0x56 => {
            /* LD D,(HL) */
            instr__LD_D_iHL(data, memory);
            true
        }

        0x57 => {
            /* LD D,A */
            instr__LD_D_A(data);
            true
        }

        0x58 => {
            /* LD E,B */
            instr__LD_E_B(data);
            true
        }

        0x59 => {
            /* LD E,C */
            instr__LD_E_C(data);
            true
        }

        0x5a => {
            /* LD E,D */
            instr__LD_E_D(data);
            true
        }

        0x5b => {
            /* LD E,E */
            instr__LD_E_E();
            true
        }

        0x5c => {
            /* LD E,H */
            instr__LD_E_H(data);
            true
        }

        0x5d => {
            /* LD E,L */
            instr__LD_E_L(data);
            true
        }

        0x5e => {
            /* LD E,(HL) */
            instr__LD_E_iHL(data, memory);
            true
        }

        0x5f => {
            /* LD E,A */
            instr__LD_E_A(data);
            true
        }

        0x60 => {
            /* LD H,B */
            instr__LD_H_B(data);
            true
        }

        0x61 => {
            /* LD H,C */
            instr__LD_H_C(data);
            true
        }

        0x62 => {
            /* LD H,D */
            instr__LD_H_D(data);
            true
        }

        0x63 => {
            /* LD H,E */
            instr__LD_H_E(data);
            true
        }

        0x64 => {
            /* LD H,H */
            instr__LD_H_H();
            true
        }

        0x65 => {
            /* LD H,L */
            instr__LD_H_L(data);
            true
        }

        0x66 => {
            /* LD H,(HL) */
            instr__LD_H_iHL(data, memory);
            true
        }

        0x67 => {
            /* LD H,A */
            instr__LD_H_A(data);
            true
        }

        0x68 => {
            /* LD L,B */
            instr__LD_L_B(data);
            true
        }

        0x69 => {
            /* LD L,C */
            instr__LD_L_C(data);
            true
        }

        0x6a => {
            /* LD L,D */
            instr__LD_L_D(data);
            true
        }

        0x6b => {
            /* LD L,E */
            instr__LD_L_E(data);
            true
        }

        0x6c => {
            /* LD L,H */
            instr__LD_L_H(data);
            true
        }

        0x6d => {
            /* LD L,L */
            instr__LD_L_L();
            true
        }

        0x6e => {
            /* LD L,(HL) */
            instr__LD_L_iHL(data, memory);
            true
        }

        0x6f => {
            /* LD L,A */
            instr__LD_L_A(data);
            true
        }

        0x70 => {
            /* LD (HL),B */
            instr__LD_iHL_B(data, memory);
            true
        }

        0x71 => {
            /* LD (HL),C */
            instr__LD_iHL_C(data, memory);
            true
        }

        0x72 => {
            /* LD (HL),D */
            instr__LD_iHL_D(data, memory);
            true
        }

        0x73 => {
            /* LD (HL),E */
            instr__LD_iHL_E(data, memory);
            true
        }

        0x74 => {
            /* LD (HL),H */
            instr__LD_iHL_H(data, memory);
            true
        }

        0x75 => {
            /* LD (HL),L */
            instr__LD_iHL_L(data, memory);
            true
        }

        0x76 => {
            /* HALT */
            instr__HALT(data);
            true
        }

        0x77 => {
            /* LD (HL),A */
            instr__LD_iHL_A(data, memory);
            true
        }

        0x78 => {
            /* LD A,B */
            instr__LD_A_B(data);
            true
        }

        0x79 => {
            /* LD A,C */
            instr__LD_A_C(data);
            true
        }

        0x7a => {
            /* LD A,D */
            instr__LD_A_D(data);
            true
        }

        0x7b => {
            /* LD A,E */
            instr__LD_A_E(data);
            true
        }

        0x7c => {
            /* LD A,H */
            instr__LD_A_H(data);
            true
        }

        0x7d => {
            /* LD A,L */
            instr__LD_A_L(data);
            true
        }

        0x7e => {
            /* LD A,(HL) */
            instr__LD_A_iHL(data, memory);
            true
        }

        0x7f => {
            /* LD A,A */
            instr__LD_A_A();
            true
        }

        0x80 => {
            /* ADD A,B */
            instr__ADD_A_B(data);
            true
        }

        0x81 => {
            /* ADD A,C */
            instr__ADD_A_C(data);
            true
        }

        0x82 => {
            /* ADD A,D */
            instr__ADD_A_D(data);
            true
        }

        0x83 => {
            /* ADD A,E */
            instr__ADD_A_E(data);
            true
        }

        0x84 => {
            /* ADD A,H */
            instr__ADD_A_H(data);
            true
        }

        0x85 => {
            /* ADD A,L */
            instr__ADD_A_L(data);
            true
        }

        0x86 => {
            /* ADD A,(HL) */
            instr__ADD_A_iHL(data, memory);
            true
        }

        0x87 => {
            /* ADD A,A */
            instr__ADD_A_A(data);
            true
        }

        0x88 => {
            /* ADC A,B */
            instr__ADC_A_B(data);
            true
        }

        0x89 => {
            /* ADC A,C */
            instr__ADC_A_C(data);
            true
        }

        0x8a => {
            /* ADC A,D */
            instr__ADC_A_D(data);
            true
        }

        0x8b => {
            /* ADC A,E */
            instr__ADC_A_E(data);
            true
        }

        0x8c => {
            /* ADC A,H */
            instr__ADC_A_H(data);
            true
        }

        0x8d => {
            /* ADC A,L */
            instr__ADC_A_L(data);
            true
        }

        0x8e => {
            /* ADC A,(HL) */
            instr__ADC_A_iHL(data, memory);
            true
        }

        0x8f => {
            /* ADC A,A */
            instr__ADC_A_A(data);
            true
        }

        0x90 => {
            /* SUB A,B */
            instr__SUB_A_B(data);
            true
        }

        0x91 => {
            /* SUB A,C */
            instr__SUB_A_C(data);
            true
        }

        0x92 => {
            /* SUB A,D */
            instr__SUB_A_D(data);
            true
        }

        0x93 => {
            /* SUB A,E */
            instr__SUB_A_E(data);
            true
        }

        0x94 => {
            /* SUB A,H */
            instr__SUB_A_H(data);
            true
        }

        0x95 => {
            /* SUB A,L */
            instr__SUB_A_L(data);
            true
        }

        0x96 => {
            /* SUB A,(HL) */
            instr__SUB_A_iHL(data, memory);
            true
        }

        0x97 => {
            /* SUB A,A */
            instr__SUB_A_A(data);
            true
        }

        0x98 => {
            /* SBC A,B */
            instr__SBC_A_B(data);
            true
        }

        0x99 => {
            /* SBC A,C */
            instr__SBC_A_C(data);
            true
        }

        0x9a => {
            /* SBC A,D */
            instr__SBC_A_D(data);
            true
        }

        0x9b => {
            /* SBC A,E */
            instr__SBC_A_E(data);
            true
        }

        0x9c => {
            /* SBC A,H */
            instr__SBC_A_H(data);
            true
        }

        0x9d => {
            /* SBC A,L */
            instr__SBC_A_L(data);
            true
        }

        0x9e => {
            /* SBC A,(HL) */
            instr__SBC_A_iHL(data, memory);
            true
        }

        0x9f => {
            /* SBC A,A */
            instr__SBC_A_A(data);
            true
        }

        0xa0 => {
            /* AND A,B */
            instr__AND_A_B(data);
            true
        }

        0xa1 => {
            /* AND A,C */
            instr__AND_A_C(data);
            true
        }

        0xa2 => {
            /* AND A,D */
            instr__AND_A_D(data);
            true
        }

        0xa3 => {
            /* AND A,E */
            instr__AND_A_E(data);
            true
        }

        0xa4 => {
            /* AND A,H */
            instr__AND_A_H(data);
            true
        }

        0xa5 => {
            /* AND A,L */
            instr__AND_A_L(data);
            true
        }

        0xa6 => {
            /* AND A,(HL) */
            instr__AND_A_iHL(data, memory);
            true
        }

        0xa7 => {
            /* AND A,A */
            instr__AND_A_A(data);
            true
        }

        0xa8 => {
            /* XOR A,B */
            instr__XOR_A_B(data);
            true
        }

        0xa9 => {
            /* XOR A,C */
            instr__XOR_A_C(data);
            true
        }

        0xaa => {
            /* XOR A,D */
            instr__XOR_A_D(data);
            true
        }

        0xab => {
            /* XOR A,E */
            instr__XOR_A_E(data);
            true
        }

        0xac => {
            /* XOR A,H */
            instr__XOR_A_H(data);
            true
        }

        0xad => {
            /* XOR A,L */
            instr__XOR_A_L(data);
            true
        }

        0xae => {
            /* XOR A,(HL) */
            instr__XOR_A_iHL(data, memory);
            true
        }

        0xaf => {
            /* XOR A,A */
            instr__XOR_A_A(data);
            true
        }

        0xb0 => {
            /* OR A,B */
            instr__OR_A_B(data);
            true
        }

        0xb1 => {
            /* OR A,C */
            instr__OR_A_C(data);
            true
        }

        0xb2 => {
            /* OR A,D */
            instr__OR_A_D(data);
            true
        }

        0xb3 => {
            /* OR A,E */
            instr__OR_A_E(data);
            true
        }

        0xb4 => {
            /* OR A,H */
            instr__OR_A_H(data);
            true
        }

        0xb5 => {
            /* OR A,L */
            instr__OR_A_L(data);
            true
        }

        0xb6 => {
            /* OR A,(HL) */
            instr__OR_A_iHL(data, memory);
            true
        }

        0xb7 => {
            /* OR A,A */
            instr__OR_A_A(data);
            true
        }

        0xb8 => {
            /* CP B */
            instr__CP_B(data);
            true
        }

        0xb9 => {
            /* CP C */
            instr__CP_C(data);
            true
        }

        0xba => {
            /* CP D */
            instr__CP_D(data);
            true
        }

        0xbb => {
            /* CP E */
            instr__CP_E(data);
            true
        }

        0xbc => {
            /* CP H */
            instr__CP_H(data);
            true
        }

        0xbd => {
            /* CP L */
            instr__CP_L(data);
            true
        }

        0xbe => {
            /* CP (HL) */
            instr__CP_iHL(data, memory);
            true
        }

        0xbf => {
            /* CP A */
            instr__CP_A(data);
            true
        }

        0xc0 => {
            /* RET NZ */
            instr__RET_NZ(data, memory, hook);
            true
        }

        0xc1 => {
            /* POP BC */
            instr__POP_BC(data, memory);
            true
        }

        0xc2 => {
            /* JP NZ,nnnn */
            instr__JP_NZ_NNNN(data, memory);
            true
        }

        0xc3 => {
            /* JP nnnn */
            instr__JP_NNNN(data, memory);
            true
        }

        0xc4 => {
            /* CALL NZ,nnnn */
            instr__CALL_NZ_NNNN(data, memory, ports, hook);
            true
        }

        0xc5 => {
            /* PUSH BC */
            instr__PUSH_BC(data, memory);
            true
        }

        0xc6 => {
            /* ADD A,nn */
            instr__ADD_A_NN(data, memory);
            true
        }

        0xc7 => {
            /* RST 00 */
            instr__RST_00(data, memory);
            true
        }

        0xc8 => {
            /* RET Z */
            instr__RET_Z(data, memory, hook);
            true
        }

        0xc9 => {
            /* RET */
            instr__RET(data, memory, hook);
            true
        }

        0xca => {
            /* JP Z,nnnn */
            instr__JP_Z_NNNN(data, memory);
            true
        }

        0xcb => {
            /* shift CB */
            instr__SHIFT_CB(data, memory);
            true
        }

        0xcc => {
            /* CALL Z,nnnn */
            instr__CALL_Z_NNNN(data, memory, ports, hook);
            true
        }

        0xcd => {
            /* CALL nnnn */
            instr__CALL_NNNN(data, memory, ports, hook);
            true
        }

        0xce => {
            /* ADC A,nn */
            instr__ADC_A_NN(data, memory);
            true
        }

        0xcf => {
            /* RST 8 */
            instr__RST_8(data, memory);
            true
        }

        0xd0 => {
            /* RET NC */
            instr__RET_NC(data, memory, hook);
            true
        }

        0xd1 => {
            /* POP DE */
            instr__POP_DE(data, memory);
            true
        }

        0xd2 => {
            /* JP NC,nnnn */
            instr__JP_NC_NNNN(data, memory);
            true
        }

        0xd3 => {
            /* OUT (nn),A */
            instr__OUT_iNN_A(data, memory, ports);
            true
        }

        0xd4 => {
            /* CALL NC,nnnn */
            instr__CALL_NC_NNNN(data, memory, ports, hook);
            true
        }

        0xd5 => {
            /* PUSH DE */
            instr__PUSH_DE(data, memory);
            true
        }

        0xd6 => {
            /* SUB nn */
            instr__SUB_NN(data, memory);
            true
        }

        0xd7 => {
            /* RST 10 */
            instr__RST_10(data, memory);
            true
        }

        0xd8 => {
            /* RET C */
            instr__RET_C(data, memory, hook);
            true
        }

        0xd9 => {
            /* EXX */
            instr__EXX(data);
            true
        }

        0xda => {
            /* JP C,nnnn */
            instr__JP_C_NNNN(data, memory);
            true
        }

        0xdb => {
            /* IN A,(nn) */
            instr__IN_A_iNN(data, memory, ports);
            true
        }

        0xdc => {
            /* CALL C,nnnn */
            instr__CALL_C_NNNN(data, memory, ports, hook);
            true
        }

        0xdd => {
            /* shift DD */
            instr__SHIFT_DD(data, memory);
            true
        }

        0xde => {
            /* SBC A,nn */
            instr__SBC_A_NN(data, memory);
            true
        }

        0xdf => {
            /* RST 18 */
            instr__RST_18(data, memory);
            true
        }

        0xe0 => {
            /* RET PO */
            instr__RET_PO(data, memory, hook);
            true
        }

        0xe1 => {
            /* POP HL */
            instr__POP_HL(data, memory);
            true
        }

        0xe2 => {
            /* JP PO,nnnn */
            instr__JP_PO_NNNN(data, memory);
            true
        }

        0xe3 => {
            /* EX (SP),HL */
            instr__EX_iSP_HL(data, memory);
            true
        }

        0xe4 => {
            /* CALL PO,nnnn */
            instr__CALL_PO_NNNN(data, memory, ports, hook);
            true
        }

        0xe5 => {
            /* PUSH HL */
            instr__PUSH_HL(data, memory);
            true
        }

        0xe6 => {
            /* AND nn */
            instr__AND_NN(data, memory);
            true
        }

        0xe7 => {
            /* RST 20 */
            instr__RST_20(data, memory);
            true
        }

        0xe8 => {
            /* RET PE */
            instr__RET_PE(data, memory, hook);
            true
        }

        0xe9 => {
            /* JP HL */
            instr__JP_HL(data, memory, ports, hook);
            true
        }

        0xea => {
            /* JP PE,nnnn */
            instr__JP_PE_NNNN(data, memory);
            true
        }

        0xeb => {
            /* EX DE,HL */
            instr__EX_DE_HL(data);
            true
        }

        0xec => {
            /* CALL PE,nnnn */
            instr__CALL_PE_NNNN(data, memory, ports, hook);
            true
        }

        0xed => {
            /* shift ED */
            instr__SHIFT_ED(data, memory);
            true
        }

        0xee => {
            /* XOR A,nn */
            instr__XOR_A_NN(data, memory);
            true
        }

        0xef => {
            /* RST 28 */
            instr__RST_28(data, memory);
            true
        }

        0xf0 => {
            /* RET P */
            instr__RET_P(data, memory, hook);
            true
        }

        0xf1 => {
            /* POP AF */
            instr__POP_AF(data, memory);
            true
        }

        0xf2 => {
            /* JP P,nnnn */
            instr__JP_P_NNNN(data, memory);
            true
        }

        0xf3 => {
            /* DI */
            instr__DI(data);
            true
        }

        0xf4 => {
            /* CALL P,nnnn */
            instr__CALL_P_NNNN(data, memory, ports, hook);
            true
        }

        0xf5 => {
            /* PUSH AF */
            instr__PUSH_AF(data, memory);
            true
        }

        0xf6 => {
            /* OR nn */
            instr__OR_NN(data, memory);
            true
        }

        0xf7 => {
            /* RST 30 */
            instr__RST_30(data, memory);
            true
        }

        0xf8 => {
            /* RET M */
            instr__RET_M(data, memory, hook);
            true
        }

        0xf9 => {
            /* LD SP,HL */
            instr__LD_SP_HL(data, memory);
            true
        }

        0xfa => {
            /* JP M,nnnn */
            instr__JP_M_NNNN(data, memory);
            true
        }

        0xfb => {
            /* EI */
            instr__EI(data);
            true
        }

        0xfc => {
            /* CALL M,nnnn */
            instr__CALL_M_NNNN(data, memory, ports, hook);
            true
        }

        0xfd => {
            /* shift FD */
            instr__SHIFT_FD(data, memory);
            true
        }

        0xfe => {
            /* CP nn */
            instr__CP_NN(data, memory);
            true
        }

        0xff => {
            /* RST 38 */
            instr__RST_38(data, memory);
            true
        }

        val if val == SHIFT_0X_CB => {
            /* RLC B */
            instrCB__RLC_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x01 => {
            /* RLC C */
            instrCB__RLC_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x02 => {
            /* RLC D */
            instrCB__RLC_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x03 => {
            /* RLC E */
            instrCB__RLC_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x04 => {
            /* RLC H */
            instrCB__RLC_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x05 => {
            /* RLC L */
            instrCB__RLC_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x06 => {
            /* RLC (HL) */
            instrCB__RLC_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x07 => {
            /* RLC A */
            instrCB__RLC_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x08 => {
            /* RRC B */
            instrCB__RRC_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x09 => {
            /* RRC C */
            instrCB__RRC_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x0a => {
            /* RRC D */
            instrCB__RRC_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x0b => {
            /* RRC E */
            instrCB__RRC_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x0c => {
            /* RRC H */
            instrCB__RRC_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x0d => {
            /* RRC L */
            instrCB__RRC_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x0e => {
            /* RRC (HL) */
            instrCB__RRC_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x0f => {
            /* RRC A */
            instrCB__RRC_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x10 => {
            /* RL B */
            instrCB__RL_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x11 => {
            /* RL C */
            instrCB__RL_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x12 => {
            /* RL D */
            instrCB__RL_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x13 => {
            /* RL E */
            instrCB__RL_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x14 => {
            /* RL H */
            instrCB__RL_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x15 => {
            /* RL L */
            instrCB__RL_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x16 => {
            /* RL (HL) */
            instrCB__RL_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x17 => {
            /* RL A */
            instrCB__RL_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x18 => {
            /* RR B */
            instrCB__RR_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x19 => {
            /* RR C */
            instrCB__RR_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x1a => {
            /* RR D */
            instrCB__RR_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x1b => {
            /* RR E */
            instrCB__RR_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x1c => {
            /* RR H */
            instrCB__RR_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x1d => {
            /* RR L */
            instrCB__RR_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x1e => {
            /* RR (HL) */
            instrCB__RR_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x1f => {
            /* RR A */
            instrCB__RR_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x20 => {
            /* SLA B */
            instrCB__SLA_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x21 => {
            /* SLA C */
            instrCB__SLA_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x22 => {
            /* SLA D */
            instrCB__SLA_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x23 => {
            /* SLA E */
            instrCB__SLA_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x24 => {
            /* SLA H */
            instrCB__SLA_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x25 => {
            /* SLA L */
            instrCB__SLA_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x26 => {
            /* SLA (HL) */
            instrCB__SLA_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x27 => {
            /* SLA A */
            instrCB__SLA_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x28 => {
            /* SRA B */
            instrCB__SRA_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x29 => {
            /* SRA C */
            instrCB__SRA_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x2a => {
            /* SRA D */
            instrCB__SRA_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x2b => {
            /* SRA E */
            instrCB__SRA_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x2c => {
            /* SRA H */
            instrCB__SRA_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x2d => {
            /* SRA L */
            instrCB__SRA_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x2e => {
            /* SRA (HL) */
            instrCB__SRA_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x2f => {
            /* SRA A */
            instrCB__SRA_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x30 => {
            /* SLL B */
            instrCB__SLL_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x31 => {
            /* SLL C */
            instrCB__SLL_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x32 => {
            /* SLL D */
            instrCB__SLL_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x33 => {
            /* SLL E */
            instrCB__SLL_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x34 => {
            /* SLL H */
            instrCB__SLL_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x35 => {
            /* SLL L */
            instrCB__SLL_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x36 => {
            /* SLL (HL) */
            instrCB__SLL_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x37 => {
            /* SLL A */
            instrCB__SLL_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x38 => {
            /* SRL B */
            instrCB__SRL_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x39 => {
            /* SRL C */
            instrCB__SRL_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x3a => {
            /* SRL D */
            instrCB__SRL_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x3b => {
            /* SRL E */
            instrCB__SRL_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x3c => {
            /* SRL H */
            instrCB__SRL_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x3d => {
            /* SRL L */
            instrCB__SRL_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x3e => {
            /* SRL (HL) */
            instrCB__SRL_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x3f => {
            /* SRL A */
            instrCB__SRL_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x40 => {
            /* BIT 0,B */
            instrCB__BIT_0_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x41 => {
            /* BIT 0,C */
            instrCB__BIT_0_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x42 => {
            /* BIT 0,D */
            instrCB__BIT_0_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x43 => {
            /* BIT 0,E */
            instrCB__BIT_0_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x44 => {
            /* BIT 0,H */
            instrCB__BIT_0_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x45 => {
            /* BIT 0,L */
            instrCB__BIT_0_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x46 => {
            /* BIT 0,(HL) */
            instrCB__BIT_0_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x47 => {
            /* BIT 0,A */
            instrCB__BIT_0_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x48 => {
            /* BIT 1,B */
            instrCB__BIT_1_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x49 => {
            /* BIT 1,C */
            instrCB__BIT_1_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x4a => {
            /* BIT 1,D */
            instrCB__BIT_1_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x4b => {
            /* BIT 1,E */
            instrCB__BIT_1_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x4c => {
            /* BIT 1,H */
            instrCB__BIT_1_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x4d => {
            /* BIT 1,L */
            instrCB__BIT_1_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x4e => {
            /* BIT 1,(HL) */
            instrCB__BIT_1_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x4f => {
            /* BIT 1,A */
            instrCB__BIT_1_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x50 => {
            /* BIT 2,B */
            instrCB__BIT_2_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x51 => {
            /* BIT 2,C */
            instrCB__BIT_2_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x52 => {
            /* BIT 2,D */
            instrCB__BIT_2_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x53 => {
            /* BIT 2,E */
            instrCB__BIT_2_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x54 => {
            /* BIT 2,H */
            instrCB__BIT_2_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x55 => {
            /* BIT 2,L */
            instrCB__BIT_2_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x56 => {
            /* BIT 2,(HL) */
            instrCB__BIT_2_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x57 => {
            /* BIT 2,A */
            instrCB__BIT_2_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x58 => {
            /* BIT 3,B */
            instrCB__BIT_3_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x59 => {
            /* BIT 3,C */
            instrCB__BIT_3_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x5a => {
            /* BIT 3,D */
            instrCB__BIT_3_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x5b => {
            /* BIT 3,E */
            instrCB__BIT_3_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x5c => {
            /* BIT 3,H */
            instrCB__BIT_3_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x5d => {
            /* BIT 3,L */
            instrCB__BIT_3_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x5e => {
            /* BIT 3,(HL) */
            instrCB__BIT_3_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x5f => {
            /* BIT 3,A */
            instrCB__BIT_3_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x60 => {
            /* BIT 4,B */
            instrCB__BIT_4_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x61 => {
            /* BIT 4,C */
            instrCB__BIT_4_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x62 => {
            /* BIT 4,D */
            instrCB__BIT_4_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x63 => {
            /* BIT 4,E */
            instrCB__BIT_4_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x64 => {
            /* BIT 4,H */
            instrCB__BIT_4_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x65 => {
            /* BIT 4,L */
            instrCB__BIT_4_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x66 => {
            /* BIT 4,(HL) */
            instrCB__BIT_4_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x67 => {
            /* BIT 4,A */
            instrCB__BIT_4_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x68 => {
            /* BIT 5,B */
            instrCB__BIT_5_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x69 => {
            /* BIT 5,C */
            instrCB__BIT_5_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x6a => {
            /* BIT 5,D */
            instrCB__BIT_5_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x6b => {
            /* BIT 5,E */
            instrCB__BIT_5_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x6c => {
            /* BIT 5,H */
            instrCB__BIT_5_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x6d => {
            /* BIT 5,L */
            instrCB__BIT_5_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x6e => {
            /* BIT 5,(HL) */
            instrCB__BIT_5_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x6f => {
            /* BIT 5,A */
            instrCB__BIT_5_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x70 => {
            /* BIT 6,B */
            instrCB__BIT_6_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x71 => {
            /* BIT 6,C */
            instrCB__BIT_6_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x72 => {
            /* BIT 6,D */
            instrCB__BIT_6_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x73 => {
            /* BIT 6,E */
            instrCB__BIT_6_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x74 => {
            /* BIT 6,H */
            instrCB__BIT_6_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x75 => {
            /* BIT 6,L */
            instrCB__BIT_6_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x76 => {
            /* BIT 6,(HL) */
            instrCB__BIT_6_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x77 => {
            /* BIT 6,A */
            instrCB__BIT_6_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x78 => {
            /* BIT 7,B */
            instrCB__BIT_7_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x79 => {
            /* BIT 7,C */
            instrCB__BIT_7_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x7a => {
            /* BIT 7,D */
            instrCB__BIT_7_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x7b => {
            /* BIT 7,E */
            instrCB__BIT_7_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x7c => {
            /* BIT 7,H */
            instrCB__BIT_7_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x7d => {
            /* BIT 7,L */
            instrCB__BIT_7_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x7e => {
            /* BIT 7,(HL) */
            instrCB__BIT_7_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x7f => {
            /* BIT 7,A */
            instrCB__BIT_7_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x80 => {
            /* RES 0,B */
            instrCB__RES_0_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x81 => {
            /* RES 0,C */
            instrCB__RES_0_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x82 => {
            /* RES 0,D */
            instrCB__RES_0_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x83 => {
            /* RES 0,E */
            instrCB__RES_0_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x84 => {
            /* RES 0,H */
            instrCB__RES_0_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x85 => {
            /* RES 0,L */
            instrCB__RES_0_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x86 => {
            /* RES 0,(HL) */
            instrCB__RES_0_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x87 => {
            /* RES 0,A */
            instrCB__RES_0_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x88 => {
            /* RES 1,B */
            instrCB__RES_1_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x89 => {
            /* RES 1,C */
            instrCB__RES_1_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x8a => {
            /* RES 1,D */
            instrCB__RES_1_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x8b => {
            /* RES 1,E */
            instrCB__RES_1_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x8c => {
            /* RES 1,H */
            instrCB__RES_1_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x8d => {
            /* RES 1,L */
            instrCB__RES_1_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x8e => {
            /* RES 1,(HL) */
            instrCB__RES_1_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x8f => {
            /* RES 1,A */
            instrCB__RES_1_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x90 => {
            /* RES 2,B */
            instrCB__RES_2_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x91 => {
            /* RES 2,C */
            instrCB__RES_2_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x92 => {
            /* RES 2,D */
            instrCB__RES_2_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x93 => {
            /* RES 2,E */
            instrCB__RES_2_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x94 => {
            /* RES 2,H */
            instrCB__RES_2_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x95 => {
            /* RES 2,L */
            instrCB__RES_2_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x96 => {
            /* RES 2,(HL) */
            instrCB__RES_2_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x97 => {
            /* RES 2,A */
            instrCB__RES_2_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x98 => {
            /* RES 3,B */
            instrCB__RES_3_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x99 => {
            /* RES 3,C */
            instrCB__RES_3_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x9a => {
            /* RES 3,D */
            instrCB__RES_3_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x9b => {
            /* RES 3,E */
            instrCB__RES_3_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x9c => {
            /* RES 3,H */
            instrCB__RES_3_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x9d => {
            /* RES 3,L */
            instrCB__RES_3_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0x9e => {
            /* RES 3,(HL) */
            instrCB__RES_3_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0x9f => {
            /* RES 3,A */
            instrCB__RES_3_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xa0 => {
            /* RES 4,B */
            instrCB__RES_4_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xa1 => {
            /* RES 4,C */
            instrCB__RES_4_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xa2 => {
            /* RES 4,D */
            instrCB__RES_4_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xa3 => {
            /* RES 4,E */
            instrCB__RES_4_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xa4 => {
            /* RES 4,H */
            instrCB__RES_4_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xa5 => {
            /* RES 4,L */
            instrCB__RES_4_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xa6 => {
            /* RES 4,(HL) */
            instrCB__RES_4_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xa7 => {
            /* RES 4,A */
            instrCB__RES_4_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xa8 => {
            /* RES 5,B */
            instrCB__RES_5_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xa9 => {
            /* RES 5,C */
            instrCB__RES_5_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xaa => {
            /* RES 5,D */
            instrCB__RES_5_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xab => {
            /* RES 5,E */
            instrCB__RES_5_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xac => {
            /* RES 5,H */
            instrCB__RES_5_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xad => {
            /* RES 5,L */
            instrCB__RES_5_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xae => {
            /* RES 5,(HL) */
            instrCB__RES_5_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xaf => {
            /* RES 5,A */
            instrCB__RES_5_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xb0 => {
            /* RES 6,B */
            instrCB__RES_6_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xb1 => {
            /* RES 6,C */
            instrCB__RES_6_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xb2 => {
            /* RES 6,D */
            instrCB__RES_6_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xb3 => {
            /* RES 6,E */
            instrCB__RES_6_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xb4 => {
            /* RES 6,H */
            instrCB__RES_6_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xb5 => {
            /* RES 6,L */
            instrCB__RES_6_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xb6 => {
            /* RES 6,(HL) */
            instrCB__RES_6_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xb7 => {
            /* RES 6,A */
            instrCB__RES_6_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xb8 => {
            /* RES 7,B */
            instrCB__RES_7_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xb9 => {
            /* RES 7,C */
            instrCB__RES_7_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xba => {
            /* RES 7,D */
            instrCB__RES_7_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xbb => {
            /* RES 7,E */
            instrCB__RES_7_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xbc => {
            /* RES 7,H */
            instrCB__RES_7_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xbd => {
            /* RES 7,L */
            instrCB__RES_7_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xbe => {
            /* RES 7,(HL) */
            instrCB__RES_7_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xbf => {
            /* RES 7,A */
            instrCB__RES_7_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xc0 => {
            /* SET 0,B */
            instrCB__SET_0_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xc1 => {
            /* SET 0,C */
            instrCB__SET_0_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xc2 => {
            /* SET 0,D */
            instrCB__SET_0_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xc3 => {
            /* SET 0,E */
            instrCB__SET_0_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xc4 => {
            /* SET 0,H */
            instrCB__SET_0_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xc5 => {
            /* SET 0,L */
            instrCB__SET_0_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xc6 => {
            /* SET 0,(HL) */
            instrCB__SET_0_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xc7 => {
            /* SET 0,A */
            instrCB__SET_0_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xc8 => {
            /* SET 1,B */
            instrCB__SET_1_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xc9 => {
            /* SET 1,C */
            instrCB__SET_1_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xca => {
            /* SET 1,D */
            instrCB__SET_1_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xcb => {
            /* SET 1,E */
            instrCB__SET_1_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xcc => {
            /* SET 1,H */
            instrCB__SET_1_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xcd => {
            /* SET 1,L */
            instrCB__SET_1_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xce => {
            /* SET 1,(HL) */
            instrCB__SET_1_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xcf => {
            /* SET 1,A */
            instrCB__SET_1_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xd0 => {
            /* SET 2,B */
            instrCB__SET_2_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xd1 => {
            /* SET 2,C */
            instrCB__SET_2_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xd2 => {
            /* SET 2,D */
            instrCB__SET_2_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xd3 => {
            /* SET 2,E */
            instrCB__SET_2_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xd4 => {
            /* SET 2,H */
            instrCB__SET_2_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xd5 => {
            /* SET 2,L */
            instrCB__SET_2_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xd6 => {
            /* SET 2,(HL) */
            instrCB__SET_2_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xd7 => {
            /* SET 2,A */
            instrCB__SET_2_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xd8 => {
            /* SET 3,B */
            instrCB__SET_3_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xd9 => {
            /* SET 3,C */
            instrCB__SET_3_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xda => {
            /* SET 3,D */
            instrCB__SET_3_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xdb => {
            /* SET 3,E */
            instrCB__SET_3_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xdc => {
            /* SET 3,H */
            instrCB__SET_3_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xdd => {
            /* SET 3,L */
            instrCB__SET_3_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xde => {
            /* SET 3,(HL) */
            instrCB__SET_3_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xdf => {
            /* SET 3,A */
            instrCB__SET_3_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xe0 => {
            /* SET 4,B */
            instrCB__SET_4_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xe1 => {
            /* SET 4,C */
            instrCB__SET_4_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xe2 => {
            /* SET 4,D */
            instrCB__SET_4_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xe3 => {
            /* SET 4,E */
            instrCB__SET_4_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xe4 => {
            /* SET 4,H */
            instrCB__SET_4_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xe5 => {
            /* SET 4,L */
            instrCB__SET_4_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xe6 => {
            /* SET 4,(HL) */
            instrCB__SET_4_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xe7 => {
            /* SET 4,A */
            instrCB__SET_4_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xe8 => {
            /* SET 5,B */
            instrCB__SET_5_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xe9 => {
            /* SET 5,C */
            instrCB__SET_5_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xea => {
            /* SET 5,D */
            instrCB__SET_5_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xeb => {
            /* SET 5,E */
            instrCB__SET_5_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xec => {
            /* SET 5,H */
            instrCB__SET_5_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xed => {
            /* SET 5,L */
            instrCB__SET_5_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xee => {
            /* SET 5,(HL) */
            instrCB__SET_5_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xef => {
            /* SET 5,A */
            instrCB__SET_5_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xf0 => {
            /* SET 6,B */
            instrCB__SET_6_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xf1 => {
            /* SET 6,C */
            instrCB__SET_6_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xf2 => {
            /* SET 6,D */
            instrCB__SET_6_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xf3 => {
            /* SET 6,E */
            instrCB__SET_6_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xf4 => {
            /* SET 6,H */
            instrCB__SET_6_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xf5 => {
            /* SET 6,L */
            instrCB__SET_6_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xf6 => {
            /* SET 6,(HL) */
            instrCB__SET_6_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xf7 => {
            /* SET 6,A */
            instrCB__SET_6_A(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xf8 => {
            /* SET 7,B */
            instrCB__SET_7_B(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xf9 => {
            /* SET 7,C */
            instrCB__SET_7_C(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xfa => {
            /* SET 7,D */
            instrCB__SET_7_D(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xfb => {
            /* SET 7,E */
            instrCB__SET_7_E(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xfc => {
            /* SET 7,H */
            instrCB__SET_7_H(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xfd => {
            /* SET 7,L */
            instrCB__SET_7_L(data);
            true
        }

        val if val == SHIFT_0X_CB + 0xfe => {
            /* SET 7,(HL) */
            instrCB__SET_7_iHL(data, memory);
            true
        }

        val if val == SHIFT_0X_CB + 0xff => {
            /* SET 7,A */
            instrCB__SET_7_A(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x40 => {
            /* IN B,(C) */
            instrED__IN_B_iC(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x41 => {
            /* OUT (C),B */
            instrED__OUT_iC_B(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x42 => {
            /* SBC HL,BC */
            instrED__SBC_HL_BC(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x43 => {
            /* LD (nnnn),BC */
            instrED__LD_iNNNN_BC(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x7c => {
            /* NEG */
            instrED__NEG(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x44 => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c]();return true;
            instrED__NEG(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x4c => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c]();return true;
            instrED__NEG(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x54 => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c]();return true;
            instrED__NEG(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x5c => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c]();return true;
            instrED__NEG(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x64 => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c]();return true;
            instrED__NEG(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x6c => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c]();return true;
            instrED__NEG(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x74 => {
            /* NEG */
            // self.OpcodesMap[SHIFT_0xED + 0x7c]();return true;
            instrED__NEG(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x7d => {
            /* RETN */
            instrED__RETN(data, memory, hook);
            true
        }

        val if val == SHIFT_0X_ED + 0x45 => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d]();return true;
            instrED__RETN(data, memory, hook);
            true
        }

        val if val == SHIFT_0X_ED + 0x4d => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d]();return true;
            instrED__RETN(data, memory, hook);
            true
        }

        val if val == SHIFT_0X_ED + 0x55 => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d]();return true;
            instrED__RETN(data, memory, hook);
            true
        }

        val if val == SHIFT_0X_ED + 0x5d => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d]();return true;
            instrED__RETN(data, memory, hook);
            true
        }

        val if val == SHIFT_0X_ED + 0x65 => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d]();return true;
            instrED__RETN(data, memory, hook);
            true
        }

        val if val == SHIFT_0X_ED + 0x6d => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d]();return true;
            instrED__RETN(data, memory, hook);
            true
        }

        val if val == SHIFT_0X_ED + 0x75 => {
            /* RETN */
            // self.OpcodesMap[SHIFT_0xED + 0x7d]();return true;
            instrED__RETN(data, memory, hook);
            true
        }

        val if val == SHIFT_0X_ED + 0x6e => {
            /* IM 0 */
            instrED__IM_0(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x46 => {
            /* IM 0 */
            // self.OpcodesMap[SHIFT_0xED + 0x6e]();return true;
            instrED__IM_0(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x4e => {
            /* IM 0 */
            // self.OpcodesMap[SHIFT_0xED + 0x6e]();return true;
            instrED__IM_0(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x66 => {
            /* IM 0 */
            // self.OpcodesMap[SHIFT_0xED + 0x6e]();return true;
            instrED__IM_0(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x47 => {
            /* LD I,A */
            instrED__LD_I_A(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x48 => {
            /* IN C,(C) */
            instrED__IN_C_iC(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x49 => {
            /* OUT (C),C */
            instrED__OUT_iC_C(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x4a => {
            /* ADC HL,BC */
            instrED__ADC_HL_BC(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x4b => {
            /* LD BC,(nnnn) */
            instrED__LD_BC_iNNNN(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x4f => {
            /* LD R,A */
            instrED__LD_R_A(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x50 => {
            /* IN D,(C) */
            instrED__IN_D_iC(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x51 => {
            /* OUT (C),D */
            instrED__OUT_iC_D(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x52 => {
            /* SBC HL,DE */
            instrED__SBC_HL_DE(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x53 => {
            /* LD (nnnn),DE */
            instrED__LD_iNNNN_DE(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x76 => {
            /* IM 1 */
            instrED__IM_1(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x56 => {
            /* IM 1 */
            // self.OpcodesMap[SHIFT_0xED + 0x76]();return true;
            instrED__IM_1(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x57 => {
            /* LD A,I */
            instrED__LD_A_I(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x58 => {
            /* IN E,(C) */
            instrED__IN_E_iC(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x59 => {
            /* OUT (C),E */
            instrED__OUT_iC_E(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x5a => {
            /* ADC HL,DE */
            instrED__ADC_HL_DE(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x5b => {
            /* LD DE,(nnnn) */
            instrED__LD_DE_iNNNN(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x7e => {
            /* IM 2 */
            instrED__IM_2(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x5e => {
            /* IM 2 */
            // self.OpcodesMap[SHIFT_0xED + 0x7e]();return true;
            instrED__IM_2(data);
            true
        }

        val if val == SHIFT_0X_ED + 0x5f => {
            /* LD A,R */
            instrED__LD_A_R(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x60 => {
            /* IN H,(C) */
            instrED__IN_H_iC(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x61 => {
            /* OUT (C),H */
            instrED__OUT_iC_H(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x62 => {
            /* SBC HL,HL */
            instrED__SBC_HL_HL(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x63 => {
            /* LD (nnnn),HL */
            instrED__LD_iNNNN_HL(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x67 => {
            /* RRD */
            instrED__RRD(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x68 => {
            /* IN L,(C) */
            instrED__IN_L_iC(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x69 => {
            /* OUT (C),L */
            instrED__OUT_iC_L(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x6a => {
            /* ADC HL,HL */
            instrED__ADC_HL_HL(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x6b => {
            /* LD HL,(nnnn) */
            instrED__LD_HL_iNNNN(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x6f => {
            /* RLD */
            instrED__RLD(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x70 => {
            /* IN F,(C) */
            instrED__IN_F_iC(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x71 => {
            /* OUT (C),0 */
            instrED__OUT_iC_0(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x72 => {
            /* SBC HL,SP */
            instrED__SBC_HL_SP(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x73 => {
            /* LD (nnnn),SP */
            instrED__LD_iNNNN_SP(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x78 => {
            /* IN A,(C) */
            instrED__IN_A_iC(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x79 => {
            /* OUT (C),A */
            instrED__OUT_iC_A(data, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0x7a => {
            /* ADC HL,SP */
            instrED__ADC_HL_SP(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0x7b => {
            /* LD SP,(nnnn) */
            instrED__LD_SP_iNNNN(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0xa0 => {
            /* LDI */
            instrED__LDI(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0xa1 => {
            /* CPI */
            instrED__CPI(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0xa2 => {
            /* INI */
            instrED__INI(data, memory, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0xa3 => {
            /* OUTI */
            instrED__OUTI(data, memory, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0xa8 => {
            /* LDD */
            instrED__LDD(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0xa9 => {
            /* CPD */
            instrED__CPD(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0xaa => {
            /* IND */
            instrED__IND(data, memory, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0xab => {
            /* OUTD */
            instrED__OUTD(data, memory, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0xb0 => {
            /* LDIR */
            instrED__LDIR(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0xb1 => {
            /* CPIR */
            instrED__CPIR(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0xb2 => {
            /* INIR */
            instrED__INIR(data, memory, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0xb3 => {
            /* OTIR */
            instrED__OTIR(data, memory, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0xb8 => {
            /* LDDR */
            instrED__LDDR(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0xb9 => {
            /* CPDR */
            instrED__CPDR(data, memory);
            true
        }

        val if val == SHIFT_0X_ED + 0xba => {
            /* INDR */
            instrED__INDR(data, memory, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0xbb => {
            /* OTDR */
            instrED__OTDR(data, memory, ports);
            true
        }

        val if val == SHIFT_0X_ED + 0xfb => {
            /* slttrap */
            instrED__SLTTRAP(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x09 => {
            /* ADD REGISTER,BC */
            instrDD__ADD_REG_BC(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x19 => {
            /* ADD REGISTER,DE */
            instrDD__ADD_REG_DE(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x21 => {
            /* LD REGISTER,nnnn */
            instrDD__LD_REG_NNNN(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x22 => {
            /* LD (nnnn),REGISTER */
            instrDD__LD_iNNNN_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x23 => {
            /* INC REGISTER */
            instrDD__INC_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x24 => {
            /* INC REGISTERH */
            instrDD__INC_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x25 => {
            /* DEC REGISTERH */
            instrDD__DEC_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x26 => {
            /* LD REGISTERH,nn */
            instrDD__LD_REGH_NN(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x29 => {
            /* ADD REGISTER,REGISTER */
            instrDD__ADD_REG_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x2a => {
            /* LD REGISTER,(nnnn) */
            instrDD__LD_REG_iNNNN(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x2b => {
            /* DEC REGISTER */
            instrDD__DEC_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x2c => {
            /* INC REGISTERL */
            instrDD__INC_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x2d => {
            /* DEC REGISTERL */
            instrDD__DEC_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x2e => {
            /* LD REGISTERL,nn */
            instrDD__LD_REGL_NN(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x34 => {
            /* INC (REGISTER+dd) */
            instrDD__INC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x35 => {
            /* DEC (REGISTER+dd) */
            instrDD__DEC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x36 => {
            /* LD (REGISTER+dd),nn */
            instrDD__LD_iREGpDD_NN(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x39 => {
            /* ADD REGISTER,SP */
            instrDD__ADD_REG_SP(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x44 => {
            /* LD B,REGISTERH */
            instrDD__LD_B_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x45 => {
            /* LD B,REGISTERL */
            instrDD__LD_B_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x46 => {
            /* LD B,(REGISTER+dd) */
            instrDD__LD_B_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x4c => {
            /* LD C,REGISTERH */
            instrDD__LD_C_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x4d => {
            /* LD C,REGISTERL */
            instrDD__LD_C_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x4e => {
            /* LD C,(REGISTER+dd) */
            instrDD__LD_C_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x54 => {
            /* LD D,REGISTERH */
            instrDD__LD_D_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x55 => {
            /* LD D,REGISTERL */
            instrDD__LD_D_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x56 => {
            /* LD D,(REGISTER+dd) */
            instrDD__LD_D_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x5c => {
            /* LD E,REGISTERH */
            instrDD__LD_E_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x5d => {
            /* LD E,REGISTERL */
            instrDD__LD_E_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x5e => {
            /* LD E,(REGISTER+dd) */
            instrDD__LD_E_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x60 => {
            /* LD REGISTERH,B */
            instrDD__LD_REGH_B(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x61 => {
            /* LD REGISTERH,C */
            instrDD__LD_REGH_C(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x62 => {
            /* LD REGISTERH,D */
            instrDD__LD_REGH_D(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x63 => {
            /* LD REGISTERH,E */
            instrDD__LD_REGH_E(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x64 => {
            /* LD REGISTERH,REGISTERH */
            instrDD__LD_REGH_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x65 => {
            /* LD REGISTERH,REGISTERL */
            instrDD__LD_REGH_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x66 => {
            /* LD H,(REGISTER+dd) */
            instrDD__LD_H_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x67 => {
            /* LD REGISTERH,A */
            instrDD__LD_REGH_A(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x68 => {
            /* LD REGISTERL,B */
            instrDD__LD_REGL_B(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x69 => {
            /* LD REGISTERL,C */
            instrDD__LD_REGL_C(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x6a => {
            /* LD REGISTERL,D */
            instrDD__LD_REGL_D(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x6b => {
            /* LD REGISTERL,E */
            instrDD__LD_REGL_E(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x6c => {
            /* LD REGISTERL,REGISTERH */
            instrDD__LD_REGL_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x6d => {
            /* LD REGISTERL,REGISTERL */
            instrDD__LD_REGL_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x6e => {
            /* LD L,(REGISTER+dd) */
            instrDD__LD_L_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x6f => {
            /* LD REGISTERL,A */
            instrDD__LD_REGL_A(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x70 => {
            /* LD (REGISTER+dd),B */
            instrDD__LD_iREGpDD_B(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x71 => {
            /* LD (REGISTER+dd),C */
            instrDD__LD_iREGpDD_C(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x72 => {
            /* LD (REGISTER+dd),D */
            instrDD__LD_iREGpDD_D(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x73 => {
            /* LD (REGISTER+dd),E */
            instrDD__LD_iREGpDD_E(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x74 => {
            /* LD (REGISTER+dd),H */
            instrDD__LD_iREGpDD_H(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x75 => {
            /* LD (REGISTER+dd),L */
            instrDD__LD_iREGpDD_L(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x77 => {
            /* LD (REGISTER+dd),A */
            instrDD__LD_iREGpDD_A(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x7c => {
            /* LD A,REGISTERH */
            instrDD__LD_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x7d => {
            /* LD A,REGISTERL */
            instrDD__LD_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x7e => {
            /* LD A,(REGISTER+dd) */
            instrDD__LD_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x84 => {
            /* ADD A,REGISTERH */
            instrDD__ADD_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x85 => {
            /* ADD A,REGISTERL */
            instrDD__ADD_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x86 => {
            /* ADD A,(REGISTER+dd) */
            instrDD__ADD_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x8c => {
            /* ADC A,REGISTERH */
            instrDD__ADC_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x8d => {
            /* ADC A,REGISTERL */
            instrDD__ADC_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x8e => {
            /* ADC A,(REGISTER+dd) */
            instrDD__ADC_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x94 => {
            /* SUB A,REGISTERH */
            instrDD__SUB_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x95 => {
            /* SUB A,REGISTERL */
            instrDD__SUB_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x96 => {
            /* SUB A,(REGISTER+dd) */
            instrDD__SUB_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0x9c => {
            /* SBC A,REGISTERH */
            instrDD__SBC_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x9d => {
            /* SBC A,REGISTERL */
            instrDD__SBC_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0x9e => {
            /* SBC A,(REGISTER+dd) */
            instrDD__SBC_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0xa4 => {
            /* AND A,REGISTERH */
            instrDD__AND_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0xa5 => {
            /* AND A,REGISTERL */
            instrDD__AND_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0xa6 => {
            /* AND A,(REGISTER+dd) */
            instrDD__AND_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0xac => {
            /* XOR A,REGISTERH */
            instrDD__XOR_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0xad => {
            /* XOR A,REGISTERL */
            instrDD__XOR_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0xae => {
            /* XOR A,(REGISTER+dd) */
            instrDD__XOR_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0xb4 => {
            /* OR A,REGISTERH */
            instrDD__OR_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0xb5 => {
            /* OR A,REGISTERL */
            instrDD__OR_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0xb6 => {
            /* OR A,(REGISTER+dd) */
            instrDD__OR_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0xbc => {
            /* CP A,REGISTERH */
            instrDD__CP_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_DD + 0xbd => {
            /* CP A,REGISTERL */
            instrDD__CP_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_DD + 0xbe => {
            /* CP A,(REGISTER+dd) */
            instrDD__CP_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0xcb => {
            /* shift DDFDCB */
            instrDD__SHIFT_DDFDCB(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0xe1 => {
            /* POP REGISTER */
            instrDD__POP_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0xe3 => {
            /* EX (SP),REGISTER */
            instrDD__EX_iSP_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0xe5 => {
            /* PUSH REGISTER */
            instrDD__PUSH_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_DD + 0xe9 => {
            /* JP REGISTER */
            instrDD__JP_REG(data);
            true
        }

        val if val == SHIFT_0X_DD + 0xf9 => {
            /* LD SP,REGISTER */
            instrDD__LD_SP_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x09 => {
            /* ADD REGISTER,BC */
            instrFD__ADD_REG_BC(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x19 => {
            /* ADD REGISTER,DE */
            instrFD__ADD_REG_DE(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x21 => {
            /* LD REGISTER,nnnn */
            instrFD__LD_REG_NNNN(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x22 => {
            /* LD (nnnn),REGISTER */
            instrFD__LD_iNNNN_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x23 => {
            /* INC REGISTER */
            instrFD__INC_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x24 => {
            /* INC REGISTERH */
            instrFD__INC_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x25 => {
            /* DEC REGISTERH */
            instrFD__DEC_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x26 => {
            /* LD REGISTERH,nn */
            instrFD__LD_REGH_NN(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x29 => {
            /* ADD REGISTER,REGISTER */
            instrFD__ADD_REG_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x2a => {
            /* LD REGISTER,(nnnn) */
            instrFD__LD_REG_iNNNN(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x2b => {
            /* DEC REGISTER */
            instrFD__DEC_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x2c => {
            /* INC REGISTERL */
            instrFD__INC_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x2d => {
            /* DEC REGISTERL */
            instrFD__DEC_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x2e => {
            /* LD REGISTERL,nn */
            instrFD__LD_REGL_NN(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x34 => {
            /* INC (REGISTER+dd) */
            instrFD__INC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x35 => {
            /* DEC (REGISTER+dd) */
            instrFD__DEC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x36 => {
            /* LD (REGISTER+dd),nn */
            instrFD__LD_iREGpDD_NN(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x39 => {
            /* ADD REGISTER,SP */
            instrFD__ADD_REG_SP(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x44 => {
            /* LD B,REGISTERH */
            instrFD__LD_B_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x45 => {
            /* LD B,REGISTERL */
            instrFD__LD_B_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x46 => {
            /* LD B,(REGISTER+dd) */
            instrFD__LD_B_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x4c => {
            /* LD C,REGISTERH */
            instrFD__LD_C_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x4d => {
            /* LD C,REGISTERL */
            instrFD__LD_C_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x4e => {
            /* LD C,(REGISTER+dd) */
            instrFD__LD_C_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x54 => {
            /* LD D,REGISTERH */
            instrFD__LD_D_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x55 => {
            /* LD D,REGISTERL */
            instrFD__LD_D_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x56 => {
            /* LD D,(REGISTER+dd) */
            instrFD__LD_D_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x5c => {
            /* LD E,REGISTERH */
            instrFD__LD_E_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x5d => {
            /* LD E,REGISTERL */
            instrFD__LD_E_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x5e => {
            /* LD E,(REGISTER+dd) */
            instrFD__LD_E_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x60 => {
            /* LD REGISTERH,B */
            instrFD__LD_REGH_B(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x61 => {
            /* LD REGISTERH,C */
            instrFD__LD_REGH_C(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x62 => {
            /* LD REGISTERH,D */
            instrFD__LD_REGH_D(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x63 => {
            /* LD REGISTERH,E */
            instrFD__LD_REGH_E(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x64 => {
            /* LD REGISTERH,REGISTERH */
            instrFD__LD_REGH_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x65 => {
            /* LD REGISTERH,REGISTERL */
            instrFD__LD_REGH_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x66 => {
            /* LD H,(REGISTER+dd) */
            instrFD__LD_H_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x67 => {
            /* LD REGISTERH,A */
            instrFD__LD_REGH_A(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x68 => {
            /* LD REGISTERL,B */
            instrFD__LD_REGL_B(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x69 => {
            /* LD REGISTERL,C */
            instrFD__LD_REGL_C(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x6a => {
            /* LD REGISTERL,D */
            instrFD__LD_REGL_D(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x6b => {
            /* LD REGISTERL,E */
            instrFD__LD_REGL_E(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x6c => {
            /* LD REGISTERL,REGISTERH */
            instrFD__LD_REGL_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x6d => {
            /* LD REGISTERL,REGISTERL */
            instrFD__LD_REGL_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x6e => {
            /* LD L,(REGISTER+dd) */
            instrFD__LD_L_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x6f => {
            /* LD REGISTERL,A */
            instrFD__LD_REGL_A(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x70 => {
            /* LD (REGISTER+dd),B */
            instrFD__LD_iREGpDD_B(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x71 => {
            /* LD (REGISTER+dd),C */
            instrFD__LD_iREGpDD_C(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x72 => {
            /* LD (REGISTER+dd),D */
            instrFD__LD_iREGpDD_D(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x73 => {
            /* LD (REGISTER+dd),E */
            instrFD__LD_iREGpDD_E(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x74 => {
            /* LD (REGISTER+dd),H */
            instrFD__LD_iREGpDD_H(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x75 => {
            /* LD (REGISTER+dd),L */
            instrFD__LD_iREGpDD_L(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x77 => {
            /* LD (REGISTER+dd),A */
            instrFD__LD_iREGpDD_A(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x7c => {
            /* LD A,REGISTERH */
            instrFD__LD_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x7d => {
            /* LD A,REGISTERL */
            instrFD__LD_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x7e => {
            /* LD A,(REGISTER+dd) */
            instrFD__LD_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x84 => {
            /* ADD A,REGISTERH */
            instrFD__ADD_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x85 => {
            /* ADD A,REGISTERL */
            instrFD__ADD_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x86 => {
            /* ADD A,(REGISTER+dd) */
            instrFD__ADD_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x8c => {
            /* ADC A,REGISTERH */
            instrFD__ADC_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x8d => {
            /* ADC A,REGISTERL */
            instrFD__ADC_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x8e => {
            /* ADC A,(REGISTER+dd) */
            instrFD__ADC_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x94 => {
            /* SUB A,REGISTERH */
            instrFD__SUB_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x95 => {
            /* SUB A,REGISTERL */
            instrFD__SUB_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x96 => {
            /* SUB A,(REGISTER+dd) */
            instrFD__SUB_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0x9c => {
            /* SBC A,REGISTERH */
            instrFD__SBC_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x9d => {
            /* SBC A,REGISTERL */
            instrFD__SBC_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0x9e => {
            /* SBC A,(REGISTER+dd) */
            instrFD__SBC_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0xa4 => {
            /* AND A,REGISTERH */
            instrFD__AND_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0xa5 => {
            /* AND A,REGISTERL */
            instrFD__AND_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0xa6 => {
            /* AND A,(REGISTER+dd) */
            instrFD__AND_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0xac => {
            /* XOR A,REGISTERH */
            instrFD__XOR_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0xad => {
            /* XOR A,REGISTERL */
            instrFD__XOR_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0xae => {
            /* XOR A,(REGISTER+dd) */
            instrFD__XOR_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0xb4 => {
            /* OR A,REGISTERH */
            instrFD__OR_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0xb5 => {
            /* OR A,REGISTERL */
            instrFD__OR_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0xb6 => {
            /* OR A,(REGISTER+dd) */
            instrFD__OR_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0xbc => {
            /* CP A,REGISTERH */
            instrFD__CP_A_REGH(data);
            true
        }

        val if val == SHIFT_0X_FD + 0xbd => {
            /* CP A,REGISTERL */
            instrFD__CP_A_REGL(data);
            true
        }

        val if val == SHIFT_0X_FD + 0xbe => {
            /* CP A,(REGISTER+dd) */
            instrFD__CP_A_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0xcb => {
            /* shift DDFDCB */
            instrFD__SHIFT_DDFDCB(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0xe1 => {
            /* POP REGISTER */
            instrFD__POP_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0xe3 => {
            /* EX (SP),REGISTER */
            instrFD__EX_iSP_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0xe5 => {
            /* PUSH REGISTER */
            instrFD__PUSH_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_FD + 0xe9 => {
            /* JP REGISTER */
            instrFD__JP_REG(data);
            true
        }

        val if val == SHIFT_0X_FD + 0xf9 => {
            /* LD SP,REGISTER */
            instrFD__LD_SP_REG(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB => {
            /* LD B,RLC (REGISTER+dd) */
            instrDDCB__LD_B_RLC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x01 => {
            /* LD C,RLC (REGISTER+dd) */
            instrDDCB__LD_C_RLC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x02 => {
            /* LD D,RLC (REGISTER+dd) */
            instrDDCB__LD_D_RLC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x03 => {
            /* LD E,RLC (REGISTER+dd) */
            instrDDCB__LD_E_RLC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x04 => {
            /* LD H,RLC (REGISTER+dd) */
            instrDDCB__LD_H_RLC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x05 => {
            /* LD L,RLC (REGISTER+dd) */
            instrDDCB__LD_L_RLC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x06 => {
            /* RLC (REGISTER+dd) */
            instrDDCB__RLC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x07 => {
            /* LD A,RLC (REGISTER+dd) */
            instrDDCB__LD_A_RLC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x08 => {
            /* LD B,RRC (REGISTER+dd) */
            instrDDCB__LD_B_RRC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x09 => {
            /* LD C,RRC (REGISTER+dd) */
            instrDDCB__LD_C_RRC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x0a => {
            /* LD D,RRC (REGISTER+dd) */
            instrDDCB__LD_D_RRC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x0b => {
            /* LD E,RRC (REGISTER+dd) */
            instrDDCB__LD_E_RRC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x0c => {
            /* LD H,RRC (REGISTER+dd) */
            instrDDCB__LD_H_RRC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x0d => {
            /* LD L,RRC (REGISTER+dd) */
            instrDDCB__LD_L_RRC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x0e => {
            /* RRC (REGISTER+dd) */
            instrDDCB__RRC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x0f => {
            /* LD A,RRC (REGISTER+dd) */
            instrDDCB__LD_A_RRC_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x10 => {
            /* LD B,RL (REGISTER+dd) */
            instrDDCB__LD_B_RL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x11 => {
            /* LD C,RL (REGISTER+dd) */
            instrDDCB__LD_C_RL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x12 => {
            /* LD D,RL (REGISTER+dd) */
            instrDDCB__LD_D_RL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x13 => {
            /* LD E,RL (REGISTER+dd) */
            instrDDCB__LD_E_RL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x14 => {
            /* LD H,RL (REGISTER+dd) */
            instrDDCB__LD_H_RL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x15 => {
            /* LD L,RL (REGISTER+dd) */
            instrDDCB__LD_L_RL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x16 => {
            /* RL (REGISTER+dd) */
            instrDDCB__RL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x17 => {
            /* LD A,RL (REGISTER+dd) */
            instrDDCB__LD_A_RL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x18 => {
            /* LD B,RR (REGISTER+dd) */
            instrDDCB__LD_B_RR_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x19 => {
            /* LD C,RR (REGISTER+dd) */
            instrDDCB__LD_C_RR_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x1a => {
            /* LD D,RR (REGISTER+dd) */
            instrDDCB__LD_D_RR_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x1b => {
            /* LD E,RR (REGISTER+dd) */
            instrDDCB__LD_E_RR_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x1c => {
            /* LD H,RR (REGISTER+dd) */
            instrDDCB__LD_H_RR_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x1d => {
            /* LD L,RR (REGISTER+dd) */
            instrDDCB__LD_L_RR_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x1e => {
            /* RR (REGISTER+dd) */
            instrDDCB__RR_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x1f => {
            /* LD A,RR (REGISTER+dd) */
            instrDDCB__LD_A_RR_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x20 => {
            /* LD B,SLA (REGISTER+dd) */
            instrDDCB__LD_B_SLA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x21 => {
            /* LD C,SLA (REGISTER+dd) */
            instrDDCB__LD_C_SLA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x22 => {
            /* LD D,SLA (REGISTER+dd) */
            instrDDCB__LD_D_SLA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x23 => {
            /* LD E,SLA (REGISTER+dd) */
            instrDDCB__LD_E_SLA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x24 => {
            /* LD H,SLA (REGISTER+dd) */
            instrDDCB__LD_H_SLA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x25 => {
            /* LD L,SLA (REGISTER+dd) */
            instrDDCB__LD_L_SLA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x26 => {
            /* SLA (REGISTER+dd) */
            instrDDCB__SLA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x27 => {
            /* LD A,SLA (REGISTER+dd) */
            instrDDCB__LD_A_SLA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x28 => {
            /* LD B,SRA (REGISTER+dd) */
            instrDDCB__LD_B_SRA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x29 => {
            /* LD C,SRA (REGISTER+dd) */
            instrDDCB__LD_C_SRA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x2a => {
            /* LD D,SRA (REGISTER+dd) */
            instrDDCB__LD_D_SRA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x2b => {
            /* LD E,SRA (REGISTER+dd) */
            instrDDCB__LD_E_SRA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x2c => {
            /* LD H,SRA (REGISTER+dd) */
            instrDDCB__LD_H_SRA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x2d => {
            /* LD L,SRA (REGISTER+dd) */
            instrDDCB__LD_L_SRA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x2e => {
            /* SRA (REGISTER+dd) */
            instrDDCB__SRA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x2f => {
            /* LD A,SRA (REGISTER+dd) */
            instrDDCB__LD_A_SRA_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x30 => {
            /* LD B,SLL (REGISTER+dd) */
            instrDDCB__LD_B_SLL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x31 => {
            /* LD C,SLL (REGISTER+dd) */
            instrDDCB__LD_C_SLL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x32 => {
            /* LD D,SLL (REGISTER+dd) */
            instrDDCB__LD_D_SLL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x33 => {
            /* LD E,SLL (REGISTER+dd) */
            instrDDCB__LD_E_SLL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x34 => {
            /* LD H,SLL (REGISTER+dd) */
            instrDDCB__LD_H_SLL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x35 => {
            /* LD L,SLL (REGISTER+dd) */
            instrDDCB__LD_L_SLL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x36 => {
            /* SLL (REGISTER+dd) */
            instrDDCB__SLL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x37 => {
            /* LD A,SLL (REGISTER+dd) */
            instrDDCB__LD_A_SLL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x38 => {
            /* LD B,SRL (REGISTER+dd) */
            instrDDCB__LD_B_SRL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x39 => {
            /* LD C,SRL (REGISTER+dd) */
            instrDDCB__LD_C_SRL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x3a => {
            /* LD D,SRL (REGISTER+dd) */
            instrDDCB__LD_D_SRL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x3b => {
            /* LD E,SRL (REGISTER+dd) */
            instrDDCB__LD_E_SRL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x3c => {
            /* LD H,SRL (REGISTER+dd) */
            instrDDCB__LD_H_SRL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x3d => {
            /* LD L,SRL (REGISTER+dd) */
            instrDDCB__LD_L_SRL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x3e => {
            /* SRL (REGISTER+dd) */
            instrDDCB__SRL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x3f => {
            /* LD A,SRL (REGISTER+dd) */
            instrDDCB__LD_A_SRL_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x47 => {
            /* BIT 0,(REGISTER+dd) */
            instrDDCB__BIT_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x40 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47]();return true;
            instrDDCB__BIT_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x41 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47]();return true;
            instrDDCB__BIT_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x42 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47]();return true;
            instrDDCB__BIT_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x43 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47]();return true;
            instrDDCB__BIT_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x44 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47]();return true;
            instrDDCB__BIT_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x45 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47]();return true;
            instrDDCB__BIT_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x46 => {
            /* BIT 0,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x47]();return true;
            instrDDCB__BIT_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x4f => {
            /* BIT 1,(REGISTER+dd) */
            instrDDCB__BIT_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x48 => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f]();return true;
            instrDDCB__BIT_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x49 => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f]();return true;
            instrDDCB__BIT_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x4a => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f]();return true;
            instrDDCB__BIT_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x4b => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f]();return true;
            instrDDCB__BIT_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x4c => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f]();return true;
            instrDDCB__BIT_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x4d => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f]();return true;
            instrDDCB__BIT_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x4e => {
            /* BIT 1,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x4f]();return true;
            instrDDCB__BIT_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x57 => {
            /* BIT 2,(REGISTER+dd) */
            instrDDCB__BIT_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x50 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57]();return true;
            instrDDCB__BIT_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x51 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57]();return true;
            instrDDCB__BIT_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x52 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57]();return true;
            instrDDCB__BIT_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x53 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57]();return true;
            instrDDCB__BIT_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x54 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57]();return true;
            instrDDCB__BIT_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x55 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57]();return true;
            instrDDCB__BIT_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x56 => {
            /* BIT 2,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x57]();return true;
            instrDDCB__BIT_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x5f => {
            /* BIT 3,(REGISTER+dd) */
            instrDDCB__BIT_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x58 => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f]();return true;
            instrDDCB__BIT_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x59 => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f]();return true;
            instrDDCB__BIT_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x5a => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f]();return true;
            instrDDCB__BIT_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x5b => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f]();return true;
            instrDDCB__BIT_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x5c => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f]();return true;
            instrDDCB__BIT_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x5d => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f]();return true;
            instrDDCB__BIT_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x5e => {
            /* BIT 3,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x5f]();return true;
            instrDDCB__BIT_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x67 => {
            /* BIT 4,(REGISTER+dd) */
            instrDDCB__BIT_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x60 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67]();return true;
            instrDDCB__BIT_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x61 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67]();return true;
            instrDDCB__BIT_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x62 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67]();return true;
            instrDDCB__BIT_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x63 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67]();return true;
            instrDDCB__BIT_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x64 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67]();return true;
            instrDDCB__BIT_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x65 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67]();return true;
            instrDDCB__BIT_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x66 => {
            /* BIT 4,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x67]();return true;
            instrDDCB__BIT_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x6f => {
            /* BIT 5,(REGISTER+dd) */
            instrDDCB__BIT_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x68 => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f]();return true;
            instrDDCB__BIT_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x69 => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f]();return true;
            instrDDCB__BIT_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x6a => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f]();return true;
            instrDDCB__BIT_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x6b => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f]();return true;
            instrDDCB__BIT_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x6c => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f]();return true;
            instrDDCB__BIT_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x6d => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f]();return true;
            instrDDCB__BIT_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x6e => {
            /* BIT 5,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x6f]();return true;
            instrDDCB__BIT_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x77 => {
            /* BIT 6,(REGISTER+dd) */
            instrDDCB__BIT_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x70 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77]();return true;
            instrDDCB__BIT_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x71 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77]();return true;
            instrDDCB__BIT_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x72 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77]();return true;
            instrDDCB__BIT_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x73 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77]();return true;
            instrDDCB__BIT_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x74 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77]();return true;
            instrDDCB__BIT_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x75 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77]();return true;
            instrDDCB__BIT_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x76 => {
            /* BIT 6,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x77]();return true;
            instrDDCB__BIT_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x7f => {
            /* BIT 7,(REGISTER+dd) */
            instrDDCB__BIT_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x78 => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f]();return true;
            instrDDCB__BIT_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x79 => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f]();return true;
            instrDDCB__BIT_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x7a => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f]();return true;
            instrDDCB__BIT_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x7b => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f]();return true;
            instrDDCB__BIT_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x7c => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f]();return true;
            instrDDCB__BIT_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x7d => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f]();return true;
            instrDDCB__BIT_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x7e => {
            /* BIT 7,(REGISTER+dd) */
            // self.OpcodesMap[SHIFT_0xDDCB + 0x7f]();return true;
            instrDDCB__BIT_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x80 => {
            /* LD B,RES 0,(REGISTER+dd) */
            instrDDCB__LD_B_RES_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x81 => {
            /* LD C,RES 0,(REGISTER+dd) */
            instrDDCB__LD_C_RES_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x82 => {
            /* LD D,RES 0,(REGISTER+dd) */
            instrDDCB__LD_D_RES_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x83 => {
            /* LD E,RES 0,(REGISTER+dd) */
            instrDDCB__LD_E_RES_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x84 => {
            /* LD H,RES 0,(REGISTER+dd) */
            instrDDCB__LD_H_RES_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x85 => {
            /* LD L,RES 0,(REGISTER+dd) */
            instrDDCB__LD_L_RES_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x86 => {
            /* RES 0,(REGISTER+dd) */
            instrDDCB__RES_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x87 => {
            /* LD A,RES 0,(REGISTER+dd) */
            instrDDCB__LD_A_RES_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x88 => {
            /* LD B,RES 1,(REGISTER+dd) */
            instrDDCB__LD_B_RES_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x89 => {
            /* LD C,RES 1,(REGISTER+dd) */
            instrDDCB__LD_C_RES_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x8a => {
            /* LD D,RES 1,(REGISTER+dd) */
            instrDDCB__LD_D_RES_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x8b => {
            /* LD E,RES 1,(REGISTER+dd) */
            instrDDCB__LD_E_RES_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x8c => {
            /* LD H,RES 1,(REGISTER+dd) */
            instrDDCB__LD_H_RES_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x8d => {
            /* LD L,RES 1,(REGISTER+dd) */
            instrDDCB__LD_L_RES_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x8e => {
            /* RES 1,(REGISTER+dd) */
            instrDDCB__RES_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x8f => {
            /* LD A,RES 1,(REGISTER+dd) */
            instrDDCB__LD_A_RES_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x90 => {
            /* LD B,RES 2,(REGISTER+dd) */
            instrDDCB__LD_B_RES_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x91 => {
            /* LD C,RES 2,(REGISTER+dd) */
            instrDDCB__LD_C_RES_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x92 => {
            /* LD D,RES 2,(REGISTER+dd) */
            instrDDCB__LD_D_RES_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x93 => {
            /* LD E,RES 2,(REGISTER+dd) */
            instrDDCB__LD_E_RES_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x94 => {
            /* LD H,RES 2,(REGISTER+dd) */
            instrDDCB__LD_H_RES_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x95 => {
            /* LD L,RES 2,(REGISTER+dd) */
            instrDDCB__LD_L_RES_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x96 => {
            /* RES 2,(REGISTER+dd) */
            instrDDCB__RES_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x97 => {
            /* LD A,RES 2,(REGISTER+dd) */
            instrDDCB__LD_A_RES_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x98 => {
            /* LD B,RES 3,(REGISTER+dd) */
            instrDDCB__LD_B_RES_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x99 => {
            /* LD C,RES 3,(REGISTER+dd) */
            instrDDCB__LD_C_RES_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x9a => {
            /* LD D,RES 3,(REGISTER+dd) */
            instrDDCB__LD_D_RES_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x9b => {
            /* LD E,RES 3,(REGISTER+dd) */
            instrDDCB__LD_E_RES_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x9c => {
            /* LD H,RES 3,(REGISTER+dd) */
            instrDDCB__LD_H_RES_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x9d => {
            /* LD L,RES 3,(REGISTER+dd) */
            instrDDCB__LD_L_RES_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x9e => {
            /* RES 3,(REGISTER+dd) */
            instrDDCB__RES_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0x9f => {
            /* LD A,RES 3,(REGISTER+dd) */
            instrDDCB__LD_A_RES_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xa0 => {
            /* LD B,RES 4,(REGISTER+dd) */
            instrDDCB__LD_B_RES_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xa1 => {
            /* LD C,RES 4,(REGISTER+dd) */
            instrDDCB__LD_C_RES_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xa2 => {
            /* LD D,RES 4,(REGISTER+dd) */
            instrDDCB__LD_D_RES_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xa3 => {
            /* LD E,RES 4,(REGISTER+dd) */
            instrDDCB__LD_E_RES_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xa4 => {
            /* LD H,RES 4,(REGISTER+dd) */
            instrDDCB__LD_H_RES_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xa5 => {
            /* LD L,RES 4,(REGISTER+dd) */
            instrDDCB__LD_L_RES_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xa6 => {
            /* RES 4,(REGISTER+dd) */
            instrDDCB__RES_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xa7 => {
            /* LD A,RES 4,(REGISTER+dd) */
            instrDDCB__LD_A_RES_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xa8 => {
            /* LD B,RES 5,(REGISTER+dd) */
            instrDDCB__LD_B_RES_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xa9 => {
            /* LD C,RES 5,(REGISTER+dd) */
            instrDDCB__LD_C_RES_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xaa => {
            /* LD D,RES 5,(REGISTER+dd) */
            instrDDCB__LD_D_RES_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xab => {
            /* LD E,RES 5,(REGISTER+dd) */
            instrDDCB__LD_E_RES_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xac => {
            /* LD H,RES 5,(REGISTER+dd) */
            instrDDCB__LD_H_RES_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xad => {
            /* LD L,RES 5,(REGISTER+dd) */
            instrDDCB__LD_L_RES_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xae => {
            /* RES 5,(REGISTER+dd) */
            instrDDCB__RES_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xaf => {
            /* LD A,RES 5,(REGISTER+dd) */
            instrDDCB__LD_A_RES_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xb0 => {
            /* LD B,RES 6,(REGISTER+dd) */
            instrDDCB__LD_B_RES_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xb1 => {
            /* LD C,RES 6,(REGISTER+dd) */
            instrDDCB__LD_C_RES_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xb2 => {
            /* LD D,RES 6,(REGISTER+dd) */
            instrDDCB__LD_D_RES_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xb3 => {
            /* LD E,RES 6,(REGISTER+dd) */
            instrDDCB__LD_E_RES_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xb4 => {
            /* LD H,RES 6,(REGISTER+dd) */
            instrDDCB__LD_H_RES_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xb5 => {
            /* LD L,RES 6,(REGISTER+dd) */
            instrDDCB__LD_L_RES_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xb6 => {
            /* RES 6,(REGISTER+dd) */
            instrDDCB__RES_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xb7 => {
            /* LD A,RES 6,(REGISTER+dd) */
            instrDDCB__LD_A_RES_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xb8 => {
            /* LD B,RES 7,(REGISTER+dd) */
            instrDDCB__LD_B_RES_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xb9 => {
            /* LD C,RES 7,(REGISTER+dd) */
            instrDDCB__LD_C_RES_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xba => {
            /* LD D,RES 7,(REGISTER+dd) */
            instrDDCB__LD_D_RES_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xbb => {
            /* LD E,RES 7,(REGISTER+dd) */
            instrDDCB__LD_E_RES_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xbc => {
            /* LD H,RES 7,(REGISTER+dd) */
            instrDDCB__LD_H_RES_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xbd => {
            /* LD L,RES 7,(REGISTER+dd) */
            instrDDCB__LD_L_RES_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xbe => {
            /* RES 7,(REGISTER+dd) */
            instrDDCB__RES_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xbf => {
            /* LD A,RES 7,(REGISTER+dd) */
            instrDDCB__LD_A_RES_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xc0 => {
            /* LD B,SET 0,(REGISTER+dd) */
            instrDDCB__LD_B_SET_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xc1 => {
            /* LD C,SET 0,(REGISTER+dd) */
            instrDDCB__LD_C_SET_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xc2 => {
            /* LD D,SET 0,(REGISTER+dd) */
            instrDDCB__LD_D_SET_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xc3 => {
            /* LD E,SET 0,(REGISTER+dd) */
            instrDDCB__LD_E_SET_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xc4 => {
            /* LD H,SET 0,(REGISTER+dd) */
            instrDDCB__LD_H_SET_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xc5 => {
            /* LD L,SET 0,(REGISTER+dd) */
            instrDDCB__LD_L_SET_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xc6 => {
            /* SET 0,(REGISTER+dd) */
            instrDDCB__SET_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xc7 => {
            /* LD A,SET 0,(REGISTER+dd) */
            instrDDCB__LD_A_SET_0_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xc8 => {
            /* LD B,SET 1,(REGISTER+dd) */
            instrDDCB__LD_B_SET_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xc9 => {
            /* LD C,SET 1,(REGISTER+dd) */
            instrDDCB__LD_C_SET_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xca => {
            /* LD D,SET 1,(REGISTER+dd) */
            instrDDCB__LD_D_SET_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xcb => {
            /* LD E,SET 1,(REGISTER+dd) */
            instrDDCB__LD_E_SET_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xcc => {
            /* LD H,SET 1,(REGISTER+dd) */
            instrDDCB__LD_H_SET_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xcd => {
            /* LD L,SET 1,(REGISTER+dd) */
            instrDDCB__LD_L_SET_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xce => {
            /* SET 1,(REGISTER+dd) */
            instrDDCB__SET_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xcf => {
            /* LD A,SET 1,(REGISTER+dd) */
            instrDDCB__LD_A_SET_1_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xd0 => {
            /* LD B,SET 2,(REGISTER+dd) */
            instrDDCB__LD_B_SET_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xd1 => {
            /* LD C,SET 2,(REGISTER+dd) */
            instrDDCB__LD_C_SET_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xd2 => {
            /* LD D,SET 2,(REGISTER+dd) */
            instrDDCB__LD_D_SET_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xd3 => {
            /* LD E,SET 2,(REGISTER+dd) */
            instrDDCB__LD_E_SET_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xd4 => {
            /* LD H,SET 2,(REGISTER+dd) */
            instrDDCB__LD_H_SET_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xd5 => {
            /* LD L,SET 2,(REGISTER+dd) */
            instrDDCB__LD_L_SET_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xd6 => {
            /* SET 2,(REGISTER+dd) */
            instrDDCB__SET_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xd7 => {
            /* LD A,SET 2,(REGISTER+dd) */
            instrDDCB__LD_A_SET_2_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xd8 => {
            /* LD B,SET 3,(REGISTER+dd) */
            instrDDCB__LD_B_SET_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xd9 => {
            /* LD C,SET 3,(REGISTER+dd) */
            instrDDCB__LD_C_SET_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xda => {
            /* LD D,SET 3,(REGISTER+dd) */
            instrDDCB__LD_D_SET_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xdb => {
            /* LD E,SET 3,(REGISTER+dd) */
            instrDDCB__LD_E_SET_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xdc => {
            /* LD H,SET 3,(REGISTER+dd) */
            instrDDCB__LD_H_SET_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xdd => {
            /* LD L,SET 3,(REGISTER+dd) */
            instrDDCB__LD_L_SET_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xde => {
            /* SET 3,(REGISTER+dd) */
            instrDDCB__SET_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xdf => {
            /* LD A,SET 3,(REGISTER+dd) */
            instrDDCB__LD_A_SET_3_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xe0 => {
            /* LD B,SET 4,(REGISTER+dd) */
            instrDDCB__LD_B_SET_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xe1 => {
            /* LD C,SET 4,(REGISTER+dd) */
            instrDDCB__LD_C_SET_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xe2 => {
            /* LD D,SET 4,(REGISTER+dd) */
            instrDDCB__LD_D_SET_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xe3 => {
            /* LD E,SET 4,(REGISTER+dd) */
            instrDDCB__LD_E_SET_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xe4 => {
            /* LD H,SET 4,(REGISTER+dd) */
            instrDDCB__LD_H_SET_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xe5 => {
            /* LD L,SET 4,(REGISTER+dd) */
            instrDDCB__LD_L_SET_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xe6 => {
            /* SET 4,(REGISTER+dd) */
            instrDDCB__SET_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xe7 => {
            /* LD A,SET 4,(REGISTER+dd) */
            instrDDCB__LD_A_SET_4_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xe8 => {
            /* LD B,SET 5,(REGISTER+dd) */
            instrDDCB__LD_B_SET_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xe9 => {
            /* LD C,SET 5,(REGISTER+dd) */
            instrDDCB__LD_C_SET_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xea => {
            /* LD D,SET 5,(REGISTER+dd) */
            instrDDCB__LD_D_SET_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xeb => {
            /* LD E,SET 5,(REGISTER+dd) */
            instrDDCB__LD_E_SET_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xec => {
            /* LD H,SET 5,(REGISTER+dd) */
            instrDDCB__LD_H_SET_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xed => {
            /* LD L,SET 5,(REGISTER+dd) */
            instrDDCB__LD_L_SET_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xee => {
            /* SET 5,(REGISTER+dd) */
            instrDDCB__SET_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xef => {
            /* LD A,SET 5,(REGISTER+dd) */
            instrDDCB__LD_A_SET_5_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xf0 => {
            /* LD B,SET 6,(REGISTER+dd) */
            instrDDCB__LD_B_SET_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xf1 => {
            /* LD C,SET 6,(REGISTER+dd) */
            instrDDCB__LD_C_SET_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xf2 => {
            /* LD D,SET 6,(REGISTER+dd) */
            instrDDCB__LD_D_SET_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xf3 => {
            /* LD E,SET 6,(REGISTER+dd) */
            instrDDCB__LD_E_SET_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xf4 => {
            /* LD H,SET 6,(REGISTER+dd) */
            instrDDCB__LD_H_SET_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xf5 => {
            /* LD L,SET 6,(REGISTER+dd) */
            instrDDCB__LD_L_SET_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xf6 => {
            /* SET 6,(REGISTER+dd) */
            instrDDCB__SET_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xf7 => {
            /* LD A,SET 6,(REGISTER+dd) */
            instrDDCB__LD_A_SET_6_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xf8 => {
            /* LD B,SET 7,(REGISTER+dd) */
            instrDDCB__LD_B_SET_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xf9 => {
            /* LD C,SET 7,(REGISTER+dd) */
            instrDDCB__LD_C_SET_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xfa => {
            /* LD D,SET 7,(REGISTER+dd) */
            instrDDCB__LD_D_SET_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xfb => {
            /* LD E,SET 7,(REGISTER+dd) */
            instrDDCB__LD_E_SET_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xfc => {
            /* LD H,SET 7,(REGISTER+dd) */
            instrDDCB__LD_H_SET_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xfd => {
            /* LD L,SET 7,(REGISTER+dd) */
            instrDDCB__LD_L_SET_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xfe => {
            /* SET 7,(REGISTER+dd) */
            instrDDCB__SET_7_iREGpDD(data, memory);
            true
        }

        val if val == SHIFT_0X_DDCB + 0xff => {
            /* LD A,SET 7,(REGISTER+dd) */
            instrDDCB__LD_A_SET_7_iREGpDD(data, memory);
            true
        }
        _ => false,
    }
}
/* NOP */
pub fn instr__NOP() {}
/* LD BC,nnnn */
fn_instr_ld_r16_nnnn!(instr__LD_BC_NNNN, BC, set_bc);

/* LD (BC),A */
pub fn instr__LD_iBC_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.bc();
    memory.write_byte(address, data.A);
}

/* INC BC */
fn_instr_op_16!(instr__INC_BC, inc_bc);

/* INC B */
fn_instr_op_8!(instr__INC_B, inc_b);

/* DEC B */
fn_instr_op_8!(instr__DEC_B, dec_b);

/* LD B,nn */
fn_instr_ld_r8_nn!(instr__LD_B_NN, B);

/* RLCA */
pub fn instr__RLCA(data: &mut Z80Data) {
    data.A = data.A.rotate_left(1);
    data.F = (data.F & (FLAG_P | FLAG_Z | FLAG_S)) | (data.A & (FLAG_C | FLAG_3 | FLAG_5));
}

/* EX AF,AF' */
pub fn instr__EX_AF_AF(data: &mut Z80Data) {
    let old_a: u8 = data.A;
    let old_f: u8 = data.F;
    data.A = data.A_;
    data.F = data.F_;
    data.A_ = old_a;
    data.F_ = old_f;
}

/* ADD HL,BC */
fn_instr_add_hl_r16!(instr__ADD_HL_BC, bc);

/* LD A,(BC) */
fn_instr_ld_a_r16!(instr__LD_A_iBC, bc);

/* DEC BC */
fn_instr_op_16!(instr__DEC_BC, dec_bc);

/* INC C */
fn_instr_op_8!(instr__INC_C, inc_c);

/* DEC C */
fn_instr_op_8!(instr__DEC_C, dec_c);

/* LD C,nn */
fn_instr_ld_r8_nn!(instr__LD_C_NN, C);

/* RRCA */
pub fn instr__RRCA(data: &mut Z80Data) {
    data.F = (data.F & (FLAG_P | FLAG_Z | FLAG_S)) | (data.A & FLAG_C);
    data.A = data.A.rotate_right(1);
    data.F |= data.A & (FLAG_3 | FLAG_5);
}

/* DJNZ offset */
pub fn instr__DJNZ_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    data.B = data.B.wrapping_sub(1);
    if data.B != 0 {
        jr(data, memory);
        data.cycles += 14;
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        data.cycles += 9;
    }
    data.inc_pc(1);
}

/* LD DE,nnnn */
fn_instr_ld_r16_nnnn!(instr__LD_DE_NNNN, DE, set_de);

/* LD (DE),A */
fn_instr_ld_i_r16_r8!(instr__LD_iDE_A, de, A);

/* INC DE */
fn_instr_op_16!(instr__INC_DE, inc_de);

/* INC D */
fn_instr_op_8!(instr__INC_D, inc_d);

/* DEC D */
fn_instr_op_8!(instr__DEC_D, dec_d);

/* LD D,nn */
fn_instr_ld_r8_nn!(instr__LD_D_NN, D);

/* RLA */
pub fn instr__RLA(data: &mut Z80Data) {
    let byte_temp: u8 = data.A;
    data.A = (data.A << 1) | data.F & FLAG_C;
    data.F =
        (data.F & (FLAG_P | FLAG_Z | FLAG_S)) | (data.A & (FLAG_3 | FLAG_5)) | (byte_temp >> 7);
}

/* JR offset */
pub fn instr__JR_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    jr(data, memory);
    data.inc_pc(1);
}

/* ADD HL,DE */
fn_instr_add_hl_r16!(instr__ADD_HL_DE, de);

/* LD A,(DE) */
fn_instr_ld_a_r16!(instr__LD_A_iDE, de);

/* DEC DE */
fn_instr_op_16!(instr__DEC_DE, dec_de);

/* INC E */
fn_instr_op_8!(instr__INC_E, inc_e);

/* DEC E */
fn_instr_op_8!(instr__DEC_E, dec_e);

/* LD E,nn */
fn_instr_ld_r8_nn!(instr__LD_E_NN, E);

/* RRA */
pub fn instr__RRA(data: &mut Z80Data) {
    let byte_temp: u8 = data.A;
    data.A = (data.A >> 1) | (data.F << 7);
    data.F = data.F & (FLAG_P | FLAG_Z | FLAG_S) | data.A & (FLAG_3 | FLAG_5) | byte_temp & FLAG_C;
}

/* JR NZ,offset */
pub fn instr__JR_NZ_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    if (data.F & FLAG_Z) == 0 {
        jr(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
    }
    data.inc_pc(1);
}

/* LD HL,nnnn */
fn_instr_ld_r16_nnnn!(instr__LD_HL_NNNN, HL, set_hl);

/* LD (nnnn),HL */
fn_instr_ld_i_nnnn_r16!(instr__LD_iNNNN_HL, L, H);

/* INC HL */
fn_instr_op_16!(instr__INC_HL, inc_hl);

/* INC H */
fn_instr_op_8!(instr__INC_H, inc_h);

/* DEC H */
fn_instr_op_8!(instr__DEC_H, dec_h);

/* LD H,nn */
fn_instr_ld_r8_nn!(instr__LD_H_NN, H);

/* DAA */
pub fn instr__DAA(data: &mut Z80Data) {
    let mut add: u8 = 0;
    let mut carry: u8 = data.F & FLAG_C;
    if ((data.F & FLAG_H) != 0) || ((data.A & 0x0f) > 9) {
        add = 6;
    }
    if (carry != 0) || (data.A > 0x99) {
        add |= 0x60;
    }
    if data.A > 0x99 {
        carry = FLAG_C;
    }
    if (data.F & FLAG_N) != 0 {
        sub(data, add);
    } else {
        super::api::add(data, add);
    }
    let temp: u8 =
        data.F & !(FLAG_C | FLAG_P) | carry | z80_tables::get().parity_table[data.A as usize];
    data.F = temp;
}

/* JR Z,offset */
pub fn instr__JR_Z_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    if (data.F & FLAG_Z) != 0 {
        jr(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
    }
    data.inc_pc(1);
}

/* ADD HL,HL */
fn_instr_add_hl_r16!(instr__ADD_HL_HL, hl);

/* LD HL,(nnnn) */
fn_instr_ld_hl_i_nnnn!(instr__LD_HL_iNNNN, L, H);

/* DEC HL */
fn_instr_op_16!(instr__DEC_HL, dec_hl);

/* INC L */
fn_instr_op_8!(instr__INC_L, inc_l);

/* DEC L */
fn_instr_op_8!(instr__DEC_L, dec_l);

/* LD L,nn */
fn_instr_ld_r8_nn!(instr__LD_L_NN, L);

/* CPL */
pub fn instr__CPL(data: &mut Z80Data) {
    data.A ^= 0xff;
    data.F = data.F & (FLAG_C | FLAG_P | FLAG_Z | FLAG_S)
        | data.A & (FLAG_3 | FLAG_5)
        | (FLAG_N | FLAG_H);
}

/* JR NC,offset */
pub fn instr__JR_NC_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    if data.F & FLAG_C == 0 {
        jr(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
    }
    data.inc_pc(1);
}

/* LD SP,nnnn */
fn_instr_ld_r16_nnnn!(instr__LD_SP_NNNN, SP, set_sp);

/* LD (nnnn),A */
pub fn instr__LD_iNNNN_A(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let mut word_temp: u16 = (memory.read_byte(address)) as u16;
    data.inc_pc(1);
    let address = data.pc();
    word_temp |= (memory.read_byte(address) as u16) << 8;
    data.inc_pc(1);
    memory.write_byte(word_temp, data.A);
}

/* INC SP */
fn_instr_op_16!(instr__INC_SP, inc_sp);

/* INC (HL) */
pub fn instr__INC_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    inc(data, &mut byte_temp);
    memory.write_byte(data.hl(), byte_temp);
}

/* DEC (HL) */
pub fn instr__DEC_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.hl();
    let mut byte_temp: u8 = memory.read_byte(address);
    let _address = data.hl();
    memory.contend_read_no_mreq(_address, 1);
    dec(data, &mut byte_temp);
    memory.write_byte(data.hl(), byte_temp);
}

/* LD (HL),nn */
pub fn instr__LD_iHL_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let value = memory.read_byte(address);
    let address = data.hl();
    memory.write_byte(address, value);
    data.inc_pc(1);
}

/* SCF */
pub fn instr__SCF(data: &mut Z80Data) {
    data.F = (data.F & (FLAG_P | FLAG_Z | FLAG_S)) | (data.A & (FLAG_3 | FLAG_5)) | FLAG_C;
}

/* JR C,offset */
pub fn instr__JR_C_OFFSET(data: &mut Z80Data, memory: &mut Memory) {
    if data.F & FLAG_C != 0 {
        jr(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
    }
    data.inc_pc(1);
}

/* ADD HL,SP */
fn_instr_add_hl_r16!(instr__ADD_HL_SP, sp);

/* LD A,(nnnn) */
pub fn instr__LD_A_iNNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let mut word_temp: u16 = memory.read_byte(address) as u16;
    data.inc_pc(1);
    let address = data.pc();
    word_temp |= (memory.read_byte(address) as u16) << 8;
    data.inc_pc(1);
    data.A = memory.read_byte(word_temp);
}

/* DEC SP */
fn_instr_op_16!(instr__DEC_SP, dec_sp);

/* INC A */
fn_instr_op_8!(instr__INC_A, inc_a);

/* DEC A */
fn_instr_op_8!(instr__DEC_A, dec_a);

/* LD A,nn */
fn_instr_ld_r8_nn!(instr__LD_A_NN, A);

/* CCF */
pub fn instr__CCF(data: &mut Z80Data) {
    data.F = data.F & (FLAG_P | FLAG_Z | FLAG_S)
        | tern_op_b(data.F & FLAG_C != 0, FLAG_H, FLAG_C)
        | data.A & (FLAG_3 | FLAG_5);
}

/* LD B,B */
pub fn instr__LD_B_B() {}

/* LD B,C */
pub fn instr__LD_B_C(data: &mut Z80Data) {
    data.B = data.C;
}

/* LD B,D */
pub fn instr__LD_B_D(data: &mut Z80Data) {
    data.B = data.D;
}

/* LD B,E */
pub fn instr__LD_B_E(data: &mut Z80Data) {
    data.B = data.E;
}

/* LD B,H */
pub fn instr__LD_B_H(data: &mut Z80Data) {
    data.B = data.H;
}

/* LD B,L */
pub fn instr__LD_B_L(data: &mut Z80Data) {
    data.B = data.L;
}

/* LD B,(HL) */
pub fn instr__LD_B_iHL(data: &mut Z80Data, memory: &mut Memory) {
    data.B = memory.read_byte(data.hl());
}

/* LD B,A */
pub fn instr__LD_B_A(data: &mut Z80Data) {
    data.B = data.A;
}

/* LD C,B */
pub fn instr__LD_C_B(data: &mut Z80Data) {
    data.C = data.B;
}

/* LD C,C */
pub fn instr__LD_C_C() {}

/* LD C,D */
pub fn instr__LD_C_D(data: &mut Z80Data) {
    data.C = data.D;
}

/* LD C,E */
pub fn instr__LD_C_E(data: &mut Z80Data) {
    data.C = data.E;
}

/* LD C,H */
pub fn instr__LD_C_H(data: &mut Z80Data) {
    data.C = data.H;
}

/* LD C,L */
pub fn instr__LD_C_L(data: &mut Z80Data) {
    data.C = data.L;
}

/* LD C,(HL) */
pub fn instr__LD_C_iHL(data: &mut Z80Data, memory: &mut Memory) {
    data.C = memory.read_byte(data.hl());
}

/* LD C,A */
pub fn instr__LD_C_A(data: &mut Z80Data) {
    data.C = data.A;
}

/* LD D,B */
pub fn instr__LD_D_B(data: &mut Z80Data) {
    data.D = data.B;
}

/* LD D,C */
pub fn instr__LD_D_C(data: &mut Z80Data) {
    data.D = data.C;
}

/* LD D,D */
pub fn instr__LD_D_D() {}

/* LD D,E */
pub fn instr__LD_D_E(data: &mut Z80Data) {
    data.D = data.E;
}

/* LD D,H */
pub fn instr__LD_D_H(data: &mut Z80Data) {
    data.D = data.H;
}

/* LD D,L */
pub fn instr__LD_D_L(data: &mut Z80Data) {
    data.D = data.L;
}

/* LD D,(HL) */
pub fn instr__LD_D_iHL(data: &mut Z80Data, memory: &mut Memory) {
    data.D = memory.read_byte(data.hl());
}

/* LD D,A */
pub fn instr__LD_D_A(data: &mut Z80Data) {
    data.D = data.A;
}

/* LD E,B */
pub fn instr__LD_E_B(data: &mut Z80Data) {
    data.E = data.B;
}

/* LD E,C */
pub fn instr__LD_E_C(data: &mut Z80Data) {
    data.E = data.C;
}

/* LD E,D */
pub fn instr__LD_E_D(data: &mut Z80Data) {
    data.E = data.D;
}

/* LD E,E */
pub fn instr__LD_E_E() {}

/* LD E,H */
pub fn instr__LD_E_H(data: &mut Z80Data) {
    data.E = data.H;
}

/* LD E,L */
pub fn instr__LD_E_L(data: &mut Z80Data) {
    data.E = data.L;
}

/* LD E,(HL) */
pub fn instr__LD_E_iHL(data: &mut Z80Data, memory: &mut Memory) {
    data.E = memory.read_byte(data.hl());
}

/* LD E,A */
pub fn instr__LD_E_A(data: &mut Z80Data) {
    data.E = data.A;
}

/* LD H,B */
pub fn instr__LD_H_B(data: &mut Z80Data) {
    data.H = data.B;
}

/* LD H,C */
pub fn instr__LD_H_C(data: &mut Z80Data) {
    data.H = data.C;
}

/* LD H,D */
pub fn instr__LD_H_D(data: &mut Z80Data) {
    data.H = data.D;
}

/* LD H,E */
pub fn instr__LD_H_E(data: &mut Z80Data) {
    data.H = data.E;
}

/* LD H,H */
pub fn instr__LD_H_H() {}

/* LD H,L */
pub fn instr__LD_H_L(data: &mut Z80Data) {
    data.H = data.L;
}

/* LD H,(HL) */
pub fn instr__LD_H_iHL(data: &mut Z80Data, memory: &mut Memory) {
    data.H = memory.read_byte(data.hl());
}

/* LD H,A */
pub fn instr__LD_H_A(data: &mut Z80Data) {
    data.H = data.A;
}

/* LD L,B */
pub fn instr__LD_L_B(data: &mut Z80Data) {
    data.L = data.B;
}

/* LD L,C */
pub fn instr__LD_L_C(data: &mut Z80Data) {
    data.L = data.C;
}

/* LD L,D */
pub fn instr__LD_L_D(data: &mut Z80Data) {
    data.L = data.D;
}

/* LD L,E */
pub fn instr__LD_L_E(data: &mut Z80Data) {
    data.L = data.E;
}

/* LD L,H */
pub fn instr__LD_L_H(data: &mut Z80Data) {
    data.L = data.H;
}

/* LD L,L */
pub fn instr__LD_L_L() {}

/* LD L,(HL) */
pub fn instr__LD_L_iHL(data: &mut Z80Data, memory: &mut Memory) {
    data.L = memory.read_byte(data.hl());
}

/* LD L,A */
pub fn instr__LD_L_A(data: &mut Z80Data) {
    data.L = data.A;
}

/* LD (HL),B */
fn_instr_ld_i_r16_r8!(instr__LD_iHL_B, hl, B);

/* LD (HL),C */
fn_instr_ld_i_r16_r8!(instr__LD_iHL_C, hl, C);

/* LD (HL),D */
fn_instr_ld_i_r16_r8!(instr__LD_iHL_D, hl, D);

/* LD (HL),E */
fn_instr_ld_i_r16_r8!(instr__LD_iHL_E, hl, E);

/* LD (HL),H */
fn_instr_ld_i_r16_r8!(instr__LD_iHL_H, hl, H);

/* LD (HL),L */
fn_instr_ld_i_r16_r8!(instr__LD_iHL_L, hl, L);

/* HALT */
pub fn instr__HALT(data: &mut Z80Data) {
    data.halted = true;
    data.dec_pc(1);
}

/* LD (HL),A */
fn_instr_ld_i_r16_r8!(instr__LD_iHL_A, hl, A);

/* LD A,B */
fn_instr_ld_a_r8!(instr__LD_A_B, B);

/* LD A,C */
fn_instr_ld_a_r8!(instr__LD_A_C, C);

/* LD A,D */
fn_instr_ld_a_r8!(instr__LD_A_D, D);

/* LD A,E */
fn_instr_ld_a_r8!(instr__LD_A_E, E);

/* LD A,H */
fn_instr_ld_a_r8!(instr__LD_A_H, H);

/* LD A,L */
fn_instr_ld_a_r8!(instr__LD_A_L, L);

/* LD A,(HL) */
fn_instr_ld_a_r16!(instr__LD_A_iHL, hl);

/* LD A,A */
pub fn instr__LD_A_A() {}

/* ADD A,B */
fn_instr_add_r8!(instr__ADD_A_B, B);

/* ADD A,C */
fn_instr_add_r8!(instr__ADD_A_C, C);

/* ADD A,D */
fn_instr_add_r8!(instr__ADD_A_D, D);

/* ADD A,E */
fn_instr_add_r8!(instr__ADD_A_E, E);

/* ADD A,H */
fn_instr_add_r8!(instr__ADD_A_H, H);

/* ADD A,L */
fn_instr_add_r8!(instr__ADD_A_L, L);

/* ADD A,(HL) */
pub fn instr__ADD_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());

    add(data, byte_temp);
}

/* ADD A,A */
fn_instr_add_r8!(instr__ADD_A_A, A);

/* ADC A,B */
fn_instr_adc_r8!(instr__ADC_A_B, B);

/* ADC A,C */
fn_instr_adc_r8!(instr__ADC_A_C, C);

/* ADC A,D */
fn_instr_adc_r8!(instr__ADC_A_D, D);

/* ADC A,E */
fn_instr_adc_r8!(instr__ADC_A_E, E);

/* ADC A,H */
fn_instr_adc_r8!(instr__ADC_A_H, H);

/* ADC A,L */
fn_instr_adc_r8!(instr__ADC_A_L, L);

/* ADC A,(HL) */
pub fn instr__ADC_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());

    adc(data, byte_temp);
}

/* ADC A,A */
fn_instr_adc_r8!(instr__ADC_A_A, A);

/* SUB A,B */
fn_instr_sub_r8!(instr__SUB_A_B, B);

/* SUB A,C */
fn_instr_sub_r8!(instr__SUB_A_C, C);

/* SUB A,D */
fn_instr_sub_r8!(instr__SUB_A_D, D);

/* SUB A,E */
fn_instr_sub_r8!(instr__SUB_A_E, E);

/* SUB A,H */
fn_instr_sub_r8!(instr__SUB_A_H, H);

/* SUB A,L */
fn_instr_sub_r8!(instr__SUB_A_L, L);

/* SUB A,(HL) */
pub fn instr__SUB_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());

    sub(data, byte_temp);
}

/* SUB A,A */
fn_instr_sub_r8!(instr__SUB_A_A, A);

/* SBC A,B */
fn_instr_sbc_r8!(instr__SBC_A_B, B);

/* SBC A,C */
fn_instr_sbc_r8!(instr__SBC_A_C, C);

/* SBC A,D */
fn_instr_sbc_r8!(instr__SBC_A_D, D);

/* SBC A,E */
fn_instr_sbc_r8!(instr__SBC_A_E, E);

/* SBC A,H */
fn_instr_sbc_r8!(instr__SBC_A_H, H);

/* SBC A,L */
fn_instr_sbc_r8!(instr__SBC_A_L, L);

/* SBC A,(HL) */
pub fn instr__SBC_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());

    sbc(data, byte_temp);
}

/* SBC A,A */
fn_instr_sbc_r8!(instr__SBC_A_A, A);

/* AND A,B */
fn_instr_and_r8!(instr__AND_A_B, B);

/* AND A,C */
fn_instr_and_r8!(instr__AND_A_C, C);

/* AND A,D */
fn_instr_and_r8!(instr__AND_A_D, D);

/* AND A,E */
fn_instr_and_r8!(instr__AND_A_E, E);

/* AND A,H */
fn_instr_and_r8!(instr__AND_A_H, H);

/* AND A,L */
fn_instr_and_r8!(instr__AND_A_L, L);

/* AND A,(HL) */
pub fn instr__AND_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());

    and(data, byte_temp);
}

/* AND A,A */
fn_instr_and_r8!(instr__AND_A_A, A);

/* XOR A,B */
fn_instr_xor_r8!(instr__XOR_A_B, B);

/* XOR A,C */
fn_instr_xor_r8!(instr__XOR_A_C, C);

/* XOR A,D */
fn_instr_xor_r8!(instr__XOR_A_D, D);

/* XOR A,E */
fn_instr_xor_r8!(instr__XOR_A_E, E);

/* XOR A,H */
fn_instr_xor_r8!(instr__XOR_A_H, H);

/* XOR A,L */
fn_instr_xor_r8!(instr__XOR_A_L, L);

/* XOR A,(HL) */
pub fn instr__XOR_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());

    xor(data, byte_temp);
}

/* XOR A,A */
fn_instr_xor_r8!(instr__XOR_A_A, A);

/* OR A,B */
fn_instr_or_r8!(instr__OR_A_B, B);

/* OR A,C */
fn_instr_or_r8!(instr__OR_A_C, C);

/* OR A,D */
fn_instr_or_r8!(instr__OR_A_D, D);

/* OR A,E */
fn_instr_or_r8!(instr__OR_A_E, E);

/* OR A,H */
fn_instr_or_r8!(instr__OR_A_H, H);

/* OR A,L */
fn_instr_or_r8!(instr__OR_A_L, L);

/* OR A,(HL) */
pub fn instr__OR_A_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());

    or(data, byte_temp);
}

/* OR A,A */
fn_instr_or_r8!(instr__OR_A_A, A);

/* CP B */
fn_instr_cp_r8!(instr__CP_B, B);

/* CP C */
fn_instr_cp_r8!(instr__CP_C, C);

/* CP D */
fn_instr_cp_r8!(instr__CP_D, D);

/* CP E */
fn_instr_cp_r8!(instr__CP_E, E);

/* CP H */
fn_instr_cp_r8!(instr__CP_H, H);

/* CP L */
fn_instr_cp_r8!(instr__CP_L, L);

/* CP (HL) */
pub fn instr__CP_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.hl();
    let byte_temp: u8 = memory.read_byte(address);

    cp(data, byte_temp);
}

/* CP A */
fn_instr_cp_r8!(instr__CP_A, A);

/* RET NZ */
pub fn instr__RET_NZ(data: &mut Z80Data, memory: &mut Memory, hook: Rc<RefCell<dyn FuncHook>>) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    if (data.F & FLAG_Z) == 0 {
        ret(data, memory, hook);
    }
}

/* POP BC */
fn_instr_pop_r16!(instr__POP_BC, C, B);

/* JP NZ,nnnn */
pub fn instr__JP_NZ_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    if (data.F & FLAG_Z) == 0 {
        jp(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* JP nnnn */
pub fn instr__JP_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    jp(data, memory);
}

/* CALL NZ,nnnn */
pub fn instr__CALL_NZ_NNNN(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
) {
    if (data.F & FLAG_Z) == 0 {
        call(data, memory, ports, hook);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* PUSH BC */
fn_instr_push_r16!(instr__PUSH_BC, C, B);

/* ADD A,nn */
pub fn instr__ADD_A_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let byte_temp: u8 = memory.read_byte(address);
    data.inc_pc(1);
    add(data, byte_temp);
}

/* RST 00 */
pub fn instr__RST_00(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    rst(data, memory, 0x00);
}

/* RET Z */
pub fn instr__RET_Z(data: &mut Z80Data, memory: &mut Memory, hook: Rc<RefCell<dyn FuncHook>>) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    if (data.F & FLAG_Z) != 0 {
        ret(data, memory, hook);
    }
}

/* RET */
pub fn instr__RET(data: &mut Z80Data, memory: &mut Memory, hook: Rc<RefCell<dyn FuncHook>>) {
    ret(data, memory, hook);
}

/* JP Z,nnnn */
pub fn instr__JP_Z_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    if (data.F & FLAG_Z) != 0 {
        jp(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* shift CB */
pub fn instr__SHIFT_CB(_data: &mut Z80Data, _memory: &mut Memory) {}

/* CALL Z,nnnn */
pub fn instr__CALL_Z_NNNN(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
) {
    if (data.F & FLAG_Z) != 0 {
        call(data, memory, ports, hook);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* CALL nnnn */
pub fn instr__CALL_NNNN(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
) {
    call(data, memory, ports, hook);
}

/* ADC A,nn */
pub fn instr__ADC_A_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let byte_temp: u8 = memory.read_byte(address);
    data.inc_pc(1);
    adc(data, byte_temp);
}

/* RST 8 */
pub fn instr__RST_8(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    rst(data, memory, 0x8);
}

/* RET NC */
pub fn instr__RET_NC(data: &mut Z80Data, memory: &mut Memory, hook: Rc<RefCell<dyn FuncHook>>) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    if data.F & FLAG_C == 0 {
        ret(data, memory, hook);
    }
}

/* POP DE */
fn_instr_pop_r16!(instr__POP_DE, E, D);

/* JP NC,nnnn */
pub fn instr__JP_NC_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    if data.F & FLAG_C == 0 {
        jp(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* OUT (nn),A */
pub fn instr__OUT_iNN_A(data: &mut Z80Data, memory: &mut Memory, ports: &mut Ports) {
    let address = data.pc();
    let out_temp: u16 = (memory.read_byte(address) as u16) + ((data.A as u16) << 8);
    data.inc_pc(1);
    ports.write_port(out_temp, data.A);
}

/* CALL NC,nnnn */
pub fn instr__CALL_NC_NNNN(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
) {
    if data.F & FLAG_C == 0 {
        call(data, memory, ports, hook);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* PUSH DE */
fn_instr_push_r16!(instr__PUSH_DE, E, D);

/* SUB nn */
pub fn instr__SUB_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let byte_temp: u8 = memory.read_byte(address);
    data.inc_pc(1);
    sub(data, byte_temp);
}

/* RST 10 */
pub fn instr__RST_10(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    rst(data, memory, 0x10);
}

/* RET C */
pub fn instr__RET_C(data: &mut Z80Data, memory: &mut Memory, hook: Rc<RefCell<dyn FuncHook>>) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    if data.F & FLAG_C != 0 {
        ret(data, memory, hook);
    }
}

/* EXX */
pub fn instr__EXX(data: &mut Z80Data) {
    let word_temp: u16 = data.bc();
    data.set_bc(data.bc_());
    data.set_bc_(word_temp);

    let word_temp = data.de();
    data.set_de(data.de_());
    data.set_de_(word_temp);

    let word_temp = data.hl();
    data.set_hl(data.hl_());
    data.set_hl_(word_temp);
}

/* JP C,nnnn */
pub fn instr__JP_C_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    if data.F & FLAG_C != 0 {
        jp(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* IN A,(nn) */
pub fn instr__IN_A_iNN(data: &mut Z80Data, memory: &mut Memory, ports: &mut Ports) {
    let address = data.pc();
    let in_temp: u16 = (memory.read_byte(address) as u16) + ((data.A as u16) << 8);
    data.inc_pc(1);
    data.A = ports.read_port(in_temp);
}

/* CALL C,nnnn */
pub fn instr__CALL_C_NNNN(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
) {
    if data.F & FLAG_C != 0 {
        call(data, memory, ports, hook);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* shift DD */
pub fn instr__SHIFT_DD(_data: &mut Z80Data, _memory: &mut Memory) {}

/* SBC A,nn */
pub fn instr__SBC_A_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let byte_temp: u8 = memory.read_byte(address);
    data.inc_pc(1);
    sbc(data, byte_temp);
}

/* RST 18 */
pub fn instr__RST_18(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    rst(data, memory, 0x18);
}

/* RET PO */
pub fn instr__RET_PO(data: &mut Z80Data, memory: &mut Memory, hook: Rc<RefCell<dyn FuncHook>>) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    if (data.F & FLAG_P) == 0 {
        ret(data, memory, hook);
    }
}

/* POP HL */
fn_instr_pop_r16!(instr__POP_HL, L, H);

/* JP PO,nnnn */
pub fn instr__JP_PO_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    if (data.F & FLAG_P) == 0 {
        jp(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* EX (SP),HL */
pub fn instr__EX_iSP_HL(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.sp();
    let byte_temp_l = memory.read_byte(address);
    let sp = data.sp();
    let byte_temp_h = memory.read_byte(sp + 1);
    let sp = data.sp();
    memory.contend_read_no_mreq(sp + 1, 1);
    let sp = data.sp();
    memory.write_byte(sp + 1, data.H);
    let address = data.sp();
    memory.write_byte(address, data.L);
    let _address = data.sp();
    memory.contend_write_no_mreq_loop(_address, 1, 2);
    data.L = byte_temp_l;
    data.H = byte_temp_h;
}

/* CALL PO,nnnn */
pub fn instr__CALL_PO_NNNN(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
) {
    if (data.F & FLAG_P) == 0 {
        call(data, memory, ports, hook);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* PUSH HL */
fn_instr_push_r16!(instr__PUSH_HL, L, H);

/* AND nn */
pub fn instr__AND_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let byte_temp: u8 = memory.read_byte(address);
    data.inc_pc(1);
    and(data, byte_temp);
}

/* RST 20 */
pub fn instr__RST_20(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    rst(data, memory, 0x20);
}

/* RET PE */
pub fn instr__RET_PE(data: &mut Z80Data, memory: &mut Memory, hook: Rc<RefCell<dyn FuncHook>>) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    if (data.F & FLAG_P) != 0 {
        ret(data, memory, hook);
    }
}

/* JP HL */
pub fn instr__JP_HL(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
) {
    // data.SetPC(data.hl());
    jp_hl(data, memory, ports, hook);
    /* NB: NOT INDIRECT! */
}

/* JP PE,nnnn */
pub fn instr__JP_PE_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    if (data.F & FLAG_P) != 0 {
        jp(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* EX DE,HL */
pub fn instr__EX_DE_HL(data: &mut Z80Data) {
    let word_temp: u16 = data.de();
    data.set_de(data.hl());
    data.set_hl(word_temp);
}

/* CALL PE,nnnn */
pub fn instr__CALL_PE_NNNN(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
) {
    if (data.F & FLAG_P) != 0 {
        call(data, memory, ports, hook);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* shift ED */
pub fn instr__SHIFT_ED(_data: &mut Z80Data, _memory: &mut Memory) {}

/* XOR A,nn */
pub fn instr__XOR_A_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let byte_temp: u8 = memory.read_byte(address);
    data.inc_pc(1);
    xor(data, byte_temp);
}

/* RST 28 */
pub fn instr__RST_28(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    rst(data, memory, 0x28);
}

/* RET P */
pub fn instr__RET_P(data: &mut Z80Data, memory: &mut Memory, hook: Rc<RefCell<dyn FuncHook>>) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    if (data.F & FLAG_S) == 0 {
        ret(data, memory, hook);
    }
}

/* POP AF */
fn_instr_pop_r16!(instr__POP_AF, F, A);

/* JP P,nnnn */
pub fn instr__JP_P_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    if (data.F & FLAG_S) == 0 {
        jp(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* DI */
pub fn instr__DI(data: &mut Z80Data) {
    (data.IFF1, data.IFF2) = (0, 0);
}

/* CALL P,nnnn */
pub fn instr__CALL_P_NNNN(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
) {
    if (data.F & FLAG_S) == 0 {
        call(data, memory, ports, hook);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* PUSH AF */
fn_instr_push_r16!(instr__PUSH_AF, F, A);

/* OR nn */
pub fn instr__OR_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let byte_temp: u8 = memory.read_byte(address);
    data.inc_pc(1);
    or(data, byte_temp);
}

/* RST 30 */
pub fn instr__RST_30(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    rst(data, memory, 0x30);
}

/* RET M */
pub fn instr__RET_M(data: &mut Z80Data, memory: &mut Memory, hook: Rc<RefCell<dyn FuncHook>>) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    if (data.F & FLAG_S) != 0 {
        ret(data, memory, hook);
    }
}

/* LD SP,HL */
pub fn instr__LD_SP_HL(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 2);
    data.set_sp(data.hl());
}

/* JP M,nnnn */
pub fn instr__JP_M_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    if (data.F & FLAG_S) != 0 {
        jp(data, memory);
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* EI */
pub fn instr__EI(data: &mut Z80Data) {
    /* Interrupts are not accepted immediately after an EI, but are
    accepted after the next instruction */
    (data.IFF1, data.IFF2) = (1, 1);
    data.interrupts_enabled_at = data.t_states;
    // eventAdd(self.Tstates + 1, z80InterruptEvent)
}

/* CALL M,nnnn */
pub fn instr__CALL_M_NNNN(
    data: &mut Z80Data,
    memory: &mut Memory,
    ports: &mut Ports,
    hook: Rc<RefCell<dyn FuncHook>>,
) {
    if (data.F & FLAG_S) != 0 {
        call(data, memory, ports, hook)
    } else {
        let _address = data.pc();
        memory.contend_read(_address, 3);
        let pc = data.pc();
        memory.contend_read(pc + 1, 3);
        data.inc_pc(2);
    }
}

/* shift FD */
pub fn instr__SHIFT_FD(_data: &mut Z80Data, _memory: &mut Memory) {}

/* CP nn */
pub fn instr__CP_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let byte_temp: u8 = memory.read_byte(address);
    data.inc_pc(1);
    cp(data, byte_temp);
}

/* RST 38 */
pub fn instr__RST_38(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    rst(data, memory, 0x38);
}

/* RLC B */
pub fn instrCB__RLC_B(data: &mut Z80Data) {
    data.B = rlc(data, data.B);
}

/* RLC C */
pub fn instrCB__RLC_C(data: &mut Z80Data) {
    data.C = rlc(data, data.C);
}

/* RLC D */
pub fn instrCB__RLC_D(data: &mut Z80Data) {
    data.D = rlc(data, data.D);
}

/* RLC E */
pub fn instrCB__RLC_E(data: &mut Z80Data) {
    data.E = rlc(data, data.E);
}

/* RLC H */
pub fn instrCB__RLC_H(data: &mut Z80Data) {
    data.H = rlc(data, data.H);
}

/* RLC L */
pub fn instrCB__RLC_L(data: &mut Z80Data) {
    data.L = rlc(data, data.L);
}

/* RLC (HL) */
pub fn instrCB__RLC_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    byte_temp = rlc(data, byte_temp);
    memory.write_byte(data.hl(), byte_temp);
}

/* RLC A */
pub fn instrCB__RLC_A(data: &mut Z80Data) {
    data.A = rlc(data, data.A);
}

/* RRC B */
pub fn instrCB__RRC_B(data: &mut Z80Data) {
    data.B = rrc(data, data.B);
}

/* RRC C */
pub fn instrCB__RRC_C(data: &mut Z80Data) {
    data.C = rrc(data, data.C);
}

/* RRC D */
pub fn instrCB__RRC_D(data: &mut Z80Data) {
    data.D = rrc(data, data.D);
}

/* RRC E */
pub fn instrCB__RRC_E(data: &mut Z80Data) {
    data.E = rrc(data, data.E);
}

/* RRC H */
pub fn instrCB__RRC_H(data: &mut Z80Data) {
    data.H = rrc(data, data.H);
}

/* RRC L */
pub fn instrCB__RRC_L(data: &mut Z80Data) {
    data.L = rrc(data, data.L);
}

/* RRC (HL) */
pub fn instrCB__RRC_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    byte_temp = rrc(data, byte_temp);
    memory.write_byte(data.hl(), byte_temp);
}

/* RRC A */
pub fn instrCB__RRC_A(data: &mut Z80Data) {
    data.A = rrc(data, data.A);
}

/* RL B */
pub fn instrCB__RL_B(data: &mut Z80Data) {
    data.B = rl(data, data.B);
}

/* RL C */
pub fn instrCB__RL_C(data: &mut Z80Data) {
    data.C = rl(data, data.C);
}

/* RL D */
pub fn instrCB__RL_D(data: &mut Z80Data) {
    data.D = rl(data, data.D);
}

/* RL E */
pub fn instrCB__RL_E(data: &mut Z80Data) {
    data.E = rl(data, data.E);
}

/* RL H */
pub fn instrCB__RL_H(data: &mut Z80Data) {
    data.H = rl(data, data.H);
}

/* RL L */
pub fn instrCB__RL_L(data: &mut Z80Data) {
    data.L = rl(data, data.L);
}

/* RL (HL) */
pub fn instrCB__RL_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    byte_temp = rl(data, byte_temp);
    memory.write_byte(data.hl(), byte_temp);
}

/* RL A */
pub fn instrCB__RL_A(data: &mut Z80Data) {
    data.A = rl(data, data.A);
}

/* RR B */
pub fn instrCB__RR_B(data: &mut Z80Data) {
    data.B = rr(data, data.B);
}

/* RR C */
pub fn instrCB__RR_C(data: &mut Z80Data) {
    data.C = rr(data, data.C);
}

/* RR D */
pub fn instrCB__RR_D(data: &mut Z80Data) {
    data.D = rr(data, data.D);
}

/* RR E */
pub fn instrCB__RR_E(data: &mut Z80Data) {
    data.E = rr(data, data.E);
}

/* RR H */
pub fn instrCB__RR_H(data: &mut Z80Data) {
    data.H = rr(data, data.H);
}

/* RR L */
pub fn instrCB__RR_L(data: &mut Z80Data) {
    data.L = rr(data, data.L);
}

/* RR (HL) */
pub fn instrCB__RR_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    byte_temp = rr(data, byte_temp);
    memory.write_byte(data.hl(), byte_temp);
}

/* RR A */
pub fn instrCB__RR_A(data: &mut Z80Data) {
    data.A = rr(data, data.A);
}

/* SLA B */
pub fn instrCB__SLA_B(data: &mut Z80Data) {
    data.B = sla(data, data.B);
}

/* SLA C */
pub fn instrCB__SLA_C(data: &mut Z80Data) {
    data.C = sla(data, data.C);
}

/* SLA D */
pub fn instrCB__SLA_D(data: &mut Z80Data) {
    data.D = sla(data, data.D);
}

/* SLA E */
pub fn instrCB__SLA_E(data: &mut Z80Data) {
    data.E = sla(data, data.E);
}

/* SLA H */
pub fn instrCB__SLA_H(data: &mut Z80Data) {
    data.H = sla(data, data.H);
}

/* SLA L */
pub fn instrCB__SLA_L(data: &mut Z80Data) {
    data.L = sla(data, data.L);
}

/* SLA (HL) */
pub fn instrCB__SLA_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    byte_temp = sla(data, byte_temp);
    memory.write_byte(data.hl(), byte_temp);
}

/* SLA A */
pub fn instrCB__SLA_A(data: &mut Z80Data) {
    data.A = sla(data, data.A);
}

/* SRA B */
pub fn instrCB__SRA_B(data: &mut Z80Data) {
    data.B = sra(data, data.B);
}

/* SRA C */
pub fn instrCB__SRA_C(data: &mut Z80Data) {
    data.C = sra(data, data.C);
}

/* SRA D */
pub fn instrCB__SRA_D(data: &mut Z80Data) {
    data.D = sra(data, data.D);
}

/* SRA E */
pub fn instrCB__SRA_E(data: &mut Z80Data) {
    data.E = sra(data, data.E);
}

/* SRA H */
pub fn instrCB__SRA_H(data: &mut Z80Data) {
    data.H = sra(data, data.H);
}

/* SRA L */
pub fn instrCB__SRA_L(data: &mut Z80Data) {
    data.L = sra(data, data.L);
}

/* SRA (HL) */
pub fn instrCB__SRA_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    byte_temp = sra(data, byte_temp);
    memory.write_byte(data.hl(), byte_temp);
}

/* SRA A */
pub fn instrCB__SRA_A(data: &mut Z80Data) {
    data.A = sra(data, data.A);
}

/* SLL B */
pub fn instrCB__SLL_B(data: &mut Z80Data) {
    data.B = sll(data, data.B);
}

/* SLL C */
pub fn instrCB__SLL_C(data: &mut Z80Data) {
    data.C = sll(data, data.C);
}

/* SLL D */
pub fn instrCB__SLL_D(data: &mut Z80Data) {
    data.D = sll(data, data.D);
}

/* SLL E */
pub fn instrCB__SLL_E(data: &mut Z80Data) {
    data.E = sll(data, data.E);
}

/* SLL H */
pub fn instrCB__SLL_H(data: &mut Z80Data) {
    data.H = sll(data, data.H);
}

/* SLL L */
pub fn instrCB__SLL_L(data: &mut Z80Data) {
    data.L = sll(data, data.L);
}

/* SLL (HL) */
pub fn instrCB__SLL_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    byte_temp = sll(data, byte_temp);
    memory.write_byte(data.hl(), byte_temp);
}

/* SLL A */
pub fn instrCB__SLL_A(data: &mut Z80Data) {
    data.A = sll(data, data.A);
}

/* SRL B */
pub fn instrCB__SRL_B(data: &mut Z80Data) {
    data.B = srl(data, data.B);
}

/* SRL C */
pub fn instrCB__SRL_C(data: &mut Z80Data) {
    data.C = srl(data, data.C);
}

/* SRL D */
pub fn instrCB__SRL_D(data: &mut Z80Data) {
    data.D = srl(data, data.D);
}

/* SRL E */
pub fn instrCB__SRL_E(data: &mut Z80Data) {
    data.E = srl(data, data.E);
}

/* SRL H */
pub fn instrCB__SRL_H(data: &mut Z80Data) {
    data.H = srl(data, data.H);
}

/* SRL L */
pub fn instrCB__SRL_L(data: &mut Z80Data) {
    data.L = srl(data, data.L);
}

/* SRL (HL) */
pub fn instrCB__SRL_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    byte_temp = srl(data, byte_temp);
    memory.write_byte(data.hl(), byte_temp);
}

/* SRL A */
pub fn instrCB__SRL_A(data: &mut Z80Data) {
    data.A = srl(data, data.A);
}

/* BIT 0,B */
pub fn instrCB__BIT_0_B(data: &mut Z80Data) {
    bit(data, 0, data.B);
}

/* BIT 0,C */
pub fn instrCB__BIT_0_C(data: &mut Z80Data) {
    bit(data, 0, data.C);
}

/* BIT 0,D */
pub fn instrCB__BIT_0_D(data: &mut Z80Data) {
    bit(data, 0, data.D);
}

/* BIT 0,E */
pub fn instrCB__BIT_0_E(data: &mut Z80Data) {
    bit(data, 0, data.E);
}

/* BIT 0,H */
pub fn instrCB__BIT_0_H(data: &mut Z80Data) {
    bit(data, 0, data.H);
}

/* BIT 0,L */
pub fn instrCB__BIT_0_L(data: &mut Z80Data) {
    bit(data, 0, data.L);
}

/* BIT 0,(HL) */
pub fn instrCB__BIT_0_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    bit(data, 0, byte_temp)
}

/* BIT 0,A */
pub fn instrCB__BIT_0_A(data: &mut Z80Data) {
    bit(data, 0, data.A)
}

/* BIT 1,B */
pub fn instrCB__BIT_1_B(data: &mut Z80Data) {
    bit(data, 1, data.B)
}

/* BIT 1,C */
pub fn instrCB__BIT_1_C(data: &mut Z80Data) {
    bit(data, 1, data.C)
}

/* BIT 1,D */
pub fn instrCB__BIT_1_D(data: &mut Z80Data) {
    bit(data, 1, data.D)
}

/* BIT 1,E */
pub fn instrCB__BIT_1_E(data: &mut Z80Data) {
    bit(data, 1, data.E)
}

/* BIT 1,H */
pub fn instrCB__BIT_1_H(data: &mut Z80Data) {
    bit(data, 1, data.H)
}

/* BIT 1,L */
pub fn instrCB__BIT_1_L(data: &mut Z80Data) {
    bit(data, 1, data.L)
}

/* BIT 1,(HL) */
pub fn instrCB__BIT_1_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    bit(data, 1, byte_temp);
}

/* BIT 1,A */
pub fn instrCB__BIT_1_A(data: &mut Z80Data) {
    bit(data, 1, data.A);
}

/* BIT 2,B */
pub fn instrCB__BIT_2_B(data: &mut Z80Data) {
    bit(data, 2, data.B);
}

/* BIT 2,C */
pub fn instrCB__BIT_2_C(data: &mut Z80Data) {
    bit(data, 2, data.C);
}

/* BIT 2,D */
pub fn instrCB__BIT_2_D(data: &mut Z80Data) {
    bit(data, 2, data.D);
}

/* BIT 2,E */
pub fn instrCB__BIT_2_E(data: &mut Z80Data) {
    bit(data, 2, data.E);
}

/* BIT 2,H */
pub fn instrCB__BIT_2_H(data: &mut Z80Data) {
    bit(data, 2, data.H);
}

/* BIT 2,L */
pub fn instrCB__BIT_2_L(data: &mut Z80Data) {
    bit(data, 2, data.L);
}

/* BIT 2,(HL) */
pub fn instrCB__BIT_2_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    bit(data, 2, byte_temp);
}

/* BIT 2,A */
pub fn instrCB__BIT_2_A(data: &mut Z80Data) {
    bit(data, 2, data.A);
}

/* BIT 3,B */
pub fn instrCB__BIT_3_B(data: &mut Z80Data) {
    bit(data, 3, data.B);
}

/* BIT 3,C */
pub fn instrCB__BIT_3_C(data: &mut Z80Data) {
    bit(data, 3, data.C);
}

/* BIT 3,D */
pub fn instrCB__BIT_3_D(data: &mut Z80Data) {
    bit(data, 3, data.D)
}

/* BIT 3,E */
pub fn instrCB__BIT_3_E(data: &mut Z80Data) {
    bit(data, 3, data.E)
}

/* BIT 3,H */
pub fn instrCB__BIT_3_H(data: &mut Z80Data) {
    bit(data, 3, data.H)
}

/* BIT 3,L */
pub fn instrCB__BIT_3_L(data: &mut Z80Data) {
    bit(data, 3, data.L)
}

/* BIT 3,(HL) */
pub fn instrCB__BIT_3_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    bit(data, 3, byte_temp);
}

/* BIT 3,A */
pub fn instrCB__BIT_3_A(data: &mut Z80Data) {
    bit(data, 3, data.A);
}

/* BIT 4,B */
pub fn instrCB__BIT_4_B(data: &mut Z80Data) {
    bit(data, 4, data.B);
}

/* BIT 4,C */
pub fn instrCB__BIT_4_C(data: &mut Z80Data) {
    bit(data, 4, data.C);
}

/* BIT 4,D */
pub fn instrCB__BIT_4_D(data: &mut Z80Data) {
    bit(data, 4, data.D);
}

/* BIT 4,E */
pub fn instrCB__BIT_4_E(data: &mut Z80Data) {
    bit(data, 4, data.E);
}

/* BIT 4,H */
pub fn instrCB__BIT_4_H(data: &mut Z80Data) {
    bit(data, 4, data.H);
}

/* BIT 4,L */
pub fn instrCB__BIT_4_L(data: &mut Z80Data) {
    bit(data, 4, data.L);
}

/* BIT 4,(HL) */
pub fn instrCB__BIT_4_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    bit(data, 4, byte_temp);
}

/* BIT 4,A */
pub fn instrCB__BIT_4_A(data: &mut Z80Data) {
    bit(data, 4, data.A);
}

/* BIT 5,B */
pub fn instrCB__BIT_5_B(data: &mut Z80Data) {
    bit(data, 5, data.B);
}

/* BIT 5,C */
pub fn instrCB__BIT_5_C(data: &mut Z80Data) {
    bit(data, 5, data.C);
}

/* BIT 5,D */
pub fn instrCB__BIT_5_D(data: &mut Z80Data) {
    bit(data, 5, data.D);
}

/* BIT 5,E */
pub fn instrCB__BIT_5_E(data: &mut Z80Data) {
    bit(data, 5, data.E);
}

/* BIT 5,H */
pub fn instrCB__BIT_5_H(data: &mut Z80Data) {
    bit(data, 5, data.H);
}

/* BIT 5,L */
pub fn instrCB__BIT_5_L(data: &mut Z80Data) {
    bit(data, 5, data.L);
}

/* BIT 5,(HL) */
pub fn instrCB__BIT_5_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    bit(data, 5, byte_temp);
}

/* BIT 5,A */
pub fn instrCB__BIT_5_A(data: &mut Z80Data) {
    bit(data, 5, data.A);
}

/* BIT 6,B */
pub fn instrCB__BIT_6_B(data: &mut Z80Data) {
    bit(data, 6, data.B);
}

/* BIT 6,C */
pub fn instrCB__BIT_6_C(data: &mut Z80Data) {
    bit(data, 6, data.C);
}

/* BIT 6,D */
pub fn instrCB__BIT_6_D(data: &mut Z80Data) {
    bit(data, 6, data.D);
}

/* BIT 6,E */
pub fn instrCB__BIT_6_E(data: &mut Z80Data) {
    bit(data, 6, data.E);
}

/* BIT 6,H */
pub fn instrCB__BIT_6_H(data: &mut Z80Data) {
    bit(data, 6, data.H)
}

/* BIT 6,L */
pub fn instrCB__BIT_6_L(data: &mut Z80Data) {
    bit(data, 6, data.L)
}

/* BIT 6,(HL) */
pub fn instrCB__BIT_6_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    bit(data, 6, byte_temp);
}

/* BIT 6,A */
pub fn instrCB__BIT_6_A(data: &mut Z80Data) {
    bit(data, 6, data.A);
}

/* BIT 7,B */
pub fn instrCB__BIT_7_B(data: &mut Z80Data) {
    bit(data, 7, data.B);
}

/* BIT 7,C */
pub fn instrCB__BIT_7_C(data: &mut Z80Data) {
    bit(data, 7, data.C);
}

/* BIT 7,D */
pub fn instrCB__BIT_7_D(data: &mut Z80Data) {
    bit(data, 7, data.D);
}

/* BIT 7,E */
pub fn instrCB__BIT_7_E(data: &mut Z80Data) {
    bit(data, 7, data.E);
}

/* BIT 7,H */
pub fn instrCB__BIT_7_H(data: &mut Z80Data) {
    bit(data, 7, data.H);
}

/* BIT 7,L */
pub fn instrCB__BIT_7_L(data: &mut Z80Data) {
    bit(data, 7, data.L);
}

/* BIT 7,(HL) */
pub fn instrCB__BIT_7_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    bit(data, 7, byte_temp);
}

/* BIT 7,A */
pub fn instrCB__BIT_7_A(data: &mut Z80Data) {
    bit(data, 7, data.A);
}

/* RES 0,B */
pub fn instrCB__RES_0_B(data: &mut Z80Data) {
    data.B &= 0xfe;
}

/* RES 0,C */
pub fn instrCB__RES_0_C(data: &mut Z80Data) {
    data.C &= 0xfe;
}

/* RES 0,D */
pub fn instrCB__RES_0_D(data: &mut Z80Data) {
    data.D &= 0xfe;
}

/* RES 0,E */
pub fn instrCB__RES_0_E(data: &mut Z80Data) {
    data.E &= 0xfe;
}

/* RES 0,H */
pub fn instrCB__RES_0_H(data: &mut Z80Data) {
    data.H &= 0xfe;
}

/* RES 0,L */
pub fn instrCB__RES_0_L(data: &mut Z80Data) {
    data.L &= 0xfe;
}

/* RES 0,(HL) */
pub fn instrCB__RES_0_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp & 0xfe);
}

/* RES 0,A */
pub fn instrCB__RES_0_A(data: &mut Z80Data) {
    data.A &= 0xfe;
}

/* RES 1,B */
pub fn instrCB__RES_1_B(data: &mut Z80Data) {
    data.B &= 0xfd;
}

/* RES 1,C */
pub fn instrCB__RES_1_C(data: &mut Z80Data) {
    data.C &= 0xfd;
}

/* RES 1,D */
pub fn instrCB__RES_1_D(data: &mut Z80Data) {
    data.D &= 0xfd;
}

/* RES 1,E */
pub fn instrCB__RES_1_E(data: &mut Z80Data) {
    data.E &= 0xfd;
}

/* RES 1,H */
pub fn instrCB__RES_1_H(data: &mut Z80Data) {
    data.H &= 0xfd;
}

/* RES 1,L */
pub fn instrCB__RES_1_L(data: &mut Z80Data) {
    data.L &= 0xfd;
}

/* RES 1,(HL) */
pub fn instrCB__RES_1_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp & 0xfd);
}

/* RES 1,A */
pub fn instrCB__RES_1_A(data: &mut Z80Data) {
    data.A &= 0xfd;
}

/* RES 2,B */
pub fn instrCB__RES_2_B(data: &mut Z80Data) {
    data.B &= 0xfb;
}

/* RES 2,C */
pub fn instrCB__RES_2_C(data: &mut Z80Data) {
    data.C &= 0xfb;
}

/* RES 2,D */
pub fn instrCB__RES_2_D(data: &mut Z80Data) {
    data.D &= 0xfb;
}

/* RES 2,E */
pub fn instrCB__RES_2_E(data: &mut Z80Data) {
    data.E &= 0xfb;
}

/* RES 2,H */
pub fn instrCB__RES_2_H(data: &mut Z80Data) {
    data.H &= 0xfb;
}

/* RES 2,L */
pub fn instrCB__RES_2_L(data: &mut Z80Data) {
    data.L &= 0xfb;
}

/* RES 2,(HL) */
pub fn instrCB__RES_2_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp & 0xfb)
}

/* RES 2,A */
pub fn instrCB__RES_2_A(data: &mut Z80Data) {
    data.A &= 0xfb
}

/* RES 3,B */
pub fn instrCB__RES_3_B(data: &mut Z80Data) {
    data.B &= 0xf7
}

/* RES 3,C */
pub fn instrCB__RES_3_C(data: &mut Z80Data) {
    data.C &= 0xf7
}

/* RES 3,D */
pub fn instrCB__RES_3_D(data: &mut Z80Data) {
    data.D &= 0xf7
}

/* RES 3,E */
pub fn instrCB__RES_3_E(data: &mut Z80Data) {
    data.E &= 0xf7
}

/* RES 3,H */
pub fn instrCB__RES_3_H(data: &mut Z80Data) {
    data.H &= 0xf7
}

/* RES 3,L */
pub fn instrCB__RES_3_L(data: &mut Z80Data) {
    data.L &= 0xf7
}

/* RES 3,(HL) */
pub fn instrCB__RES_3_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp & 0xf7);
}

/* RES 3,A */
pub fn instrCB__RES_3_A(data: &mut Z80Data) {
    data.A &= 0xf7;
}

/* RES 4,B */
pub fn instrCB__RES_4_B(data: &mut Z80Data) {
    data.B &= 0xef;
}

/* RES 4,C */
pub fn instrCB__RES_4_C(data: &mut Z80Data) {
    data.C &= 0xef;
}

/* RES 4,D */
pub fn instrCB__RES_4_D(data: &mut Z80Data) {
    data.D &= 0xef;
}

/* RES 4,E */
pub fn instrCB__RES_4_E(data: &mut Z80Data) {
    data.E &= 0xef;
}

/* RES 4,H */
pub fn instrCB__RES_4_H(data: &mut Z80Data) {
    data.H &= 0xef;
}

/* RES 4,L */
pub fn instrCB__RES_4_L(data: &mut Z80Data) {
    data.L &= 0xef;
}

/* RES 4,(HL) */
pub fn instrCB__RES_4_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp & 0xef);
}

/* RES 4,A */
pub fn instrCB__RES_4_A(data: &mut Z80Data) {
    data.A &= 0xef;
}

/* RES 5,B */
pub fn instrCB__RES_5_B(data: &mut Z80Data) {
    data.B &= 0xdf;
}

/* RES 5,C */
pub fn instrCB__RES_5_C(data: &mut Z80Data) {
    data.C &= 0xdf;
}

/* RES 5,D */
pub fn instrCB__RES_5_D(data: &mut Z80Data) {
    data.D &= 0xdf;
}

/* RES 5,E */
pub fn instrCB__RES_5_E(data: &mut Z80Data) {
    data.E &= 0xdf;
}

/* RES 5,H */
pub fn instrCB__RES_5_H(data: &mut Z80Data) {
    data.H &= 0xdf;
}

/* RES 5,L */
pub fn instrCB__RES_5_L(data: &mut Z80Data) {
    data.L &= 0xdf;
}

/* RES 5,(HL) */
pub fn instrCB__RES_5_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp & 0xdf);
}

/* RES 5,A */
pub fn instrCB__RES_5_A(data: &mut Z80Data) {
    data.A &= 0xdf;
}

/* RES 6,B */
pub fn instrCB__RES_6_B(data: &mut Z80Data) {
    data.B &= 0xbf
}

/* RES 6,C */
pub fn instrCB__RES_6_C(data: &mut Z80Data) {
    data.C &= 0xbf
}

/* RES 6,D */
pub fn instrCB__RES_6_D(data: &mut Z80Data) {
    data.D &= 0xbf
}

/* RES 6,E */
pub fn instrCB__RES_6_E(data: &mut Z80Data) {
    data.E &= 0xbf
}

/* RES 6,H */
pub fn instrCB__RES_6_H(data: &mut Z80Data) {
    data.H &= 0xbf
}

/* RES 6,L */
pub fn instrCB__RES_6_L(data: &mut Z80Data) {
    data.L &= 0xbf
}

/* RES 6,(HL) */
pub fn instrCB__RES_6_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp & 0xbf);
}

/* RES 6,A */
pub fn instrCB__RES_6_A(data: &mut Z80Data) {
    data.A &= 0xbf;
}

/* RES 7,B */
pub fn instrCB__RES_7_B(data: &mut Z80Data) {
    data.B &= 0x7f;
}

/* RES 7,C */
pub fn instrCB__RES_7_C(data: &mut Z80Data) {
    data.C &= 0x7f;
}

/* RES 7,D */
pub fn instrCB__RES_7_D(data: &mut Z80Data) {
    data.D &= 0x7f;
}

/* RES 7,E */
pub fn instrCB__RES_7_E(data: &mut Z80Data) {
    data.E &= 0x7f;
}

/* RES 7,H */
pub fn instrCB__RES_7_H(data: &mut Z80Data) {
    data.H &= 0x7f;
}

/* RES 7,L */
pub fn instrCB__RES_7_L(data: &mut Z80Data) {
    data.L &= 0x7f;
}

/* RES 7,(HL) */
pub fn instrCB__RES_7_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp & 0x7f);
}

/* RES 7,A */
pub fn instrCB__RES_7_A(data: &mut Z80Data) {
    data.A &= 0x7f;
}

/* SET 0,B */
pub fn instrCB__SET_0_B(data: &mut Z80Data) {
    data.B |= 0x01;
}

/* SET 0,C */
pub fn instrCB__SET_0_C(data: &mut Z80Data) {
    data.C |= 0x01;
}

/* SET 0,D */
pub fn instrCB__SET_0_D(data: &mut Z80Data) {
    data.D |= 0x01;
}

/* SET 0,E */
pub fn instrCB__SET_0_E(data: &mut Z80Data) {
    data.E |= 0x01;
}

/* SET 0,H */
pub fn instrCB__SET_0_H(data: &mut Z80Data) {
    data.H |= 0x01;
}

/* SET 0,L */
pub fn instrCB__SET_0_L(data: &mut Z80Data) {
    data.L |= 0x01;
}

/* SET 0,(HL) */
pub fn instrCB__SET_0_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp | 0x01);
}

/* SET 0,A */
pub fn instrCB__SET_0_A(data: &mut Z80Data) {
    data.A |= 0x01;
}

/* SET 1,B */
pub fn instrCB__SET_1_B(data: &mut Z80Data) {
    data.B |= 0x02;
}

/* SET 1,C */
pub fn instrCB__SET_1_C(data: &mut Z80Data) {
    data.C |= 0x02;
}

/* SET 1,D */
pub fn instrCB__SET_1_D(data: &mut Z80Data) {
    data.D |= 0x02;
}

/* SET 1,E */
pub fn instrCB__SET_1_E(data: &mut Z80Data) {
    data.E |= 0x02;
}

/* SET 1,H */
pub fn instrCB__SET_1_H(data: &mut Z80Data) {
    data.H |= 0x02;
}

/* SET 1,L */
pub fn instrCB__SET_1_L(data: &mut Z80Data) {
    data.L |= 0x02;
}

/* SET 1,(HL) */
pub fn instrCB__SET_1_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp | 0x02)
}

/* SET 1,A */
pub fn instrCB__SET_1_A(data: &mut Z80Data) {
    data.A |= 0x02;
}

/* SET 2,B */
pub fn instrCB__SET_2_B(data: &mut Z80Data) {
    data.B |= 0x04;
}

/* SET 2,C */
pub fn instrCB__SET_2_C(data: &mut Z80Data) {
    data.C |= 0x04;
}

/* SET 2,D */
pub fn instrCB__SET_2_D(data: &mut Z80Data) {
    data.D |= 0x04;
}

/* SET 2,E */
pub fn instrCB__SET_2_E(data: &mut Z80Data) {
    data.E |= 0x04;
}

/* SET 2,H */
pub fn instrCB__SET_2_H(data: &mut Z80Data) {
    data.H |= 0x04;
}

/* SET 2,L */
pub fn instrCB__SET_2_L(data: &mut Z80Data) {
    data.L |= 0x04;
}

/* SET 2,(HL) */
pub fn instrCB__SET_2_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp | 0x04)
}

/* SET 2,A */
pub fn instrCB__SET_2_A(data: &mut Z80Data) {
    data.A |= 0x04;
}

/* SET 3,B */
pub fn instrCB__SET_3_B(data: &mut Z80Data) {
    data.B |= 0x08;
}

/* SET 3,C */
pub fn instrCB__SET_3_C(data: &mut Z80Data) {
    data.C |= 0x08;
}

/* SET 3,D */
pub fn instrCB__SET_3_D(data: &mut Z80Data) {
    data.D |= 0x08;
}

/* SET 3,E */
pub fn instrCB__SET_3_E(data: &mut Z80Data) {
    data.E |= 0x08;
}

/* SET 3,H */
pub fn instrCB__SET_3_H(data: &mut Z80Data) {
    data.H |= 0x08;
}

/* SET 3,L */
pub fn instrCB__SET_3_L(data: &mut Z80Data) {
    data.L |= 0x08;
}

/* SET 3,(HL) */
pub fn instrCB__SET_3_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp | 0x08)
}

/* SET 3,A */
pub fn instrCB__SET_3_A(data: &mut Z80Data) {
    data.A |= 0x08;
}

/* SET 4,B */
pub fn instrCB__SET_4_B(data: &mut Z80Data) {
    data.B |= 0x10;
}

/* SET 4,C */
pub fn instrCB__SET_4_C(data: &mut Z80Data) {
    data.C |= 0x10;
}

/* SET 4,D */
pub fn instrCB__SET_4_D(data: &mut Z80Data) {
    data.D |= 0x10;
}

/* SET 4,E */
pub fn instrCB__SET_4_E(data: &mut Z80Data) {
    data.E |= 0x10;
}

/* SET 4,H */
pub fn instrCB__SET_4_H(data: &mut Z80Data) {
    data.H |= 0x10;
}

/* SET 4,L */
pub fn instrCB__SET_4_L(data: &mut Z80Data) {
    data.L |= 0x10;
}

/* SET 4,(HL) */
pub fn instrCB__SET_4_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp | 0x10)
}

/* SET 4,A */
pub fn instrCB__SET_4_A(data: &mut Z80Data) {
    data.A |= 0x10;
}

/* SET 5,B */
pub fn instrCB__SET_5_B(data: &mut Z80Data) {
    data.B |= 0x20;
}

/* SET 5,C */
pub fn instrCB__SET_5_C(data: &mut Z80Data) {
    data.C |= 0x20;
}

/* SET 5,D */
pub fn instrCB__SET_5_D(data: &mut Z80Data) {
    data.D |= 0x20;
}

/* SET 5,E */
pub fn instrCB__SET_5_E(data: &mut Z80Data) {
    data.E |= 0x20;
}

/* SET 5,H */
pub fn instrCB__SET_5_H(data: &mut Z80Data) {
    data.H |= 0x20;
}

/* SET 5,L */
pub fn instrCB__SET_5_L(data: &mut Z80Data) {
    data.L |= 0x20;
}

/* SET 5,(HL) */
pub fn instrCB__SET_5_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp | 0x20)
}

/* SET 5,A */
pub fn instrCB__SET_5_A(data: &mut Z80Data) {
    data.A |= 0x20;
}

/* SET 6,B */
pub fn instrCB__SET_6_B(data: &mut Z80Data) {
    data.B |= 0x40;
}

/* SET 6,C */
pub fn instrCB__SET_6_C(data: &mut Z80Data) {
    data.C |= 0x40;
}

/* SET 6,D */
pub fn instrCB__SET_6_D(data: &mut Z80Data) {
    data.D |= 0x40;
}

/* SET 6,E */
pub fn instrCB__SET_6_E(data: &mut Z80Data) {
    data.E |= 0x40;
}

/* SET 6,H */
pub fn instrCB__SET_6_H(data: &mut Z80Data) {
    data.H |= 0x40;
}

/* SET 6,L */
pub fn instrCB__SET_6_L(data: &mut Z80Data) {
    data.L |= 0x40;
}

/* SET 6,(HL) */
pub fn instrCB__SET_6_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp | 0x40)
}

/* SET 6,A */
pub fn instrCB__SET_6_A(data: &mut Z80Data) {
    data.A |= 0x40;
}

/* SET 7,B */
pub fn instrCB__SET_7_B(data: &mut Z80Data) {
    data.B |= 0x80;
}

/* SET 7,C */
pub fn instrCB__SET_7_C(data: &mut Z80Data) {
    data.C |= 0x80;
}

/* SET 7,D */
pub fn instrCB__SET_7_D(data: &mut Z80Data) {
    data.D |= 0x80;
}

/* SET 7,E */
pub fn instrCB__SET_7_E(data: &mut Z80Data) {
    data.E |= 0x80;
}

/* SET 7,H */
pub fn instrCB__SET_7_H(data: &mut Z80Data) {
    data.H |= 0x80;
}

/* SET 7,L */
pub fn instrCB__SET_7_L(data: &mut Z80Data) {
    data.L |= 0x80;
}

/* SET 7,(HL) */
pub fn instrCB__SET_7_iHL(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq(data.hl(), 1);
    memory.write_byte(data.hl(), byte_temp | 0x80)
}

/* SET 7,A */
pub fn instrCB__SET_7_A(data: &mut Z80Data) {
    data.A |= 0x80;
}

/* IN B,(C) */
pub fn instrED__IN_B_iC(data: &mut Z80Data, ports: &mut Ports) {
    // self.in(&data.B, data.bc())
    let bc = data.bc();
    data.B = in_u8_ex(data, ports, bc);
}

/* OUT (C),B */
pub fn instrED__OUT_iC_B(data: &mut Z80Data, ports: &mut Ports) {
    ports.write_port(data.bc(), data.B);
}

/* SBC HL,BC */
pub fn instrED__SBC_HL_BC(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    sbc16(data, data.bc());
}

/* LD (nnnn),BC */
fn_instr_ld_i_nnnn_r16!(instrED__LD_iNNNN_BC, C, B);

/* NEG */
pub fn instrED__NEG(data: &mut Z80Data) {
    let byte_temp = data.A;
    data.A = 0;
    sub(data, byte_temp);
}

/* RETN */
pub fn instrED__RETN(data: &mut Z80Data, memory: &mut Memory, hook: Rc<RefCell<dyn FuncHook>>) {
    data.IFF1 = data.IFF2;
    ret(data, memory, hook);
}

/* IM 0 */
pub fn instrED__IM_0(data: &mut Z80Data) {
    data.IM = 0;
}

/* LD I,A */
pub fn instrED__LD_I_A(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    data.I = data.A;
}

/* IN C,(C) */
pub fn instrED__IN_C_iC(data: &mut Z80Data, ports: &mut Ports) {
    data.C = in_u8_ex(data, ports, data.bc());
}

/* OUT (C),C */
pub fn instrED__OUT_iC_C(data: &mut Z80Data, ports: &mut Ports) {
    ports.write_port(data.bc(), data.C);
}

/* ADC HL,BC */
pub fn instrED__ADC_HL_BC(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    adc16(data, data.bc());
}

/* LD BC,(nnnn) */
fn_instr_ld_hl_i_nnnn!(instrED__LD_BC_iNNNN, C, B);

/* LD R,A */
pub fn instrED__LD_R_A(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    /* Keep the RZX instruction counter right */
    data.rzx_instructions_offset += (data.R as isize) - (data.A as isize);
    (data.R, data.R7) = ((data.A as u16), data.A);
}

/* IN D,(C) */
pub fn instrED__IN_D_iC(data: &mut Z80Data, ports: &mut Ports) {
    data.D = in_u8_ex(data, ports, data.bc());
}

/* OUT (C),D */
pub fn instrED__OUT_iC_D(data: &mut Z80Data, ports: &mut Ports) {
    ports.write_port(data.bc(), data.D);
}

/* SBC HL,DE */
pub fn instrED__SBC_HL_DE(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    sbc16(data, data.de());
}

/* LD (nnnn),DE */
fn_instr_ld_i_nnnn_r16!(instrED__LD_iNNNN_DE, E, D);

/* IM 1 */
pub fn instrED__IM_1(data: &mut Z80Data) {
    data.IM = 1;
}

/* LD A,I */
pub fn instrED__LD_A_I(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    data.A = data.I;
    data.F = data.F & FLAG_C
        | z80_tables::get().sz53_table[data.A as usize]
        | tern_op_b(data.IFF2 != 0, FLAG_V, 0);
}

/* IN E,(C) */
pub fn instrED__IN_E_iC(data: &mut Z80Data, ports: &mut Ports) {
    let port = data.bc();
    data.E = in_u8_ex(data, ports, port);
}

/* OUT (C),E */
pub fn instrED__OUT_iC_E(data: &mut Z80Data, ports: &mut Ports) {
    ports.write_port(data.bc(), data.E);
}

/* ADC HL,DE */
pub fn instrED__ADC_HL_DE(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    adc16(data, data.de());
}

/* LD DE,(nnnn) */
fn_instr_ld_hl_i_nnnn!(instrED__LD_DE_iNNNN, E, D);

/* IM 2 */
pub fn instrED__IM_2(data: &mut Z80Data) {
    data.IM = 2;
}

/* LD A,R */
pub fn instrED__LD_A_R(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    data.A = (data.R & 0x7f) as u8 | (data.R7 & 0x80);
    data.F = data.F & FLAG_C
        | z80_tables::get().sz53_table[data.A as usize]
        | tern_op_b(data.IFF2 != 0, FLAG_V, 0);
}

/* IN H,(C) */
pub fn instrED__IN_H_iC(data: &mut Z80Data, ports: &mut Ports) {
    data.H = in_u8_ex(data, ports, data.bc());
}

/* OUT (C),H */
pub fn instrED__OUT_iC_H(data: &mut Z80Data, ports: &mut Ports) {
    ports.write_port(data.bc(), data.H);
}

/* SBC HL,HL */
pub fn instrED__SBC_HL_HL(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    sbc16(data, data.hl())
}

/* LD (nnnn),HL */
fn_instr_ld_i_nnnn_r16!(instrED__LD_iNNNN_HL, L, H);

/* RRD */
pub fn instrED__RRD(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq_loop(data.hl(), 1, 4);
    memory.write_byte(data.hl(), (data.A << 4) | (byte_temp >> 4));
    data.A = data.A & 0xf0 | byte_temp & 0x0f;
    data.F = data.F & FLAG_C | z80_tables::get().sz53p_table[data.A as usize];
}

/* IN L,(C) */
pub fn instrED__IN_L_iC(data: &mut Z80Data, ports: &mut Ports) {
    data.L = in_u8_ex(data, ports, data.bc());
}

/* OUT (C),L */
pub fn instrED__OUT_iC_L(data: &mut Z80Data, ports: &mut Ports) {
    ports.write_port(data.bc(), data.L);
}

/* ADC HL,HL */
pub fn instrED__ADC_HL_HL(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    adc16(data, data.hl());
}

/* LD HL,(nnnn) */
fn_instr_ld_hl_i_nnnn!(instrED__LD_HL_iNNNN, L, H);

/* RLD */
pub fn instrED__RLD(data: &mut Z80Data, memory: &mut Memory) {
    let byte_temp: u8 = memory.read_byte(data.hl());
    memory.contend_read_no_mreq_loop(data.hl(), 1, 4);
    memory.write_byte(data.hl(), (byte_temp << 4) | (data.A & 0x0f));
    data.A = (data.A & 0xf0) | (byte_temp >> 4);
    data.F = data.F & FLAG_C | z80_tables::get().sz53p_table[data.A as usize];
}

/* IN F,(C) */
pub fn instrED__IN_F_iC(data: &mut Z80Data, ports: &mut Ports) {
    let _byte_temp: u8 = in_u8_ex(data, ports, data.bc());
}

/* OUT (C),0 */
pub fn instrED__OUT_iC_0(data: &mut Z80Data, ports: &mut Ports) {
    ports.write_port(data.bc(), 0);
}

/* SBC HL,SP */
pub fn instrED__SBC_HL_SP(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    let value = data.sp();
    sbc16(data, value);
}

/* LD (nnnn),SP */
pub fn instrED__LD_iNNNN_SP(data: &mut Z80Data, memory: &mut Memory) {
    let (sph, spl) = split_word(data.sp);
    ld16nnrr(data, memory, spl, sph);
    // break
}

/* IN A,(C) */
pub fn instrED__IN_A_iC(data: &mut Z80Data, ports: &mut Ports) {
    data.A = in_u8_ex(data, ports, data.bc());
}

/* OUT (C),A */
pub fn instrED__OUT_iC_A(data: &mut Z80Data, ports: &mut Ports) {
    ports.write_port(data.bc(), data.A);
}

/* ADC HL,SP */
pub fn instrED__ADC_HL_SP(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    let value = data.sp();
    adc16(data, value);
}

/* LD SP,(nnnn) */
pub fn instrED__LD_SP_iNNNN(data: &mut Z80Data, memory: &mut Memory) {
    // let (sph, spl) = splitWord(data.sp());
    let (spl, sph) = ld16rrnn_ex(data, memory);
    data.set_sp(join_bytes(sph, spl));
    // break
}

/* LDI */
pub fn instrED__LDI(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    data.dec_bc();
    memory.write_byte(data.de(), byte_temp);
    memory.contend_write_no_mreq_loop(data.de(), 1, 2);
    data.inc_de();
    data.inc_hl();
    byte_temp += data.A;
    data.F = data.F & (FLAG_C | FLAG_Z | FLAG_S)
        | tern_op_b(data.bc() != 0, FLAG_V, 0)
        | byte_temp & FLAG_3
        | tern_op_b((byte_temp & 0x02) != 0, FLAG_5, 0);
}

/* CPI */
pub fn instrED__CPI(data: &mut Z80Data, memory: &mut Memory) {
    let value: u8 = memory.read_byte(data.hl());
    let mut byte_temp: u8 = data.A - value;
    let lookup: u8 = ((data.A & 0x08) >> 3) | ((value & 0x08) >> 2) | ((byte_temp & 0x08) >> 1);
    memory.contend_read_no_mreq_loop(data.hl(), 1, 5);
    data.inc_hl();
    data.dec_bc();
    data.F = data.F & FLAG_C
        | tern_op_b(data.bc() != 0, FLAG_V | FLAG_N, FLAG_N)
        | HALF_CARRY_SUB_TABLE[lookup as usize]
        | tern_op_b(byte_temp != 0, 0, FLAG_Z)
        | byte_temp & FLAG_S;
    if (data.F & FLAG_H) != 0 {
        byte_temp -= 1;
    }
    data.F |= (byte_temp & FLAG_3) | tern_op_b((byte_temp & 0x02) != 0, FLAG_5, 0);
}

/* INI */
pub fn instrED__INI(data: &mut Z80Data, memory: &mut Memory, ports: &mut Ports) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    let in_i_temp: u8 = ports.read_port(data.bc());
    memory.write_byte(data.hl(), in_i_temp);

    data.B = data.B.wrapping_sub(1);
    data.inc_hl();
    let in_i_temp2: u8 = in_i_temp.wrapping_add(data.C).wrapping_add(1);
    data.F = tern_op_b((in_i_temp & 0x80) != 0, FLAG_N, 0)
        | tern_op_b(in_i_temp2 < in_i_temp, FLAG_H | FLAG_C, 0)
        | tern_op_b(
            z80_tables::get().parity_table[((in_i_temp2 & 0x07) ^ data.B) as usize] != 0,
            FLAG_P,
            0,
        )
        | z80_tables::get().sz53_table[data.B as usize];
}

/* OUTI */
pub fn instrED__OUTI(data: &mut Z80Data, memory: &mut Memory, ports: &mut Ports) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    let out_i_temp: u8 = memory.read_byte(data.hl());
    data.B = data.B.wrapping_sub(1); /* This does happen first, despite what the specs say */
    ports.write_port(data.bc(), out_i_temp);

    data.inc_hl();
    let out_i_temp2: u8 = out_i_temp.wrapping_add(data.L); // + data.L;
    data.F = tern_op_b((out_i_temp & 0x80) != 0, FLAG_N, 0)
        | tern_op_b(out_i_temp2 < out_i_temp, FLAG_H | FLAG_C, 0)
        | tern_op_b(
            z80_tables::get().parity_table[((out_i_temp2 & 0x07) ^ data.B) as usize] != 0,
            FLAG_P,
            0,
        )
        | z80_tables::get().sz53_table[data.B as usize];
}

/* LDD */
pub fn instrED__LDD(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    data.dec_bc();
    memory.write_byte(data.de(), byte_temp);
    memory.contend_write_no_mreq_loop(data.de(), 1, 2);
    data.dec_de();
    data.dec_hl();
    byte_temp += data.A;
    data.F = data.F & (FLAG_C | FLAG_Z | FLAG_S)
        | tern_op_b(data.bc() != 0, FLAG_V, 0)
        | byte_temp & FLAG_3
        | tern_op_b((byte_temp & 0x02) != 0, FLAG_5, 0);
}

/* CPD */
pub fn instrED__CPD(data: &mut Z80Data, memory: &mut Memory) {
    let value: u8 = memory.read_byte(data.hl());
    let mut byte_temp: u8 = data.A - value;
    let lookup: u8 = ((data.A & 0x08) >> 3) | ((value & 0x08) >> 2) | ((byte_temp & 0x08) >> 1);
    memory.contend_read_no_mreq_loop(data.hl(), 1, 5);
    data.dec_hl();
    data.dec_bc();
    data.F = data.F & FLAG_C
        | tern_op_b(data.bc() != 0, FLAG_V | FLAG_N, FLAG_N)
        | HALF_CARRY_SUB_TABLE[lookup as usize]
        | tern_op_b(byte_temp != 0, 0, FLAG_Z)
        | byte_temp & FLAG_S;
    if (data.F & FLAG_H) != 0 {
        byte_temp -= 1;
    }
    data.F |= (byte_temp & FLAG_3) | tern_op_b((byte_temp & 0x02) != 0, FLAG_5, 0)
}

/* IND */
pub fn instrED__IND(data: &mut Z80Data, memory: &mut Memory, ports: &mut Ports) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    let in_i_temp: u8 = ports.read_port(data.bc());
    memory.write_byte(data.hl(), in_i_temp);

    data.B = data.B.wrapping_sub(1);
    data.dec_hl();
    let in_i_temp2: u8 = in_i_temp + data.C - 1;
    data.F = tern_op_b((in_i_temp & 0x80) != 0, FLAG_N, 0)
        | tern_op_b(in_i_temp2 < in_i_temp, FLAG_H | FLAG_C, 0)
        | tern_op_b(
            z80_tables::get().parity_table[((in_i_temp2 & 0x07) ^ data.B) as usize] != 0,
            FLAG_P,
            0,
        )
        | z80_tables::get().sz53_table[data.B as usize]
}

/* OUTD */
pub fn instrED__OUTD(data: &mut Z80Data, memory: &mut Memory, ports: &mut Ports) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    let out_i_temp: u8 = memory.read_byte(data.hl());
    data.B = data.B.wrapping_sub(1); /* This does happen first, despite what the specs say */
    ports.write_port(data.bc(), out_i_temp);

    data.dec_hl();
    let out_i_temp2: u8 = out_i_temp + data.L;
    data.F = tern_op_b((out_i_temp & 0x80) != 0, FLAG_N, 0)
        | tern_op_b(out_i_temp2 < out_i_temp, FLAG_H | FLAG_C, 0)
        | tern_op_b(
            z80_tables::get().parity_table[((out_i_temp2 & 0x07) ^ data.B) as usize] != 0,
            FLAG_P,
            0,
        )
        | z80_tables::get().sz53_table[data.B as usize];
}

/* LDIR */
pub fn instrED__LDIR(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.write_byte(data.de(), byte_temp);
    memory.contend_write_no_mreq_loop(data.de(), 1, 2);
    data.dec_bc();
    byte_temp = byte_temp.wrapping_add(data.A);
    data.F = data.F & (FLAG_C | FLAG_Z | FLAG_S)
        | tern_op_b(data.bc() != 0, FLAG_V, 0)
        | byte_temp & FLAG_3
        | tern_op_b(byte_temp & 0x02 != 0, FLAG_5, 0);
    if data.bc() != 0 {
        memory.contend_write_no_mreq_loop(data.de(), 1, 5);
        data.dec_pc(2);
        data.cycles += 23;
    } else {
        data.cycles += 18;
    }
    data.inc_hl();
    data.inc_de();
}

/* CPIR */
pub fn instrED__CPIR(data: &mut Z80Data, memory: &mut Memory) {
    let value: u8 = memory.read_byte(data.hl());
    let mut byte_temp: u8 = data.A - value;
    let lookup: u8 = ((data.A & 0x08) >> 3) | ((value & 0x08) >> 2) | ((byte_temp & 0x08) >> 1);
    memory.contend_read_no_mreq_loop(data.hl(), 1, 5);
    data.dec_bc();
    data.F = data.F & FLAG_C
        | tern_op_b(data.bc() != 0, FLAG_V | FLAG_N, FLAG_N)
        | HALF_CARRY_SUB_TABLE[lookup as usize]
        | tern_op_b(byte_temp != 0, 0, FLAG_Z)
        | byte_temp & FLAG_S;
    if data.F & FLAG_H != 0 {
        byte_temp -= 1;
    }
    data.F |= (byte_temp & FLAG_3) | tern_op_b((byte_temp & 0x02) != 0, FLAG_5, 0);
    if (data.F & (FLAG_V | FLAG_Z)) == FLAG_V {
        memory.contend_read_no_mreq_loop(data.hl(), 1, 5);
        data.dec_pc(2);
        data.cycles += 18;
    } else {
        data.cycles += 23;
    }
    data.inc_hl();
}

/* INIR */
pub fn instrED__INIR(data: &mut Z80Data, memory: &mut Memory, ports: &mut Ports) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    let in_i_temp: u8 = ports.read_port(data.bc());
    memory.write_byte(data.hl(), in_i_temp);

    data.B = data.B.wrapping_sub(1);
    let in_i_temp2: u8 = in_i_temp + data.C + 1;
    data.F = tern_op_b(in_i_temp & 0x80 != 0, FLAG_N, 0)
        | tern_op_b(in_i_temp2 < in_i_temp, FLAG_H | FLAG_C, 0)
        | tern_op_b(
            z80_tables::get().parity_table[((in_i_temp2 & 0x07) ^ data.B) as usize] != 0,
            FLAG_P,
            0,
        )
        | z80_tables::get().sz53_table[data.B as usize];

    if data.B != 0 {
        memory.contend_write_no_mreq_loop(data.hl(), 1, 5);
        data.dec_pc(2);
        data.cycles += 23;
    } else {
        data.cycles += 18;
    }
    data.inc_hl();
}

/* OTIR */
pub fn instrED__OTIR(data: &mut Z80Data, memory: &mut Memory, ports: &mut Ports) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    let out_i_temp: u8 = memory.read_byte(data.hl());
    data.B = data.B.wrapping_sub(1); /* This does happen first, despite what the specs say */
    ports.write_port(data.bc(), out_i_temp);

    data.inc_hl();
    let out_i_temp2: u8 = out_i_temp.wrapping_add(data.L);

    data.F = tern_op_b((out_i_temp & 0x80) != 0, FLAG_N, 0)
        | tern_op_b(out_i_temp2 < out_i_temp, FLAG_H | FLAG_C, 0)
        | tern_op_b(
            z80_tables::get().parity_table[((out_i_temp2 & 0x07) ^ data.B) as usize] != 0,
            FLAG_P,
            0,
        )
        | z80_tables::get().sz53_table[data.B as usize];

    if data.B != 0 {
        memory.contend_read_no_mreq_loop(data.bc(), 1, 5);
        data.dec_pc(2);
        data.cycles += 23;
    } else {
        data.cycles += 18;
    }
}

/* LDDR */
pub fn instrED__LDDR(data: &mut Z80Data, memory: &mut Memory) {
    let mut byte_temp: u8 = memory.read_byte(data.hl());
    memory.write_byte(data.de(), byte_temp);
    memory.contend_write_no_mreq_loop(data.de(), 1, 2);
    data.dec_bc();
    byte_temp = byte_temp.wrapping_add(data.A);
    data.F = data.F & (FLAG_C | FLAG_Z | FLAG_S)
        | tern_op_b(data.bc() != 0, FLAG_V, 0)
        | byte_temp & FLAG_3
        | tern_op_b(byte_temp & 0x02 != 0, FLAG_5, 0);
    if data.bc() != 0 {
        memory.contend_write_no_mreq_loop(data.de(), 1, 5);
        data.dec_pc(2);
        data.cycles += 23;
    } else {
        data.cycles += 18;
    }
    data.dec_hl();
    data.dec_de();
}

/* CPDR */
pub fn instrED__CPDR(data: &mut Z80Data, memory: &mut Memory) {
    let value: u8 = memory.read_byte(data.hl());
    let mut byte_temp: u8 = data.A - value;
    let lookup: u8 = ((data.A & 0x08) >> 3) | ((value & 0x08) >> 2) | ((byte_temp & 0x08) >> 1);
    memory.contend_read_no_mreq_loop(data.hl(), 1, 5);
    data.dec_bc();
    data.F = data.F & FLAG_C
        | tern_op_b(data.bc() != 0, FLAG_V | FLAG_N, FLAG_N)
        | HALF_CARRY_SUB_TABLE[lookup as usize]
        | tern_op_b(byte_temp != 0, 0, FLAG_Z)
        | byte_temp & FLAG_S;
    if data.F & FLAG_H != 0 {
        byte_temp -= 1;
    }
    data.F |= byte_temp & FLAG_3 | tern_op_b((byte_temp & 0x02) != 0, FLAG_5, 0);
    if data.F & (FLAG_V | FLAG_Z) == FLAG_V {
        memory.contend_read_no_mreq_loop(data.hl(), 1, 5);
        data.dec_pc(2);
        data.cycles += 18;
    } else {
        data.cycles += 23;
    }
    data.dec_hl();
}

/* INDR */
pub fn instrED__INDR(data: &mut Z80Data, memory: &mut Memory, ports: &mut Ports) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    let in_i_temp: u8 = ports.read_port(data.bc());
    memory.write_byte(data.hl(), in_i_temp);

    data.B = data.B.wrapping_sub(1);
    let in_i_temp2: u8 = in_i_temp + data.C - 1;
    data.F = tern_op_b(in_i_temp & 0x80 != 0, FLAG_N, 0)
        | tern_op_b(in_i_temp2 < in_i_temp, FLAG_H | FLAG_C, 0)
        | tern_op_b(
            z80_tables::get().parity_table[((in_i_temp2 & 0x07) ^ data.B) as usize] != 0,
            FLAG_P,
            0,
        )
        | z80_tables::get().sz53_table[data.B as usize];

    if data.B != 0 {
        memory.contend_write_no_mreq_loop(data.hl(), 1, 5);
        data.dec_pc(2);
        data.cycles += 23;
    } else {
        data.cycles += 18;
    }
    data.dec_hl();
}

/* OTDR */
pub fn instrED__OTDR(data: &mut Z80Data, memory: &mut Memory, ports: &mut Ports) {
    let _address = data.ir();
    memory.contend_read_no_mreq(_address, 1);
    let address = data.hl();
    let out_i_temp: u8 = memory.read_byte(address);
    data.B = data.B.wrapping_sub(1); /* This does happen first, despite what the specs say */
    ports.write_port(data.bc(), out_i_temp);

    data.dec_hl();
    let out_i_temp2: u8 = out_i_temp + data.L;
    data.F = tern_op_b((out_i_temp & 0x80) != 0, FLAG_N, 0)
        | tern_op_b(out_i_temp2 < out_i_temp, FLAG_H | FLAG_C, 0)
        | tern_op_b(
            z80_tables::get().parity_table[((out_i_temp2 & 0x07) ^ data.B) as usize] != 0,
            FLAG_P,
            0,
        )
        | z80_tables::get().sz53_table[data.B as usize];

    if data.B != 0 {
        memory.contend_read_no_mreq_loop(data.bc(), 1, 5);
        data.dec_pc(2);
        data.cycles += 23;
    } else {
        data.cycles += 18;
    }
}

/* slttrap */
pub fn instrED__SLTTRAP(data: &mut Z80Data, memory: &mut Memory) {
    slt_trap(data, memory, data.hl() as i16, data.A);
}

/* ADD ix,BC */
pub fn instrDD__ADD_REG_BC(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    // add16(data,  self.ix, data.bc())
    let mut ix = Register16::new(data.IXH, data.IXL);
    let value2 = data.bc();
    add16(data, &mut ix, value2);
    (data.IXH, data.IXL) = ix.result();
}

/* ADD ix,DE */
pub fn instrDD__ADD_REG_DE(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    // add16(data,  self.ix, data.de())
    let mut ix = Register16::new(data.IXH, data.IXL);
    let value2 = data.de();
    add16(data, &mut ix, value2);
    (data.IXH, data.IXL) = ix.result();
}

/* LD ix,nnnn */
pub fn instrDD__LD_REG_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let b1 = memory.read_byte(address);
    data.inc_pc(1);
    let address = data.pc();
    let b2 = memory.read_byte(address);
    data.inc_pc(1);
    data.set_ix(join_bytes(b2, b1));
}

/* LD (nnnn),ix */
fn_instr_ld_i_nnnn_r16!(instrDD__LD_iNNNN_REG, IXL, IXH);

/* INC ix */
pub fn instrDD__INC_REG(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 2);
    data.inc_ix()
}

/* INC IXH */
pub fn instrDD__INC_REGH(data: &mut Z80Data) {
    data.inc_ixh()
}

/* DEC IXH */
pub fn instrDD__DEC_REGH(data: &mut Z80Data) {
    data.dec_ixh()
}

/* LD IXH,nn */
pub fn instrDD__LD_REGH_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    data.IXH = memory.read_byte(address);
    data.inc_pc(1);
}

/* ADD ix,ix */
pub fn instrDD__ADD_REG_REG(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    // add16(data,  self.ix, data.ix());
    let mut ix = Register16::new(data.IXH, data.IXL);
    let value2 = data.ix();
    add16(data, &mut ix, value2);
    (data.IXH, data.IXL) = ix.result();
}

/* LD ix,(nnnn) */
fn_instr_ld_hl_i_nnnn!(instrDD__LD_REG_iNNNN, IXL, IXH);

/* DEC ix */
pub fn instrDD__DEC_REG(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 2);
    data.dec_ix()
}

/* INC IXL */
pub fn instrDD__INC_REGL(data: &mut Z80Data) {
    data.inc_ixl()
}

/* DEC IXL */
pub fn instrDD__DEC_REGL(data: &mut Z80Data) {
    data.dec_ixl()
}

/* LD IXL,nn */
pub fn instrDD__LD_REGL_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    data.IXL = memory.read_byte(address);
    data.inc_pc(1);
}

/* INC (ix+dd) */
fn_instr_dd_op_i_reg_p_dd!(instrDD__INC_iREGpDD, inc);

/* DEC (ix+dd) */
fn_instr_dd_op_i_reg_p_dd!(instrDD__DEC_iREGpDD, dec);

/* LD (ix+dd),nn */
pub fn instrDD__LD_iREGpDD_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let offset = memory.read_byte(address);
    data.inc_pc(1);
    let address = data.pc();
    let value = memory.read_byte(address);
    let _address = data.pc();
    memory.contend_read_no_mreq_loop(_address, 1, 2);
    data.inc_pc(1);
    memory.write_byte(data.ix() + (sign_extend(offset) as u16), value);
}

/* ADD ix,SP */
pub fn instrDD__ADD_REG_SP(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    // add16(data,  self.ix, data.sp());
    let mut ix = Register16::new(data.IXH, data.IXL);
    let value2 = data.sp();
    add16(data, &mut ix, value2);
    (data.IXH, data.IXL) = ix.result();
}

/* LD B,IXH */
pub fn instrDD__LD_B_REGH(data: &mut Z80Data) {
    data.B = data.IXH
}

/* LD B,IXL */
pub fn instrDD__LD_B_REGL(data: &mut Z80Data) {
    data.B = data.IXL
}

/* LD B,(ix+dd) */
fn_instr_dd_ld_r_i_reg_p_dd!(instrDD__LD_B_iREGpDD, B);

/* LD C,IXH */
pub fn instrDD__LD_C_REGH(data: &mut Z80Data) {
    data.C = data.IXH
}

/* LD C,IXL */
pub fn instrDD__LD_C_REGL(data: &mut Z80Data) {
    data.C = data.IXL
}

/* LD C,(ix+dd) */
fn_instr_dd_ld_r_i_reg_p_dd!(instrDD__LD_C_iREGpDD, C);

/* LD D,IXH */
pub fn instrDD__LD_D_REGH(data: &mut Z80Data) {
    data.D = data.IXH
}

/* LD D,IXL */
pub fn instrDD__LD_D_REGL(data: &mut Z80Data) {
    data.D = data.IXL
}

/* LD D,(ix+dd) */
fn_instr_dd_ld_r_i_reg_p_dd!(instrDD__LD_D_iREGpDD, D);

/* LD E,IXH */
pub fn instrDD__LD_E_REGH(data: &mut Z80Data) {
    data.E = data.IXH
}

/* LD E,IXL */
pub fn instrDD__LD_E_REGL(data: &mut Z80Data) {
    data.E = data.IXL
}

/* LD E,(ix+dd) */
fn_instr_dd_ld_r_i_reg_p_dd!(instrDD__LD_E_iREGpDD, E);

/* LD IXH,B */
pub fn instrDD__LD_REGH_B(data: &mut Z80Data) {
    data.IXH = data.B
}

/* LD IXH,C */
pub fn instrDD__LD_REGH_C(data: &mut Z80Data) {
    data.IXH = data.C
}

/* LD IXH,D */
pub fn instrDD__LD_REGH_D(data: &mut Z80Data) {
    data.IXH = data.D
}

/* LD IXH,E */
pub fn instrDD__LD_REGH_E(data: &mut Z80Data) {
    data.IXH = data.E
}

/* LD IXH,IXH */
pub fn instrDD__LD_REGH_REGH(_data: &mut Z80Data) {}

/* LD IXH,IXL */
pub fn instrDD__LD_REGH_REGL(data: &mut Z80Data) {
    data.IXH = data.IXL
}

/* LD H,(ix+dd) */
fn_instr_dd_ld_r_i_reg_p_dd!(instrDD__LD_H_iREGpDD, H);

/* LD IXH,A */
pub fn instrDD__LD_REGH_A(data: &mut Z80Data) {
    data.IXH = data.A
}

/* LD IXL,B */
pub fn instrDD__LD_REGL_B(data: &mut Z80Data) {
    data.IXL = data.B
}

/* LD IXL,C */
pub fn instrDD__LD_REGL_C(data: &mut Z80Data) {
    data.IXL = data.C
}

/* LD IXL,D */
pub fn instrDD__LD_REGL_D(data: &mut Z80Data) {
    data.IXL = data.D
}

/* LD IXL,E */
pub fn instrDD__LD_REGL_E(data: &mut Z80Data) {
    data.IXL = data.E
}

/* LD IXL,IXH */
pub fn instrDD__LD_REGL_REGH(data: &mut Z80Data) {
    data.IXL = data.IXH
}

/* LD IXL,IXL */
pub fn instrDD__LD_REGL_REGL(_data: &mut Z80Data) {}

/* LD L,(ix+dd) */
fn_instr_dd_ld_r_i_reg_p_dd!(instrDD__LD_L_iREGpDD, L);

/* LD IXL,A */
pub fn instrDD__LD_REGL_A(data: &mut Z80Data) {
    data.IXL = data.A
}

/* LD (ix+dd),B */
fn_instr_ld_i_reg_p_dd_r8!(instrDD__LD_iREGpDD_B, ix, B);

/* LD (ix+dd),C */
fn_instr_ld_i_reg_p_dd_r8!(instrDD__LD_iREGpDD_C, ix, C);

/* LD (ix+dd),D */
fn_instr_ld_i_reg_p_dd_r8!(instrDD__LD_iREGpDD_D, ix, D);

/* LD (ix+dd),E */
fn_instr_ld_i_reg_p_dd_r8!(instrDD__LD_iREGpDD_E, ix, E);

/* LD (ix+dd),H */
fn_instr_ld_i_reg_p_dd_r8!(instrDD__LD_iREGpDD_H, ix, H);

/* LD (ix+dd),L */
fn_instr_ld_i_reg_p_dd_r8!(instrDD__LD_iREGpDD_L, ix, L);

/* LD (ix+dd),A */
fn_instr_ld_i_reg_p_dd_r8!(instrDD__LD_iREGpDD_A, ix, A);

/* LD A,IXH */
fn_instr_ld_a_r8!(instrDD__LD_A_REGH, IXH);

/* LD A,IXL */
fn_instr_ld_a_r8!(instrDD__LD_A_REGL, IXL);

/* LD A,(ix+dd) */
fn_instr_dd_ld_r_i_reg_p_dd!(instrDD__LD_A_iREGpDD, A);

/* ADD A,IXH */
fn_instr_add_r8!(instrDD__ADD_A_REGH, IXH);

/* ADD A,IXL */
fn_instr_add_r8!(instrDD__ADD_A_REGL, IXL);

/* ADD A,(ix+dd) */
fn_instr_dd_op_a_i_reg_p_dd!(instrDD__ADD_A_iREGpDD, add);

/* ADC A,IXH */
fn_instr_adc_r8!(instrDD__ADC_A_REGH, IXH);

/* ADC A,IXL */
fn_instr_adc_r8!(instrDD__ADC_A_REGL, IXL);

/* ADC A,(ix+dd) */
fn_instr_dd_op_a_i_reg_p_dd!(instrDD__ADC_A_iREGpDD, adc);

/* SUB A,IXH */
fn_instr_sub_r8!(instrDD__SUB_A_REGH, IXH);

/* SUB A,IXL */
fn_instr_sub_r8!(instrDD__SUB_A_REGL, IXL);

/* SUB A,(ix+dd) */
fn_instr_dd_op_a_i_reg_p_dd!(instrDD__SUB_A_iREGpDD, sub);

/* SBC A,IXH */
fn_instr_sbc_r8!(instrDD__SBC_A_REGH, IXH);

/* SBC A,IXL */
fn_instr_sbc_r8!(instrDD__SBC_A_REGL, IXL);

/* SBC A,(ix+dd) */
fn_instr_dd_op_a_i_reg_p_dd!(instrDD__SBC_A_iREGpDD, sbc);

/* AND A,IXH */
fn_instr_and_r8!(instrDD__AND_A_REGH, IXH);

/* AND A,IXL */
fn_instr_and_r8!(instrDD__AND_A_REGL, IXL);

/* AND A,(ix+dd) */
fn_instr_dd_op_a_i_reg_p_dd!(instrDD__AND_A_iREGpDD, and);

/* XOR A,IXH */
fn_instr_xor_r8!(instrDD__XOR_A_REGH, IXH);

/* XOR A,IXL */
fn_instr_xor_r8!(instrDD__XOR_A_REGL, IXL);

/* XOR A,(ix+dd) */
fn_instr_dd_op_a_i_reg_p_dd!(instrDD__XOR_A_iREGpDD, xor);

/* OR A,IXH */
fn_instr_or_r8!(instrDD__OR_A_REGH, IXH);

/* OR A,IXL */
fn_instr_or_r8!(instrDD__OR_A_REGL, IXL);

/* OR A,(ix+dd) */
fn_instr_dd_op_a_i_reg_p_dd!(instrDD__OR_A_iREGpDD, or);

/* CP A,IXH */
fn_instr_cp_r8!(instrDD__CP_A_REGH, IXH);

/* CP A,IXL */
fn_instr_cp_r8!(instrDD__CP_A_REGL, IXL);

/* CP A,(ix+dd) */
fn_instr_dd_op_a_i_reg_p_dd_d!(instrDD__CP_A_iREGpDD, cp);

/* shift DDFDCB */
pub fn instrDD__SHIFT_DDFDCB(_data: &mut Z80Data, _memory: &mut Memory) {}

/* POP ix */
fn_instr_pop_r16!(instrDD__POP_REG, IXL, IXH);

/* EX (SP),ix */
pub fn instrDD__EX_iSP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.sp();
    let byte_temp_l = memory.read_byte(address);
    let sp = data.sp();
    let byte_temp_h = memory.read_byte(sp + 1);
    let sp = data.sp();
    memory.contend_read_no_mreq(sp + 1, 1);
    let sp = data.sp();
    memory.write_byte(sp + 1, data.IXH);
    let address = data.sp();
    memory.write_byte(address, data.IXL);
    let _address = data.sp();
    memory.contend_write_no_mreq_loop(_address, 1, 2);
    data.IXL = byte_temp_l;
    data.IXH = byte_temp_h;
}

/* PUSH ix */
fn_instr_push_r16!(instrDD__PUSH_REG, IXL, IXH);

/* JP ix */
pub fn instrDD__JP_REG(data: &mut Z80Data) {
    data.set_pc(data.ix()); /* NB: NOT INDIRECT! */
}

/* LD SP,ix */
pub fn instrDD__LD_SP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 2);
    data.set_sp(data.ix());
}

/* ADD iy,BC */
pub fn instrFD__ADD_REG_BC(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    // add16(data,  self.iy, data.bc());
    let mut iy = Register16::new(data.IYH, data.IYL);
    let value2 = data.bc();
    add16(data, &mut iy, value2);
    (data.IYH, data.IYL) = iy.result();
}

/* ADD iy,DE */
pub fn instrFD__ADD_REG_DE(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    // add16(data,  self.iy, data.de());
    let mut iy = Register16::new(data.IYH, data.IYL);
    let value2 = data.de();
    add16(data, &mut iy, value2);
    (data.IYH, data.IYL) = iy.result();
}

/* LD iy,nnnn */
pub fn instrFD__LD_REG_NNNN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let b1 = memory.read_byte(address);
    data.inc_pc(1);
    let address = data.pc();
    let b2 = memory.read_byte(address);
    data.inc_pc(1);
    data.set_iy(join_bytes(b2, b1));
}

/* LD (nnnn),iy */
fn_instr_ld_i_nnnn_r16!(instrFD__LD_iNNNN_REG, IYL, IYH);

/* INC iy */
pub fn instrFD__INC_REG(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 2);
    data.inc_iy()
}

/* INC IYH */
pub fn instrFD__INC_REGH(data: &mut Z80Data) {
    data.inc_iyh()
}

/* DEC IYH */
pub fn instrFD__DEC_REGH(data: &mut Z80Data) {
    data.dec_iyh()
}

/* LD IYH,nn */
pub fn instrFD__LD_REGH_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    data.IYH = memory.read_byte(address);
    data.inc_pc(1);
}

/* ADD iy,iy */
pub fn instrFD__ADD_REG_REG(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    // add16(data,  self.iy, data.iy())
    let mut iy = Register16::new(data.IYH, data.IYL);
    let value2 = data.iy();
    add16(data, &mut iy, value2);
    (data.IYH, data.IYL) = iy.result();
}

/* LD iy,(nnnn) */
fn_instr_ld_hl_i_nnnn!(instrFD__LD_REG_iNNNN, IYL, IYH);

/* DEC iy */
pub fn instrFD__DEC_REG(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 2);
    data.dec_iy()
}

/* INC IYL */
pub fn instrFD__INC_REGL(data: &mut Z80Data) {
    data.inc_iyl()
}

/* DEC IYL */
pub fn instrFD__DEC_REGL(data: &mut Z80Data) {
    data.dec_iyl()
}

/* LD IYL,nn */
pub fn instrFD__LD_REGL_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    data.IYL = memory.read_byte(address);
    data.inc_pc(1);
}

/* INC (iy+dd) */
fn_instr_fd_op_i_reg_p_dd!(instrFD__INC_iREGpDD, inc);

/* DEC (iy+dd) */
fn_instr_fd_op_i_reg_p_dd!(instrFD__DEC_iREGpDD, dec);

/* LD (iy+dd),nn */
pub fn instrFD__LD_iREGpDD_NN(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.pc();
    let offset = memory.read_byte(address);
    data.inc_pc(1);
    let address = data.pc();
    let value = memory.read_byte(address);
    let _address = data.pc();
    memory.contend_read_no_mreq_loop(_address, 1, 2);
    data.inc_pc(1);
    memory.write_byte(data.iy() + (sign_extend(offset) as u16), value)
}

/* ADD iy,SP */
pub fn instrFD__ADD_REG_SP(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 7);
    // add16(data,  self.iy, data.sp())
    let mut iy = Register16::new(data.IYH, data.IYL);
    let value2 = data.sp();
    add16(data, &mut iy, value2);
    (data.IYH, data.IYL) = iy.result();
}

/* LD B,IYH */
pub fn instrFD__LD_B_REGH(data: &mut Z80Data) {
    data.B = data.IYH
}

/* LD B,IYL */
pub fn instrFD__LD_B_REGL(data: &mut Z80Data) {
    data.B = data.IYL
}

/* LD B,(iy+dd) */
fn_instr_fd_ld_r_i_reg_p_dd!(instrFD__LD_B_iREGpDD, B);

/* LD C,IYH */
pub fn instrFD__LD_C_REGH(data: &mut Z80Data) {
    data.C = data.IYH
}

/* LD C,IYL */
pub fn instrFD__LD_C_REGL(data: &mut Z80Data) {
    data.C = data.IYL
}

/* LD C,(iy+dd) */
fn_instr_fd_ld_r_i_reg_p_dd!(instrFD__LD_C_iREGpDD, C);

/* LD D,IYH */
pub fn instrFD__LD_D_REGH(data: &mut Z80Data) {
    data.D = data.IYH
}

/* LD D,IYL */
pub fn instrFD__LD_D_REGL(data: &mut Z80Data) {
    data.D = data.IYL
}

/* LD D,(iy+dd) */
fn_instr_fd_ld_r_i_reg_p_dd!(instrFD__LD_D_iREGpDD, D);

/* LD E,IYH */
pub fn instrFD__LD_E_REGH(data: &mut Z80Data) {
    data.E = data.IYH
}

/* LD E,IYL */
pub fn instrFD__LD_E_REGL(data: &mut Z80Data) {
    data.E = data.IYL
}

/* LD E,(iy+dd) */
fn_instr_fd_ld_r_i_reg_p_dd!(instrFD__LD_E_iREGpDD, E);

/* LD IYH,B */
pub fn instrFD__LD_REGH_B(data: &mut Z80Data) {
    data.IYH = data.B
}

/* LD IYH,C */
pub fn instrFD__LD_REGH_C(data: &mut Z80Data) {
    data.IYH = data.C
}

/* LD IYH,D */
pub fn instrFD__LD_REGH_D(data: &mut Z80Data) {
    data.IYH = data.D
}

/* LD IYH,E */
pub fn instrFD__LD_REGH_E(data: &mut Z80Data) {
    data.IYH = data.E
}

/* LD IYH,IYH */
pub fn instrFD__LD_REGH_REGH(_data: &mut Z80Data) {}

/* LD IYH,IYL */
pub fn instrFD__LD_REGH_REGL(data: &mut Z80Data) {
    data.IYH = data.IYL
}

/* LD H,(iy+dd) */
fn_instr_fd_ld_r_i_reg_p_dd!(instrFD__LD_H_iREGpDD, H);

/* LD IYH,A */
pub fn instrFD__LD_REGH_A(data: &mut Z80Data) {
    data.IYH = data.A
}

/* LD IYL,B */
pub fn instrFD__LD_REGL_B(data: &mut Z80Data) {
    data.IYL = data.B
}

/* LD IYL,C */
pub fn instrFD__LD_REGL_C(data: &mut Z80Data) {
    data.IYL = data.C
}

/* LD IYL,D */
pub fn instrFD__LD_REGL_D(data: &mut Z80Data) {
    data.IYL = data.D
}

/* LD IYL,E */
pub fn instrFD__LD_REGL_E(data: &mut Z80Data) {
    data.IYL = data.E
}

/* LD IYL,IYH */
pub fn instrFD__LD_REGL_REGH(data: &mut Z80Data) {
    data.IYL = data.IYH
}

/* LD IYL,IYL */
pub fn instrFD__LD_REGL_REGL(_data: &mut Z80Data) {}

/* LD L,(iy+dd) */
fn_instr_fd_ld_r_i_reg_p_dd!(instrFD__LD_L_iREGpDD, L);

/* LD IYL,A */
pub fn instrFD__LD_REGL_A(data: &mut Z80Data) {
    data.IYL = data.A
}

/* LD (iy+dd),B */
fn_instr_ld_i_reg_p_dd_r8!(instrFD__LD_iREGpDD_B, iy, B);

/* LD (iy+dd),C */
fn_instr_ld_i_reg_p_dd_r8!(instrFD__LD_iREGpDD_C, iy, C);

/* LD (iy+dd),D */
fn_instr_ld_i_reg_p_dd_r8!(instrFD__LD_iREGpDD_D, iy, D);

/* LD (iy+dd),E */
fn_instr_ld_i_reg_p_dd_r8!(instrFD__LD_iREGpDD_E, iy, E);

/* LD (iy+dd),H */
fn_instr_ld_i_reg_p_dd_r8!(instrFD__LD_iREGpDD_H, iy, H);

/* LD (iy+dd),L */
fn_instr_ld_i_reg_p_dd_r8!(instrFD__LD_iREGpDD_L, iy, L);

/* LD (iy+dd),A */
fn_instr_ld_i_reg_p_dd_r8!(instrFD__LD_iREGpDD_A, iy, A);

/* LD A,IYH */
fn_instr_ld_a_r8!(instrFD__LD_A_REGH, IYH);

/* LD A,IYL */
fn_instr_ld_a_r8!(instrFD__LD_A_REGL, IYL);

/* LD A,(iy+dd) */
fn_instr_fd_ld_r_i_reg_p_dd!(instrFD__LD_A_iREGpDD, A);

/* ADD A,IYH */
fn_instr_add_r8!(instrFD__ADD_A_REGH, IYH);

/* ADD A,IYL */
fn_instr_add_r8!(instrFD__ADD_A_REGL, IYL);

/* ADD A,(iy+dd) */
fn_instr_fd_op_a_i_reg_p_dd!(instrFD__ADD_A_iREGpDD, add);

/* ADC A,IYH */
fn_instr_adc_r8!(instrFD__ADC_A_REGH, IYH);

/* ADC A,IYL */
fn_instr_adc_r8!(instrFD__ADC_A_REGL, IYL);

/* ADC A,(iy+dd) */
fn_instr_fd_op_a_i_reg_p_dd!(instrFD__ADC_A_iREGpDD, adc);

/* SUB A,IYH */
fn_instr_sub_r8!(instrFD__SUB_A_REGH, IYH);

/* SUB A,IYL */
fn_instr_sub_r8!(instrFD__SUB_A_REGL, IYL);

/* SUB A,(iy+dd) */
fn_instr_fd_op_a_i_reg_p_dd!(instrFD__SUB_A_iREGpDD, sub);

/* SBC A,IYH */
fn_instr_sbc_r8!(instrFD__SBC_A_REGH, IYH);

/* SBC A,IYL */
fn_instr_sbc_r8!(instrFD__SBC_A_REGL, IYL);

/* SBC A,(iy+dd) */
fn_instr_fd_op_a_i_reg_p_dd!(instrFD__SBC_A_iREGpDD, sbc);

/* AND A,IYH */
fn_instr_and_r8!(instrFD__AND_A_REGH, IYH);

/* AND A,IYL */
fn_instr_and_r8!(instrFD__AND_A_REGL, IYL);

/* AND A,(iy+dd) */
fn_instr_fd_op_a_i_reg_p_dd!(instrFD__AND_A_iREGpDD, and);

/* XOR A,IYH */
fn_instr_xor_r8!(instrFD__XOR_A_REGH, IYH);

/* XOR A,IYL */
fn_instr_xor_r8!(instrFD__XOR_A_REGL, IYL);

/* XOR A,(iy+dd) */
fn_instr_fd_op_a_i_reg_p_dd!(instrFD__XOR_A_iREGpDD, xor);

/* OR A,IYH */
fn_instr_or_r8!(instrFD__OR_A_REGH, IYH);

/* OR A,IYL */
fn_instr_or_r8!(instrFD__OR_A_REGL, IYL);

/* OR A,(iy+dd) */
fn_instr_fd_op_a_i_reg_p_dd!(instrFD__OR_A_iREGpDD, or);

/* CP A,IYH */
fn_instr_cp_r8!(instrFD__CP_A_REGH, IYH);

/* CP A,IYL */
fn_instr_cp_r8!(instrFD__CP_A_REGL, IYL);

/* CP A,(iy+dd) */
fn_instr_fd_op_a_i_reg_p_dd_d!(instrFD__CP_A_iREGpDD, cp);

/* shift DDFDCB */
pub fn instrFD__SHIFT_DDFDCB(_data: &mut Z80Data, _memory: &mut Memory) {}

/* POP iy */
fn_instr_pop_r16!(instrFD__POP_REG, IYL, IYH);

/* EX (SP),iy */
pub fn instrFD__EX_iSP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let address = data.sp();
    let byte_temp_l = memory.read_byte(address);
    let address = data.sp() + 1;
    let byte_temp_h = memory.read_byte(address);
    let _address = data.sp() + 1;
    memory.contend_read_no_mreq(_address, 1);
    let address = data.sp() + 1;
    memory.write_byte(address, data.IYH);
    let address = data.sp();
    memory.write_byte(address, data.IYL);
    let _address = data.sp();
    memory.contend_write_no_mreq_loop(_address, 1, 2);
    data.IYL = byte_temp_l;
    data.IYH = byte_temp_h;
}

/* PUSH iy */
fn_instr_push_r16!(instrFD__PUSH_REG, IYL, IYH);

/* JP iy */
pub fn instrFD__JP_REG(data: &mut Z80Data) {
    data.set_pc(data.iy()); /* NB: NOT INDIRECT! */
}

/* LD SP,iy */
pub fn instrFD__LD_SP_REG(data: &mut Z80Data, memory: &mut Memory) {
    let _address = data.ir();
    memory.contend_read_no_mreq_loop(_address, 1, 2);
    data.set_sp(data.iy());
}

/* LD B,RLC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rlc_i_reg_p_dd!(instrDDCB__LD_B_RLC_iREGpDD, B);

/* LD C,RLC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rlc_i_reg_p_dd!(instrDDCB__LD_C_RLC_iREGpDD, C);

/* LD D,RLC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rlc_i_reg_p_dd!(instrDDCB__LD_D_RLC_iREGpDD, D);

/* LD E,RLC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rlc_i_reg_p_dd!(instrDDCB__LD_E_RLC_iREGpDD, E);

/* LD H,RLC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rlc_i_reg_p_dd!(instrDDCB__LD_H_RLC_iREGpDD, H);

/* LD L,RLC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rlc_i_reg_p_dd!(instrDDCB__LD_L_RLC_iREGpDD, L);

/* RLC (REGISTER+dd) */
fn_instr_ddcb_op_i_reg_p_dd!(instrDDCB__RLC_iREGpDD, rlc);

/* LD A,RLC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rlc_i_reg_p_dd!(instrDDCB__LD_A_RLC_iREGpDD, A);

/* LD B,RRC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rrc_i_reg_p_dd!(instrDDCB__LD_B_RRC_iREGpDD, B);

/* LD C,RRC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rrc_i_reg_p_dd!(instrDDCB__LD_C_RRC_iREGpDD, C);

/* LD D,RRC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rrc_i_reg_p_dd!(instrDDCB__LD_D_RRC_iREGpDD, D);

/* LD E,RRC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rrc_i_reg_p_dd!(instrDDCB__LD_E_RRC_iREGpDD, E);

/* LD H,RRC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rrc_i_reg_p_dd!(instrDDCB__LD_H_RRC_iREGpDD, H);

/* LD L,RRC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rrc_i_reg_p_dd!(instrDDCB__LD_L_RRC_iREGpDD, L);

/* RRC (REGISTER+dd) */
fn_instr_ddcb_op_i_reg_p_dd!(instrDDCB__RRC_iREGpDD, rrc);

/* LD A,RRC (REGISTER+dd) */
fn_instr_ddcb_ld_r_rrc_i_reg_p_dd!(instrDDCB__LD_A_RRC_iREGpDD, A);

/* LD B,RL (REGISTER+dd) */
fn_instr_ddcb_ld_r_rl_i_reg_p_dd!(instrDDCB__LD_B_RL_iREGpDD, B);

/* LD C,RL (REGISTER+dd) */
fn_instr_ddcb_ld_r_rl_i_reg_p_dd!(instrDDCB__LD_C_RL_iREGpDD, C);

/* LD D,RL (REGISTER+dd) */
fn_instr_ddcb_ld_r_rl_i_reg_p_dd!(instrDDCB__LD_D_RL_iREGpDD, D);

/* LD E,RL (REGISTER+dd) */
fn_instr_ddcb_ld_r_rl_i_reg_p_dd!(instrDDCB__LD_E_RL_iREGpDD, E);

/* LD H,RL (REGISTER+dd) */
fn_instr_ddcb_ld_r_rl_i_reg_p_dd!(instrDDCB__LD_H_RL_iREGpDD, H);

/* LD L,RL (REGISTER+dd) */
fn_instr_ddcb_ld_r_rl_i_reg_p_dd!(instrDDCB__LD_L_RL_iREGpDD, L);

/* RL (REGISTER+dd) */
fn_instr_ddcb_op_i_reg_p_dd!(instrDDCB__RL_iREGpDD, rl);

/* LD A,RL (REGISTER+dd) */
fn_instr_ddcb_ld_r_rl_i_reg_p_dd!(instrDDCB__LD_A_RL_iREGpDD, A);

/* LD B,RR (REGISTER+dd) */
fn_instr_ddcb_ld_r_rr_i_reg_p_dd!(instrDDCB__LD_B_RR_iREGpDD, B);

/* LD C,RR (REGISTER+dd) */
fn_instr_ddcb_ld_r_rr_i_reg_p_dd!(instrDDCB__LD_C_RR_iREGpDD, C);

/* LD D,RR (REGISTER+dd) */
fn_instr_ddcb_ld_r_rr_i_reg_p_dd!(instrDDCB__LD_D_RR_iREGpDD, D);

/* LD E,RR (REGISTER+dd) */
fn_instr_ddcb_ld_r_rr_i_reg_p_dd!(instrDDCB__LD_E_RR_iREGpDD, E);

/* LD H,RR (REGISTER+dd) */
fn_instr_ddcb_ld_r_rr_i_reg_p_dd!(instrDDCB__LD_H_RR_iREGpDD, H);

/* LD L,RR (REGISTER+dd) */
fn_instr_ddcb_ld_r_rr_i_reg_p_dd!(instrDDCB__LD_L_RR_iREGpDD, L);

/* RR (REGISTER+dd) */
fn_instr_ddcb_op_i_reg_p_dd!(instrDDCB__RR_iREGpDD, rr);

/* LD A,RR (REGISTER+dd) */
fn_instr_ddcb_ld_r_rr_i_reg_p_dd!(instrDDCB__LD_A_RR_iREGpDD, A);

/* LD B,SLA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sla_i_reg_p_dd!(instrDDCB__LD_B_SLA_iREGpDD, B);

/* LD C,SLA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sla_i_reg_p_dd!(instrDDCB__LD_C_SLA_iREGpDD, C);

/* LD D,SLA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sla_i_reg_p_dd!(instrDDCB__LD_D_SLA_iREGpDD, D);

/* LD E,SLA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sla_i_reg_p_dd!(instrDDCB__LD_E_SLA_iREGpDD, E);

/* LD H,SLA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sla_i_reg_p_dd!(instrDDCB__LD_H_SLA_iREGpDD, H);

/* LD L,SLA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sla_i_reg_p_dd!(instrDDCB__LD_L_SLA_iREGpDD, L);

/* SLA (REGISTER+dd) */
fn_instr_ddcb_op_i_reg_p_dd!(instrDDCB__SLA_iREGpDD, sla);

/* LD A,SLA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sla_i_reg_p_dd!(instrDDCB__LD_A_SLA_iREGpDD, A);

/* LD B,SRA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sra_i_reg_p_dd!(instrDDCB__LD_B_SRA_iREGpDD, B);

/* LD C,SRA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sra_i_reg_p_dd!(instrDDCB__LD_C_SRA_iREGpDD, C);

/* LD D,SRA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sra_i_reg_p_dd!(instrDDCB__LD_D_SRA_iREGpDD, D);

/* LD E,SRA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sra_i_reg_p_dd!(instrDDCB__LD_E_SRA_iREGpDD, E);

/* LD H,SRA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sra_i_reg_p_dd!(instrDDCB__LD_H_SRA_iREGpDD, H);

/* LD L,SRA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sra_i_reg_p_dd!(instrDDCB__LD_L_SRA_iREGpDD, L);

/* SRA (REGISTER+dd) */
fn_instr_ddcb_op_i_reg_p_dd!(instrDDCB__SRA_iREGpDD, sra);

/* LD A,SRA (REGISTER+dd) */
fn_instr_ddcb_ld_r_sra_i_reg_p_dd!(instrDDCB__LD_A_SRA_iREGpDD, A);

/* LD B,SLL (REGISTER+dd) */
fn_instr_ddcb_ld_r_sll_i_reg_p_dd!(instrDDCB__LD_B_SLL_iREGpDD, B);

/* LD C,SLL (REGISTER+dd) */
fn_instr_ddcb_ld_r_sll_i_reg_p_dd!(instrDDCB__LD_C_SLL_iREGpDD, C);

/* LD D,SLL (REGISTER+dd) */
fn_instr_ddcb_ld_r_sll_i_reg_p_dd!(instrDDCB__LD_D_SLL_iREGpDD, D);

/* LD E,SLL (REGISTER+dd) */
fn_instr_ddcb_ld_r_sll_i_reg_p_dd!(instrDDCB__LD_E_SLL_iREGpDD, E);

/* LD H,SLL (REGISTER+dd) */
fn_instr_ddcb_ld_r_sll_i_reg_p_dd!(instrDDCB__LD_H_SLL_iREGpDD, H);

/* LD L,SLL (REGISTER+dd) */
fn_instr_ddcb_ld_r_sll_i_reg_p_dd!(instrDDCB__LD_L_SLL_iREGpDD, L);

/* SLL (REGISTER+dd) */
fn_instr_ddcb_op_i_reg_p_dd!(instrDDCB__SLL_iREGpDD, sll);

/* LD A,SLL (REGISTER+dd) */
fn_instr_ddcb_ld_r_sll_i_reg_p_dd!(instrDDCB__LD_A_SLL_iREGpDD, A);

/* LD B,SRL (REGISTER+dd) */
fn_instr_ddcb_ld_r_srl_i_reg_p_dd!(instrDDCB__LD_B_SRL_iREGpDD, B);

/* LD C,SRL (REGISTER+dd) */
fn_instr_ddcb_ld_r_srl_i_reg_p_dd!(instrDDCB__LD_C_SRL_iREGpDD, C);

/* LD D,SRL (REGISTER+dd) */
fn_instr_ddcb_ld_r_srl_i_reg_p_dd!(instrDDCB__LD_D_SRL_iREGpDD, D);

/* LD E,SRL (REGISTER+dd) */
fn_instr_ddcb_ld_r_srl_i_reg_p_dd!(instrDDCB__LD_E_SRL_iREGpDD, E);

/* LD H,SRL (REGISTER+dd) */
fn_instr_ddcb_ld_r_srl_i_reg_p_dd!(instrDDCB__LD_H_SRL_iREGpDD, H);

/* LD L,SRL (REGISTER+dd) */
fn_instr_ddcb_ld_r_srl_i_reg_p_dd!(instrDDCB__LD_L_SRL_iREGpDD, L);

/* SRL (REGISTER+dd) */
fn_instr_ddcb_op_i_reg_p_dd!(instrDDCB__SRL_iREGpDD, srl);

/* LD A,SRL (REGISTER+dd) */
fn_instr_ddcb_ld_r_srl_i_reg_p_dd!(instrDDCB__LD_A_SRL_iREGpDD, A);

/* BIT 0,(REGISTER+dd) */
fn_instr_ddcb_bit_n_i_reg_p_dd!(instrDDCB__BIT_0_iREGpDD, 0);

/* BIT 1,(REGISTER+dd) */
fn_instr_ddcb_bit_n_i_reg_p_dd!(instrDDCB__BIT_1_iREGpDD, 1);

/* BIT 2,(REGISTER+dd) */
fn_instr_ddcb_bit_n_i_reg_p_dd!(instrDDCB__BIT_2_iREGpDD, 2);

/* BIT 3,(REGISTER+dd) */
fn_instr_ddcb_bit_n_i_reg_p_dd!(instrDDCB__BIT_3_iREGpDD, 3);

/* BIT 4,(REGISTER+dd) */
fn_instr_ddcb_bit_n_i_reg_p_dd!(instrDDCB__BIT_4_iREGpDD, 4);

/* BIT 5,(REGISTER+dd) */
fn_instr_ddcb_bit_n_i_reg_p_dd!(instrDDCB__BIT_5_iREGpDD, 5);

/* BIT 6,(REGISTER+dd) */
fn_instr_ddcb_bit_n_i_reg_p_dd!(instrDDCB__BIT_6_iREGpDD, 6);

/* BIT 7,(REGISTER+dd) */
fn_instr_ddcb_bit_n_i_reg_p_dd!(instrDDCB__BIT_7_iREGpDD, 7);

/* LD B,RES 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_0_i_reg_p_dd!(instrDDCB__LD_B_RES_0_iREGpDD, B);

/* LD C,RES 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_0_i_reg_p_dd!(instrDDCB__LD_C_RES_0_iREGpDD, C);

/* LD D,RES 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_0_i_reg_p_dd!(instrDDCB__LD_D_RES_0_iREGpDD, D);

/* LD E,RES 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_0_i_reg_p_dd!(instrDDCB__LD_E_RES_0_iREGpDD, E);

/* LD H,RES 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_0_i_reg_p_dd!(instrDDCB__LD_H_RES_0_iREGpDD, H);

/* LD L,RES 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_0_i_reg_p_dd!(instrDDCB__LD_L_RES_0_iREGpDD, L);

/* RES 0,(REGISTER+dd) */
fn_instr_ddcb_res_n_i_reg_p_dd!(instrDDCB__RES_0_iREGpDD, 0xfe);

/* LD A,RES 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_0_i_reg_p_dd!(instrDDCB__LD_A_RES_0_iREGpDD, A);

/* LD B,RES 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_1_i_reg_p_dd!(instrDDCB__LD_B_RES_1_iREGpDD, B);

/* LD C,RES 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_1_i_reg_p_dd!(instrDDCB__LD_C_RES_1_iREGpDD, C);

/* LD D,RES 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_1_i_reg_p_dd!(instrDDCB__LD_D_RES_1_iREGpDD, D);

/* LD E,RES 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_1_i_reg_p_dd!(instrDDCB__LD_E_RES_1_iREGpDD, E);

/* LD H,RES 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_1_i_reg_p_dd!(instrDDCB__LD_H_RES_1_iREGpDD, H);

/* LD L,RES 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_1_i_reg_p_dd!(instrDDCB__LD_L_RES_1_iREGpDD, L);

/* RES 1,(REGISTER+dd) */
fn_instr_ddcb_res_n_i_reg_p_dd!(instrDDCB__RES_1_iREGpDD, 0xfd);

/* LD A,RES 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_1_i_reg_p_dd!(instrDDCB__LD_A_RES_1_iREGpDD, A);

/* LD B,RES 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_2_i_reg_p_dd!(instrDDCB__LD_B_RES_2_iREGpDD, B);

/* LD C,RES 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_2_i_reg_p_dd!(instrDDCB__LD_C_RES_2_iREGpDD, C);

/* LD D,RES 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_2_i_reg_p_dd!(instrDDCB__LD_D_RES_2_iREGpDD, D);

/* LD E,RES 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_2_i_reg_p_dd!(instrDDCB__LD_E_RES_2_iREGpDD, E);

/* LD H,RES 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_2_i_reg_p_dd!(instrDDCB__LD_H_RES_2_iREGpDD, H);

/* LD L,RES 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_2_i_reg_p_dd!(instrDDCB__LD_L_RES_2_iREGpDD, L);

/* RES 2,(REGISTER+dd) */
fn_instr_ddcb_res_n_i_reg_p_dd!(instrDDCB__RES_2_iREGpDD, 0xfb);

/* LD A,RES 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_2_i_reg_p_dd!(instrDDCB__LD_A_RES_2_iREGpDD, A);

/* LD B,RES 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_3_i_reg_p_dd!(instrDDCB__LD_B_RES_3_iREGpDD, B);

/* LD C,RES 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_3_i_reg_p_dd!(instrDDCB__LD_C_RES_3_iREGpDD, C);

/* LD D,RES 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_3_i_reg_p_dd!(instrDDCB__LD_D_RES_3_iREGpDD, D);

/* LD E,RES 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_3_i_reg_p_dd!(instrDDCB__LD_E_RES_3_iREGpDD, E);

/* LD H,RES 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_3_i_reg_p_dd!(instrDDCB__LD_H_RES_3_iREGpDD, H);

/* LD L,RES 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_3_i_reg_p_dd!(instrDDCB__LD_L_RES_3_iREGpDD, L);

/* RES 3,(REGISTER+dd) */
fn_instr_ddcb_res_n_i_reg_p_dd!(instrDDCB__RES_3_iREGpDD, 0xf7);

/* LD A,RES 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_3_i_reg_p_dd!(instrDDCB__LD_A_RES_3_iREGpDD, A);

/* LD B,RES 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_4_i_reg_p_dd!(instrDDCB__LD_B_RES_4_iREGpDD, B);

/* LD C,RES 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_4_i_reg_p_dd!(instrDDCB__LD_C_RES_4_iREGpDD, C);

/* LD D,RES 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_4_i_reg_p_dd!(instrDDCB__LD_D_RES_4_iREGpDD, D);

/* LD E,RES 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_4_i_reg_p_dd!(instrDDCB__LD_E_RES_4_iREGpDD, E);

/* LD H,RES 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_4_i_reg_p_dd!(instrDDCB__LD_H_RES_4_iREGpDD, H);

/* LD L,RES 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_4_i_reg_p_dd!(instrDDCB__LD_L_RES_4_iREGpDD, L);

/* RES 4,(REGISTER+dd) */
fn_instr_ddcb_res_n_i_reg_p_dd!(instrDDCB__RES_4_iREGpDD, 0xef);

/* LD A,RES 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_4_i_reg_p_dd!(instrDDCB__LD_A_RES_4_iREGpDD, A);

/* LD B,RES 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_5_i_reg_p_dd!(instrDDCB__LD_B_RES_5_iREGpDD, B);

/* LD C,RES 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_5_i_reg_p_dd!(instrDDCB__LD_C_RES_5_iREGpDD, C);

/* LD D,RES 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_5_i_reg_p_dd!(instrDDCB__LD_D_RES_5_iREGpDD, D);

/* LD E,RES 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_5_i_reg_p_dd!(instrDDCB__LD_E_RES_5_iREGpDD, E);

/* LD H,RES 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_5_i_reg_p_dd!(instrDDCB__LD_H_RES_5_iREGpDD, H);

/* LD L,RES 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_5_i_reg_p_dd!(instrDDCB__LD_L_RES_5_iREGpDD, L);

/* RES 5,(REGISTER+dd) */
fn_instr_ddcb_res_n_i_reg_p_dd!(instrDDCB__RES_5_iREGpDD, 0xdf);

/* LD A,RES 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_5_i_reg_p_dd!(instrDDCB__LD_A_RES_5_iREGpDD, A);

/* LD B,RES 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_6_i_reg_p_dd!(instrDDCB__LD_B_RES_6_iREGpDD, B);

/* LD C,RES 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_6_i_reg_p_dd!(instrDDCB__LD_C_RES_6_iREGpDD, C);

/* LD D,RES 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_6_i_reg_p_dd!(instrDDCB__LD_D_RES_6_iREGpDD, D);

/* LD E,RES 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_6_i_reg_p_dd!(instrDDCB__LD_E_RES_6_iREGpDD, E);

/* LD H,RES 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_6_i_reg_p_dd!(instrDDCB__LD_H_RES_6_iREGpDD, H);

/* LD L,RES 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_6_i_reg_p_dd!(instrDDCB__LD_L_RES_6_iREGpDD, L);

/* RES 6,(REGISTER+dd) */
fn_instr_ddcb_res_n_i_reg_p_dd!(instrDDCB__RES_6_iREGpDD, 0xbf);

/* LD A,RES 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_6_i_reg_p_dd!(instrDDCB__LD_A_RES_6_iREGpDD, A);

/* LD B,RES 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_7_i_reg_p_dd!(instrDDCB__LD_B_RES_7_iREGpDD, B);

/* LD C,RES 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_7_i_reg_p_dd!(instrDDCB__LD_C_RES_7_iREGpDD, C);

/* LD D,RES 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_7_i_reg_p_dd!(instrDDCB__LD_D_RES_7_iREGpDD, D);

/* LD E,RES 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_7_i_reg_p_dd!(instrDDCB__LD_E_RES_7_iREGpDD, E);

/* LD H,RES 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_7_i_reg_p_dd!(instrDDCB__LD_H_RES_7_iREGpDD, H);

/* LD L,RES 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_7_i_reg_p_dd!(instrDDCB__LD_L_RES_7_iREGpDD, L);

/* RES 7,(REGISTER+dd) */
fn_instr_ddcb_res_n_i_reg_p_dd!(instrDDCB__RES_7_iREGpDD, 0x7f);

/* LD A,RES 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_res_7_i_reg_p_dd!(instrDDCB__LD_A_RES_7_iREGpDD, A);

/* LD B,SET 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_0_i_reg_p_dd!(instrDDCB__LD_B_SET_0_iREGpDD, B);

/* LD C,SET 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_0_i_reg_p_dd!(instrDDCB__LD_C_SET_0_iREGpDD, C);

/* LD D,SET 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_0_i_reg_p_dd!(instrDDCB__LD_D_SET_0_iREGpDD, D);

/* LD E,SET 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_0_i_reg_p_dd!(instrDDCB__LD_E_SET_0_iREGpDD, E);

/* LD H,SET 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_0_i_reg_p_dd!(instrDDCB__LD_H_SET_0_iREGpDD, H);

/* LD L,SET 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_0_i_reg_p_dd!(instrDDCB__LD_L_SET_0_iREGpDD, L);

/* SET 0,(REGISTER+dd) */
fn_instr_ddcb_set_n_i_reg_p_dd!(instrDDCB__SET_0_iREGpDD, 0x01);

/* LD A,SET 0,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_0_i_reg_p_dd!(instrDDCB__LD_A_SET_0_iREGpDD, A);

/* LD B,SET 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_1_i_reg_p_dd!(instrDDCB__LD_B_SET_1_iREGpDD, B);

/* LD C,SET 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_1_i_reg_p_dd!(instrDDCB__LD_C_SET_1_iREGpDD, C);

/* LD D,SET 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_1_i_reg_p_dd!(instrDDCB__LD_D_SET_1_iREGpDD, D);

/* LD E,SET 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_1_i_reg_p_dd!(instrDDCB__LD_E_SET_1_iREGpDD, E);

/* LD H,SET 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_1_i_reg_p_dd!(instrDDCB__LD_H_SET_1_iREGpDD, H);

/* LD L,SET 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_1_i_reg_p_dd!(instrDDCB__LD_L_SET_1_iREGpDD, L);

/* SET 1,(REGISTER+dd) */
fn_instr_ddcb_set_n_i_reg_p_dd!(instrDDCB__SET_1_iREGpDD, 0x02);

/* LD A,SET 1,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_1_i_reg_p_dd!(instrDDCB__LD_A_SET_1_iREGpDD, A);

/* LD B,SET 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_2_i_reg_p_dd!(instrDDCB__LD_B_SET_2_iREGpDD, B);

/* LD C,SET 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_2_i_reg_p_dd!(instrDDCB__LD_C_SET_2_iREGpDD, C);

/* LD D,SET 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_2_i_reg_p_dd!(instrDDCB__LD_D_SET_2_iREGpDD, D);

/* LD E,SET 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_2_i_reg_p_dd!(instrDDCB__LD_E_SET_2_iREGpDD, E);

/* LD H,SET 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_2_i_reg_p_dd!(instrDDCB__LD_H_SET_2_iREGpDD, H);

/* LD L,SET 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_2_i_reg_p_dd!(instrDDCB__LD_L_SET_2_iREGpDD, L);

/* SET 2,(REGISTER+dd) */
fn_instr_ddcb_set_n_i_reg_p_dd!(instrDDCB__SET_2_iREGpDD, 0x04);

/* LD A,SET 2,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_2_i_reg_p_dd!(instrDDCB__LD_A_SET_2_iREGpDD, A);

/* LD B,SET 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_3_i_reg_p_dd!(instrDDCB__LD_B_SET_3_iREGpDD, B);

/* LD C,SET 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_3_i_reg_p_dd!(instrDDCB__LD_C_SET_3_iREGpDD, C);

/* LD D,SET 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_3_i_reg_p_dd!(instrDDCB__LD_D_SET_3_iREGpDD, D);

/* LD E,SET 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_3_i_reg_p_dd!(instrDDCB__LD_E_SET_3_iREGpDD, E);

/* LD H,SET 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_3_i_reg_p_dd!(instrDDCB__LD_H_SET_3_iREGpDD, H);

/* LD L,SET 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_3_i_reg_p_dd!(instrDDCB__LD_L_SET_3_iREGpDD, L);

/* SET 3,(REGISTER+dd) */
fn_instr_ddcb_set_n_i_reg_p_dd!(instrDDCB__SET_3_iREGpDD, 0x08);

/* LD A,SET 3,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_3_i_reg_p_dd!(instrDDCB__LD_A_SET_3_iREGpDD, A);

/* LD B,SET 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_4_i_reg_p_dd!(instrDDCB__LD_B_SET_4_iREGpDD, B);

/* LD C,SET 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_4_i_reg_p_dd!(instrDDCB__LD_C_SET_4_iREGpDD, C);

/* LD D,SET 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_4_i_reg_p_dd!(instrDDCB__LD_D_SET_4_iREGpDD, D);

/* LD E,SET 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_4_i_reg_p_dd!(instrDDCB__LD_E_SET_4_iREGpDD, E);

/* LD H,SET 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_4_i_reg_p_dd!(instrDDCB__LD_H_SET_4_iREGpDD, H);

/* LD L,SET 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_4_i_reg_p_dd!(instrDDCB__LD_L_SET_4_iREGpDD, L);

/* SET 4,(REGISTER+dd) */
fn_instr_ddcb_set_n_i_reg_p_dd!(instrDDCB__SET_4_iREGpDD, 0x10);

/* LD A,SET 4,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_4_i_reg_p_dd!(instrDDCB__LD_A_SET_4_iREGpDD, A);

/* LD B,SET 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_5_i_reg_p_dd!(instrDDCB__LD_B_SET_5_iREGpDD, B);

/* LD C,SET 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_5_i_reg_p_dd!(instrDDCB__LD_C_SET_5_iREGpDD, C);

/* LD D,SET 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_5_i_reg_p_dd!(instrDDCB__LD_D_SET_5_iREGpDD, D);

/* LD E,SET 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_5_i_reg_p_dd!(instrDDCB__LD_E_SET_5_iREGpDD, E);

/* LD H,SET 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_5_i_reg_p_dd!(instrDDCB__LD_H_SET_5_iREGpDD, H);

/* LD L,SET 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_5_i_reg_p_dd!(instrDDCB__LD_L_SET_5_iREGpDD, L);

/* SET 5,(REGISTER+dd) */
fn_instr_ddcb_set_n_i_reg_p_dd!(instrDDCB__SET_5_iREGpDD, 0x20);

/* LD A,SET 5,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_5_i_reg_p_dd!(instrDDCB__LD_A_SET_5_iREGpDD, A);

/* LD B,SET 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_6_i_reg_p_dd!(instrDDCB__LD_B_SET_6_iREGpDD, B);

/* LD C,SET 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_6_i_reg_p_dd!(instrDDCB__LD_C_SET_6_iREGpDD, C);

/* LD D,SET 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_6_i_reg_p_dd!(instrDDCB__LD_D_SET_6_iREGpDD, D);

/* LD E,SET 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_6_i_reg_p_dd!(instrDDCB__LD_E_SET_6_iREGpDD, E);

/* LD H,SET 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_6_i_reg_p_dd!(instrDDCB__LD_H_SET_6_iREGpDD, H);

/* LD L,SET 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_6_i_reg_p_dd!(instrDDCB__LD_L_SET_6_iREGpDD, L);

/* SET 6,(REGISTER+dd) */
fn_instr_ddcb_set_n_i_reg_p_dd!(instrDDCB__SET_6_iREGpDD, 0x40);

/* LD A,SET 6,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_6_i_reg_p_dd!(instrDDCB__LD_A_SET_6_iREGpDD, A);

/* LD B,SET 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_7_i_reg_p_dd!(instrDDCB__LD_B_SET_7_iREGpDD, B);

/* LD C,SET 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_7_i_reg_p_dd!(instrDDCB__LD_C_SET_7_iREGpDD, C);

/* LD D,SET 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_7_i_reg_p_dd!(instrDDCB__LD_D_SET_7_iREGpDD, D);

/* LD E,SET 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_7_i_reg_p_dd!(instrDDCB__LD_E_SET_7_iREGpDD, E);

/* LD H,SET 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_7_i_reg_p_dd!(instrDDCB__LD_H_SET_7_iREGpDD, H);

/* LD L,SET 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_7_i_reg_p_dd!(instrDDCB__LD_L_SET_7_iREGpDD, L);

/* SET 7,(REGISTER+dd) */
fn_instr_ddcb_set_n_i_reg_p_dd!(instrDDCB__SET_7_iREGpDD, 0x80);

/* LD A,SET 7,(REGISTER+dd) */
fn_instr_ddcb_ld_r_set_7_i_reg_p_dd!(instrDDCB__LD_A_SET_7_iREGpDD, A);