#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SCGC7 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `FLEXBUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FLEXBUSR {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl FLEXBUSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FLEXBUSR::_0 => false,
FLEXBUSR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FLEXBUSR {
match value {
false => FLEXBUSR::_0,
true => FLEXBUSR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == FLEXBUSR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == FLEXBUSR::_1
}
}
#[doc = "Possible values of the field `DMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAR {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl DMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DMAR::_0 => false,
DMAR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DMAR {
match value {
false => DMAR::_0,
true => DMAR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == DMAR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == DMAR::_1
}
}
#[doc = "Possible values of the field `MPU`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MPUR {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl MPUR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MPUR::_0 => false,
MPUR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MPUR {
match value {
false => MPUR::_0,
true => MPUR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == MPUR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == MPUR::_1
}
}
#[doc = "Possible values of the field `SDRAMC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SDRAMCR {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl SDRAMCR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SDRAMCR::_0 => false,
SDRAMCR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SDRAMCR {
match value {
false => SDRAMCR::_0,
true => SDRAMCR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SDRAMCR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SDRAMCR::_1
}
}
#[doc = "Values that can be written to the field `FLEXBUS`"]
pub enum FLEXBUSW {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl FLEXBUSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FLEXBUSW::_0 => false,
FLEXBUSW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FLEXBUSW<'a> {
w: &'a mut W,
}
impl<'a> _FLEXBUSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FLEXBUSW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FLEXBUSW::_0)
}
#[doc = "Clock enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FLEXBUSW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DMA`"]
pub enum DMAW {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl DMAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DMAW::_0 => false,
DMAW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DMAW<'a> {
w: &'a mut W,
}
impl<'a> _DMAW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DMAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(DMAW::_0)
}
#[doc = "Clock enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(DMAW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MPU`"]
pub enum MPUW {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl MPUW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MPUW::_0 => false,
MPUW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _MPUW<'a> {
w: &'a mut W,
}
impl<'a> _MPUW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MPUW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(MPUW::_0)
}
#[doc = "Clock enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(MPUW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SDRAMC`"]
pub enum SDRAMCW {
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl SDRAMCW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SDRAMCW::_0 => false,
SDRAMCW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SDRAMCW<'a> {
w: &'a mut W,
}
impl<'a> _SDRAMCW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SDRAMCW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SDRAMCW::_0)
}
#[doc = "Clock enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SDRAMCW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - FlexBus Clock Gate Control"]
#[inline]
pub fn flexbus(&self) -> FLEXBUSR {
FLEXBUSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - DMA Clock Gate Control"]
#[inline]
pub fn dma(&self) -> DMAR {
DMAR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - MPU Clock Gate Control"]
#[inline]
pub fn mpu(&self) -> MPUR {
MPUR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - SDRAMC Clock Gate Control"]
#[inline]
pub fn sdramc(&self) -> SDRAMCR {
SDRAMCR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 6 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - FlexBus Clock Gate Control"]
#[inline]
pub fn flexbus(&mut self) -> _FLEXBUSW {
_FLEXBUSW { w: self }
}
#[doc = "Bit 1 - DMA Clock Gate Control"]
#[inline]
pub fn dma(&mut self) -> _DMAW {
_DMAW { w: self }
}
#[doc = "Bit 2 - MPU Clock Gate Control"]
#[inline]
pub fn mpu(&mut self) -> _MPUW {
_MPUW { w: self }
}
#[doc = "Bit 3 - SDRAMC Clock Gate Control"]
#[inline]
pub fn sdramc(&mut self) -> _SDRAMCW {
_SDRAMCW { w: self }
}
}