1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
#![allow(non_snake_case, non_upper_case_globals)]
#![allow(non_camel_case_types)]
//! PGC
//!
//! Used by: imxrt1061, imxrt1062, imxrt1064
use crate::RWRegister;
#[cfg(not(feature = "nosync"))]
use core::marker::PhantomData;
/// PGC Mega Control Register
pub mod MEGA_CTRL {
/// Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up
pub mod PCR {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: Do not switch off power even if pdn_req is asserted.
pub const PCR_0: u32 = 0b0;
/// 0b1: Switch off power when pdn_req is asserted.
pub const PCR_1: u32 = 0b1;
}
}
}
/// PGC Mega Power Up Sequence Control Register
pub mod MEGA_PUPSCR {
/// After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b)
pub mod SW {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (6 bits: 0x3f << 0)
pub const mask: u32 = 0x3f << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation
pub mod SW2ISO {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (6 bits: 0x3f << 8)
pub const mask: u32 = 0x3f << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// PGC Mega Pull Down Sequence Control Register
pub mod MEGA_PDNSCR {
/// After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation
pub mod ISO {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (6 bits: 0x3f << 0)
pub const mask: u32 = 0x3f << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
/// After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b)
pub mod ISO2SW {
/// Offset (8 bits)
pub const offset: u32 = 8;
/// Mask (6 bits: 0x3f << 8)
pub const mask: u32 = 0x3f << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values (empty)
pub mod RW {}
}
}
/// PGC Mega Power Gating Controller Status Register
pub mod MEGA_SR {
/// Power status
pub mod PSR {
/// Offset (0 bits)
pub const offset: u32 = 0;
/// Mask (1 bit: 1 << 0)
pub const mask: u32 = 1 << offset;
/// Read-only values (empty)
pub mod R {}
/// Write-only values (empty)
pub mod W {}
/// Read-write values
pub mod RW {
/// 0b0: The target subsystem was not powered down for the previous power-down request.
pub const PSR_0: u32 = 0b0;
/// 0b1: The target subsystem was powered down for the previous power-down request.
pub const PSR_1: u32 = 0b1;
}
}
}
/// PGC CPU Control Register
pub mod CPU_CTRL {
pub use super::MEGA_CTRL::PCR;
}
/// PGC CPU Power Up Sequence Control Register
pub mod CPU_PUPSCR {
pub use super::MEGA_PUPSCR::SW;
pub use super::MEGA_PUPSCR::SW2ISO;
}
/// PGC CPU Pull Down Sequence Control Register
pub mod CPU_PDNSCR {
pub use super::MEGA_PDNSCR::ISO;
pub use super::MEGA_PDNSCR::ISO2SW;
}
/// PGC CPU Power Gating Controller Status Register
pub mod CPU_SR {
pub use super::MEGA_SR::PSR;
}
#[repr(C)]
pub struct RegisterBlock {
_reserved1: [u32; 136],
/// PGC Mega Control Register
pub MEGA_CTRL: RWRegister<u32>,
/// PGC Mega Power Up Sequence Control Register
pub MEGA_PUPSCR: RWRegister<u32>,
/// PGC Mega Pull Down Sequence Control Register
pub MEGA_PDNSCR: RWRegister<u32>,
/// PGC Mega Power Gating Controller Status Register
pub MEGA_SR: RWRegister<u32>,
_reserved2: [u32; 28],
/// PGC CPU Control Register
pub CPU_CTRL: RWRegister<u32>,
/// PGC CPU Power Up Sequence Control Register
pub CPU_PUPSCR: RWRegister<u32>,
/// PGC CPU Pull Down Sequence Control Register
pub CPU_PDNSCR: RWRegister<u32>,
/// PGC CPU Power Gating Controller Status Register
pub CPU_SR: RWRegister<u32>,
}
pub struct ResetValues {
pub MEGA_CTRL: u32,
pub MEGA_PUPSCR: u32,
pub MEGA_PDNSCR: u32,
pub MEGA_SR: u32,
pub CPU_CTRL: u32,
pub CPU_PUPSCR: u32,
pub CPU_PDNSCR: u32,
pub CPU_SR: u32,
}
#[cfg(not(feature = "nosync"))]
pub struct Instance {
pub(crate) addr: u32,
pub(crate) _marker: PhantomData<*const RegisterBlock>,
}
#[cfg(not(feature = "nosync"))]
impl ::core::ops::Deref for Instance {
type Target = RegisterBlock;
#[inline(always)]
fn deref(&self) -> &RegisterBlock {
unsafe { &*(self.addr as *const _) }
}
}
#[cfg(feature = "rtfm")]
unsafe impl Send for Instance {}