hc32f448_driver_sys 0.1.0

Provide driver function binding for HDSC's HC32F448 MCU.
Documentation 
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/* automatically generated by rust-bindgen 0.72.1 */

pub const SWDT_CNT_PERIOD256: u32 = 0;
pub const SWDT_CNT_PERIOD4096: u32 = 1;
pub const SWDT_CNT_PERIOD16384: u32 = 2;
pub const SWDT_CNT_PERIOD65536: u32 = 3;
pub const SWDT_CLK_DIV1: u32 = 0;
pub const SWDT_CLK_DIV16: u32 = 64;
pub const SWDT_CLK_DIV32: u32 = 80;
pub const SWDT_CLK_DIV64: u32 = 96;
pub const SWDT_CLK_DIV128: u32 = 112;
pub const SWDT_CLK_DIV256: u32 = 128;
pub const SWDT_CLK_DIV2048: u32 = 176;
pub const SWDT_RANGE_0TO25PCT: u32 = 256;
pub const SWDT_RANGE_25TO50PCT: u32 = 512;
pub const SWDT_RANGE_0TO50PCT: u32 = 768;
pub const SWDT_RANGE_50TO75PCT: u32 = 1024;
pub const SWDT_RANGE_0TO25PCT_50TO75PCT: u32 = 1280;
pub const SWDT_RANGE_25TO75PCT: u32 = 1536;
pub const SWDT_RANGE_0TO75PCT: u32 = 1792;
pub const SWDT_RANGE_75TO100PCT: u32 = 2048;
pub const SWDT_RANGE_0TO25PCT_75TO100PCT: u32 = 2304;
pub const SWDT_RANGE_25TO50PCT_75TO100PCT: u32 = 2560;
pub const SWDT_RANGE_0TO50PCT_75TO100PCT: u32 = 2816;
pub const SWDT_RANGE_50TO100PCT: u32 = 3072;
pub const SWDT_RANGE_0TO25PCT_50TO100PCT: u32 = 3328;
pub const SWDT_RANGE_25TO100PCT: u32 = 3584;
pub const SWDT_RANGE_0TO100PCT: u32 = 3840;
pub const SWDT_LPM_CNT_CONT: u32 = 0;
pub const SWDT_LPM_CNT_STOP: u32 = 65536;
pub const SWDT_EXP_TYPE_INT: u32 = 0;
pub const SWDT_EXP_TYPE_RST: u32 = 2147483648;
pub const SWDT_FLAG_UDF: u32 = 65536;
pub const SWDT_FLAG_REFRESH: u32 = 131072;
pub const SWDT_FLAG_ALL: u32 = 196608;
pub const en_flag_status_t_RESET: en_flag_status_t = 0;
pub const en_flag_status_t_SET: en_flag_status_t = 1;
#[doc = " @brief Flag status"]
pub type en_flag_status_t = ::core::ffi::c_uint;
#[doc = " @brief SWDT Init structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_swdt_init_t {
    #[doc = "< Specifies the counting period of SWDT.\nThis parameter can be a value of @ref SWDT_Count_Period"]
    pub u32CountPeriod: u32,
    #[doc = "< Specifies the clock division factor of SWDT.\nThis parameter can be a value of @ref SWDT_Clock_Division"]
    pub u32ClockDiv: u32,
    #[doc = "< Specifies the allow refresh range of SWDT.\nThis parameter can be a value of @ref SWDT_Refresh_Range"]
    pub u32RefreshRange: u32,
    #[doc = "< Specifies the count state in Low Power Mode (Sleep/Stop Mode).\nThis parameter can be a value of @ref SWDT_LPM_Count"]
    pub u32LPMCount: u32,
    #[doc = "< Specifies the type of exception response for SWDT.\nThis parameter can be a value of @ref SWDT_Exception_Type"]
    pub u32ExceptionType: u32,
}
unsafe extern "C" {
    pub fn SWDT_Init(pstcSwdtInit: *const stc_swdt_init_t) -> i32;
    pub fn SWDT_FeedDog();
    pub fn SWDT_GetStatus(u32Flag: u32) -> en_flag_status_t;
    pub fn SWDT_ClearStatus(u32Flag: u32) -> i32;
}